Editing Bus (computing) (section)

===Minis and micros===
[[Digital Equipment Corporation]] (DEC) further reduced cost for mass-produced [[minicomputer]]s, and [[Memory-mapped I/O|mapped peripherals]] into the memory bus, so that the input and output devices appeared to be memory locations.  This was implemented in the [[Unibus]] of the [[PDP-11]] around 1969.<ref>{{cite conference |title= A New Architecture for Mini-Computers—The DEC PDP-11 |author1= C. Gordon Bell |author2= R. Cady |author3= H. McFarland |author4= B. Delagi |author5= J. O'Laughlin |author6= R. Noonan |author7= W. Wulf |conference= Spring Joint Computer Conference |pages= 657–675 |year= 1970 |url= http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf |url-status= live |archive-url= https://web.archive.org/web/20111127001221/http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf |archive-date= 2011-11-27 }}</ref>

Early [[microcomputer]] bus systems were essentially a passive [[backplane]] connected directly or through buffer amplifiers to the pins of the [[CPU]]. Memory and other devices would be added to the bus using the same address and data pins as the CPU itself used, connected in parallel.  Communication was controlled by the CPU, which read and wrote data from the devices as if they are blocks of memory, using the same instructions, all timed by a central clock controlling the speed of the CPU. Still, devices [[interrupt]]ed the CPU by signaling on separate CPU pins.

For instance, a [[disk drive]] controller would signal the CPU that new data was ready to be read, at which point the CPU would move the data by reading the memory location that corresponded to the disk drive. Almost all early microcomputers were built in this fashion, starting with the [[S-100 bus]] in the [[Altair 8800]] computer system.

In some instances, most notably in the [[IBM PC]], although similar physical architecture can be employed, instructions to access peripherals (<code>in</code> and <code>out</code>) and memory (<code>mov</code> and others) have not been made uniform at all, and still generate distinct CPU signals, that could be used to implement a separate I/O bus.

These simple bus systems had a serious drawback when used for general-purpose computers.  All the equipment on the bus had to talk at the same speed, as it shared a single clock.

Increasing the speed of the CPU becomes harder, because the speed of all the devices must increase as well. When it is not practical or economical to have all devices as fast as the CPU, the CPU must either enter a [[wait state]], or work at a slower clock frequency temporarily,<ref name="bray-aug">{{cite book|last= Bray|first= Andrew C.|author2= Dickens, Adrian C.|author3= Holmes, Mark A.|title= The Advanced User Guide for the BBC Microcomputer|url= http://www.nvg.org/bbc/doc/BBCAdvancedUserGuide-PDF.zip|format= zipped PDF|access-date= 2008-03-28|year= 1983|publisher= Cambridge Microcomputer Centre|location= Cambridge, UK|isbn= 0-946827-00-1|pages= 442–443|chapter= 28. The One Megahertz bus|url-status= dead|archive-url= https://web.archive.org/web/20060114042612/http://www.nvg.org/bbc/doc/BBCAdvancedUserGuide-PDF.zip|archive-date= 2006-01-14}}</ref> to talk to other devices in the computer. While acceptable in [[embedded systems]], this problem was not tolerated for long in general-purpose, user-expandable computers.

Such bus systems are also difficult to configure when constructed from common off-the-shelf equipment.  Typically each added [[expansion card]] requires many [[Jumper (computing)|jumpers]] in order to set memory addresses, I/O addresses, interrupt priorities, and interrupt numbers.