Editing Cell (processor) (section)

===Element Interconnect Bus (EIB)===
The EIB is a communication bus internal to the Cell processor which connects the various on-chip system elements: the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of 12 participants in the PS3 (the number of SPU can vary in industrial applications). The EIB also includes an arbitration unit which functions as a set of traffic lights. In some documents, IBM refers to EIB participants as 'units'.

The EIB is presently implemented as a circular ring consisting of four 16-byte-wide unidirectional channels which counter-rotate in pairs. When traffic patterns permit, each channel can convey up to three transactions concurrently. As the EIB runs at half the system clock rate the effective channel rate is 16 bytes every two system clocks. At maximum [[Concurrency (computer science)|concurrency]], with three active transactions on each of the four rings, the peak instantaneous EIB bandwidth is 96 bytes per clock (12 concurrent transactions × 16 bytes wide / 2 system clocks per transfer). While this figure is often quoted in IBM literature, it is unrealistic to simply scale this number by processor clock speed. The arbitration unit [[#Bandwidth assessment|imposes additional constraints]].

IBM Senior Engineer [[David Krolak]], EIB lead designer, explains the concurrency model:
{{blockquote|A ring can start a new op every three cycles. Each transfer always takes eight beats. That was one of the simplifications we made, it's optimized for streaming a lot of data. If you do small ops, it does not work quite as well. If you think of eight-car trains running around this track, as long as the trains aren't running into each other, they can coexist on the track.<ref name="Krolak">{{Cite web |date=2005-12-06 |title=Meet the experts: David Krolak on the Cell Broadband Engine EIB bus |url=http://www.ibm.com/developerworks/power/library/pa-expert9/ |access-date=2007-03-18 |publisher=IBM}}</ref>}}

Each participant on the EIB has one 16-byte read port and one 16-byte write port. The limit for a single participant is to read and write at a rate of 16 bytes per EIB clock (for simplicity often regarded 8 bytes per system clock). Each SPU processor contains a dedicated [[Direct memory access|DMA]] management queue capable of scheduling long sequences of transactions to various endpoints without interfering with the SPU's ongoing computations; these DMA queues can be managed locally or remotely as well, providing additional flexibility in the control model.

Data flows on an EIB channel stepwise around the ring. Since there are twelve participants, the total number of steps around the channel back to the point of origin is twelve. Six steps is the longest distance between any pair of participants. An EIB channel is not permitted to convey data requiring more than six steps; such data must take the shorter route around the circle in the other direction. The number of steps involved in sending the packet has very little impact on transfer latency: the clock speed driving the steps is very fast relative to other considerations. However, longer communication distances are detrimental to the overall performance of the EIB as they reduce available concurrency. <!-- thinking about the Krolak interview, I have no justification for using the term hops, they could be opening the circuit end to end for the transaction; still, it seems more likely that it functions in hops and I do not feel like rewriting this passage right now; changed to steps and stepwise after seeing a comment by HappyVR using this term instead ~~~~ -->

Despite IBM's original desire to implement the EIB as a more powerful cross-bar, the circular configuration they adopted to spare resources rarely represents a limiting factor on the performance of the Cell chip as a whole. In the worst case, the programmer must take extra care to schedule communication patterns where the EIB is able to function at high concurrency levels.

David Krolak explained:
{{blockquote|Well, in the beginning, early in the development process, several people were pushing for a crossbar switch, and the way the bus is designed, you could actually pull out the EIB and put in a crossbar switch if you were willing to devote more silicon space on the chip to wiring. We had to find a balance between connectivity and area, and there just was not enough room to put a full crossbar switch in. So we came up with this ring structure which we think is very interesting. It fits within the area constraints and still has very impressive bandwidth.<ref name="Krolak" />}}

====Bandwidth assessment====
At 3.2&nbsp;GHz, each channel flows at a rate of 25.6&nbsp;GB/s. Viewing the EIB in isolation from the system elements it connects, achieving twelve concurrent transactions at this flow rate works out to an abstract EIB bandwidth of 307.2&nbsp;GB/s. Based on this view many IBM publications depict available EIB bandwidth as "greater than 300&nbsp;GB/s". This number reflects the peak instantaneous EIB bandwidth scaled by processor frequency.<ref>{{Cite web |title=Cell Multiprocessor Communication Network: Built for Speed |url=http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf |url-status=dead |archive-url=https://web.archive.org/web/20070107202021/http://hpc.pnl.gov/people/fabrizio/papers/ieeemicro-cell.pdf |archive-date=January 7, 2007 |access-date=March 22, 2007 |publisher=IEEE}}</ref>

However, other technical restrictions are involved in the arbitration mechanism for packets accepted onto the bus. The IBM Systems Performance group explained:
{{blockquote|Each unit on the EIB can simultaneously send and receive 16 bytes of data every bus cycle. The maximum data bandwidth of the entire EIB is limited by the maximum rate at which addresses are snooped across all units in the system, which is one per bus cycle. Since each snooped address request can potentially transfer up to 128 bytes, the theoretical peak data bandwidth on the EIB at 3.2&nbsp;GHz is 128Bx1.6&nbsp;GHz {{=}} 204.8&nbsp;GB/s.<ref name="pacellperf" />}}

This quote apparently represents the full extent of IBM's public disclosure of this mechanism and its impact. The EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults are not well described in the documentation set as yet made public by IBM.{{Citation needed|date=June 2009}}

In practice, effective EIB bandwidth can also be limited by the ring participants involved. While each of the nine processing cores can sustain 25.6&nbsp;GB/s read and write concurrently, the memory interface controller (MIC) is tied to a pair of XDR memory channels permitting a maximum flow of 25.6&nbsp;GB/s for reads and writes combined and the two IO controllers are documented as supporting a peak combined input speed of 25.6&nbsp;GB/s and a peak combined output speed of 35&nbsp;GB/s.

To add further to the confusion, some older publications cite EIB bandwidth assuming a 4&nbsp;GHz system clock. This reference frame results in an instantaneous EIB bandwidth figure of 384&nbsp;GB/s and an arbitration-limited bandwidth figure of 256&nbsp;GB/s.

All things considered the theoretic 204.8&nbsp;GB/s number most often cited is the best one to bear in mind. The ''IBM Systems Performance'' group has demonstrated SPU-centric data flows achieving 197&nbsp;GB/s on a Cell processor running at 3.2&nbsp;GHz so this number is a fair reflection on practice as well.<ref name="pacellperf" />