Editing Electronic design automation (section)

=== Manufacturing preparation ===
* [[Mask data preparation]] or MDP - The generation of actual [[Photolithography|lithography]] [[photomask]]s, utilised to physically manufacture the chip.
** ''Chip finishing'' which includes custom designations and structures to improve [[design for manufacturability (IC)|manufacturability]] of the layout. Examples of the latter are a seal ring and filler structures.<ref name="Layout">{{cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|pages=102–110|chapter=Chap. 3.3: Mask Data: Layout Post Processing|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0|s2cid=215840278}}</ref> 
** Producing a ''reticle layout'' with test patterns and alignment marks. 
**''Layout-to-mask preparation'' that enhances layout data with graphics operations, such as [[resolution enhancement techniques]] (RET) – methods for increasing the quality of the final [[photomask]]. This also includes [[optical proximity correction]]  (OPC) or [[inverse lithography technology]] (ILT)  – the up-front compensation for [[diffraction]] and [[Interference (wave propagation)|interference]] effects occurring later when chip is manufactured using this mask.
** ''[[Mask generation]]'' – The generation of flat mask image from hierarchical design.
** ''[[Automatic test pattern generation]]'' or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
** ''[[Built-in self-test]]'' or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design