Editing Endianness (section)

== Hardware ==

Many historical and extant processors use a big-endian memory representation, either exclusively or as a design option. The [[IBM System/360]] uses big-endian byte order, as do its successors [[System/370]], [[ESA/390]], and [[z/Architecture]]. The [[PDP-10]] uses big-endian addressing for byte-oriented instructions. The [[IBM Series/1]] minicomputer uses big-endian byte order. The Motorola [[Motorola 6800|6800]] / 6801, the [[6809]] and the [[68000 series]] of processors use the big-endian format. Solely big-endian architectures include the IBM z/Architecture and [[OpenRISC]]. The [[PDP-11]] minicomputer, however, uses little-endian byte order, as does its [[VAX]] successor.

The [[Datapoint 2200]] used simple bit-serial logic with little-endian to facilitate [[carry propagation]]. When Intel developed the [[8008]] microprocessor for Datapoint, they used little-endian for compatibility. However, as Intel was unable to deliver the 8008 in time, Datapoint used a [[medium-scale integration]] equivalent, but the little-endianness was retained in most Intel designs, including the [[MCS-48]] and the [[8086]] and its [[x86]] successors, including [[IA-32]] and [[x86-64]] processors.<ref>{{cite web |last=House |first=David |title=Oral History Panel on the Development and Promotion of the Intel 8008 Microprocessor |url=http://archive.computerhistory.org/resources/text/Oral_History/Intel_8008/Intel_8008_1.oral_history.2006.102657982.pdf#page=5 |publisher=[[Computer History Museum]] |access-date=23 April 2014 |author2=Faggin, Federico |author3=Feeney, Hal |author4=Gelbach, Ed |author5=Hoff, Ted |author6=Mazor, Stan |author7=Smith, Hank |page=b5 |date=2006-09-21 |archive-date=2014-06-29 |archive-url=https://web.archive.org/web/20140629084907/http://archive.computerhistory.org/resources/text/Oral_History/Intel_8008/Intel_8008_1.oral_history.2006.102657982.pdf#page=5 |url-status=live }}</ref><ref name="Lunde2009">{{cite book |first = Ken |last = Lunde |title = CJKV Information Processing |url = https://books.google.com/books?id=SA92uQqTB-AC&pg=PA29 |access-date=21 May 2013 |date = 13 January 2009 |publisher = O'Reilly Media, Inc. |isbn = 978-0-596-51447-1 |page = 29 }}</ref> The [[MOS Technology 6502]] family (including [[Western Design Center]] [[65802]] and [[65C816]]), the Zilog [[Z80]] (including [[Z180]] and [[eZ80]]), the [[Altera]] [[Nios II]], the [[Atmel AVR]], the [[Andes Technology]] NDS32, the [[Qualcomm Hexagon]], and many other processors and processor families are also little-endian.

The Intel [[8051]], unlike other Intel processors, expects 16-bit addresses for LJMP and LCALL in big-endian format; however, xCALL instructions store the return address onto the stack in little-endian format.<ref>{{cite web|url=http://www.keil.com/support/man/docs/c51/c51_xe.htm|title=Cx51 User's Guide: E. Byte Ordering|website=keil.com|access-date=2015-03-28|archive-date=2015-04-02|archive-url=https://web.archive.org/web/20150402094251/http://www.keil.com/support/man/docs/c51/c51_xe.htm|url-status=live}}</ref>

=== Bi-endianness ===

Some instruction set architectures feature a setting which allows for switchable endianness in data fetches and stores, instruction fetches, or both; those instruction set architectures are referred to as ''bi-endian''. Architectures that support switchable endianness include [[PowerPC]]/[[Power ISA]], [[SPARC]] V9, [[ARM architecture|ARM]] versions 3 and above, [[DEC Alpha]], [[MIPS architecture|MIPS]], [[Intel i860]], [[PA-RISC]], [[SuperH|SuperH SH-4]], [[IA-64]], [[C-Sky]], and [[RISC-V]]. This feature can improve performance or simplify the logic of networking devices and software. The word ''bi-endian'', when said of hardware, denotes the capability of the machine to compute or pass data in either endian format.

Many of these architectures can be switched via software to default to a specific endian format (usually done when the computer starts up); however, on some systems, the default endianness is selected by hardware on the motherboard and cannot be changed via software (e.g. Alpha, which runs only in big-endian mode on the [[Cray T3E]]).

[[IBM AIX]] and [[IBM i]] run in big-endian mode on bi-endian Power ISA; [[Linux]] originally ran in big-endian mode, but by 2019, IBM had transitioned to little-endian mode for Linux to ease the porting of Linux software from x86 to Power.<ref>{{cite web |title=Little endian and Linux on IBM Power Systems |url=https://developer.ibm.com/articles/l-power-little-endian-faq-trs/ |date=2016-06-16 |website=IBM |author=Jeff Scheel |access-date=2022-03-27 |archive-date=2022-03-27 |archive-url=https://web.archive.org/web/20220327025540/https://developer.ibm.com/articles/l-power-little-endian-faq-trs/ |url-status=live }}</ref><ref>{{cite web |last1=Timothy Prickett Morgan |title=The Transition To RHEL 8 Begins On Power Systems |url=https://www.itjungle.com/2019/06/10/the-transition-to-rhel-8-begins-on-power-systems/ |website=ITJungle |date=10 June 2019 |access-date=26 March 2022 |archive-date=24 January 2022 |archive-url=https://web.archive.org/web/20220124063316/https://www.itjungle.com/2019/06/10/the-transition-to-rhel-8-begins-on-power-systems/ |url-status=live }}</ref> SPARC has no relevant little-endian deployment, as both [[Oracle Solaris]] and Linux run in big-endian mode on bi-endian SPARC systems, and can be considered big-endian in practice. ARM, C-Sky, and RISC-V have no relevant big-endian deployments, and can be considered little-endian in practice.

The term ''bi-endian'' refers primarily to how a processor treats data accesses. Instruction accesses (fetches of instruction words) on a given processor may still assume a fixed endianness, even if data accesses are fully bi-endian, though this is not always the case, such as on Intel's [[IA-64]]-based Itanium CPU, which allows both.

Some nominally bi-endian CPUs require motherboard help to fully switch endianness. For instance, the 32-bit desktop-oriented [[PowerPC]] processors in little-endian mode act as little-endian from the point of view of the executing programs, but they require the motherboard to perform a 64-bit swap across all 8 byte lanes to ensure that the little-endian view of things will apply to [[I/O]] devices. In the absence of this unusual motherboard hardware, device driver software must write to different addresses to undo the incomplete transformation and also must perform a normal byte swap.{{or|date=November 2023}}

Some CPUs, such as many PowerPC processors intended for embedded use and almost all SPARC processors, allow per-page choice of endianness.

SPARC processors since the late 1990s (SPARC v9 compliant processors) allow data endianness to be chosen with each individual instruction that loads from or stores to memory.

The [[ARM architecture]] supports two big-endian modes, called ''BE-8'' and ''BE-32''.<ref>{{cite web|title=Differences between BE-32 and BE-8 buses|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html|access-date=2019-02-10|archive-date=2019-02-12|archive-url=https://web.archive.org/web/20190212070549/http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html|url-status=live}}</ref> CPUs up to ARMv5 only support BE-32 or word-invariant mode. Here any naturally aligned 32-bit access works like in little-endian mode, but access to a byte or 16-bit word is redirected to the corresponding address and unaligned access is not allowed. ARMv6 introduces BE-8 or byte-invariant mode, where access to a single byte works as in little-endian mode, but accessing a 16-bit, 32-bit or (starting with ARMv8) 64-bit word results in a byte swap of the data. This simplifies unaligned memory access as well as memory-mapped access to registers other than 32-bit.

Many processors have instructions to convert a word in a register to the opposite endianness, that is, they swap the order of the bytes in a 16-, 32- or 64-bit word. 

Recent Intel x86 and x86-64 architecture CPUs have a MOVBE instruction ([[Intel Core]] since generation 4, after [[Intel Atom|Atom]]),<ref>{{cite web |title = How to detect New Instruction support in the 4th generation Intel® Core™ processor family |url = https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf |access-date = 2 May 2017 |archive-date = 20 March 2016 |archive-url = https://web.archive.org/web/20160320222513/https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf |url-status = live }}</ref> which fetches a big-endian format word from memory or writes a word into memory in big-endian format. These processors are otherwise thoroughly little-endian.

There are also devices which use different formats in different places. For instance, the BQ27421 [[Texas Instruments]] battery gauge uses the little-endian format for its registers and the big-endian format for its [[random-access memory]].

[[SPARC]] historically used big-endian until version 9, which is bi-endian. Similarly early IBM POWER processors were big-endian, but the [[PowerPC]] and [[Power ISA]] descendants are now bi-endian. The [[ARM architecture]] was little-endian before version 3 when it became bi-endian.

=== Floating point ===

Although many processors use little-endian storage for all types of data (integer, floating point), there are a number of hardware architectures where [[floating-point]] numbers are represented in big-endian form while integers are represented in little-endian form.<ref>{{citation |title=Floating-Point Formats |author-first=John J. G. |author-last=Savard |date=2018 |orig-year=2005 |work=quadibloc |url=http://www.quadibloc.com/comp/cp0201.htm |access-date=2018-07-16 |url-status=live |archive-url=https://web.archive.org/web/20180703001709/http://www.quadibloc.com/comp/cp0201.htm |archive-date=2018-07-03}}</ref> There are [[ARM architecture|ARM]] processors that have mixed-endian floating-point representation for double-precision numbers: each of the two 32-bit words is stored as little-endian, but the most significant word is stored first. [[VAX]] floating point stores little-endian 16-bit words in big-endian order. Because there have been many floating-point formats with no network standard representation for them, the [[External Data Representation|XDR]] standard uses big-endian IEEE 754 as its representation. It may therefore appear strange that the widespread [[IEEE 754]] floating-point standard does not specify endianness.<ref>{{cite web |title = pack – convert a list into a binary representation |url = http://www.perl.com/doc/manual/html/pod/perlfunc/pack.html |access-date = 2009-02-04 |archive-date = 2009-02-18 |archive-url = https://web.archive.org/web/20090218010333/http://perl.com/doc/manual/html/pod/perlfunc/pack.html |url-status = live }}</ref> Theoretically, this means that even standard IEEE floating-point data written by one machine might not be readable by another. However, on modern standard computers (i.e., implementing IEEE 754), one may safely assume that the endianness is the same for floating-point numbers as for integers, making the conversion straightforward regardless of data type. Small [[embedded system]]s using special floating-point formats may be another matter, however.

=== Variable-length data ===

Most instructions considered so far contain the size (lengths) of their [[operand]]s within the [[operation code]]. Frequently available operand lengths are 1, 2, 4, 8, or 16 bytes. But there are also architectures where the length of an operand may be held in a separate field of the instruction or with the operand itself, e.g. by means of a [[word mark (computer hardware)|word mark]]. Such an approach allows operand lengths up to 256 bytes or larger. The data types of such operands are character strings or [[binary-coded decimal|BCD]]. Machines able to manipulate such data with one instruction (e.g. compare, add) include the [[IBM 1401]], [[IBM 1410|1410]], [[IBM 1620|1620]], [[System/360]], [[System/370]], [[ESA/390]], and [[z/Architecture]], all of them of type big-endian.

=== Middle-endian ===

Numerous other orderings, generically called ''middle-endian'' or ''mixed-endian'', are possible.

The [[PDP-11]] is in principle a 16-bit little-endian system. The instructions to convert between floating-point and integer values in the optional floating-point processor of the PDP-11/45, PDP-11/70, and in some later processors, stored 32-bit "double precision integer long" values with the 16-bit halves swapped from the expected little-endian order. The [[UNIX]] [[C (programming language)|C]] compiler used the same format for 32-bit long integers. This ordering is known as ''PDP-endian''.<ref>{{cite book|url=http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf |archive-date=2022-10-09 |url-status=live|title=PDP-11/45 Processor Handbook|page=165|year=1973|publisher=[[Digital Equipment Corporation]]}}</ref>

UNIX was one of the first systems to allow the same code to be compiled for platforms with different internal representations. One of the first programs converted was supposed to print out {{code|Unix}}, but on the Series/1 it printed {{code|nUxi}} instead.<ref name=":0">{{cite journal |last1=Jalics|first1=Paul J. |last2=Heines|first2=Thomas S. |title = Transporting a portable operating system: UNIX to an IBM minicomputer |journal=Communications of the ACM|date=1 December 1983|volume=26|issue=12|pages=1066–1072|doi=10.1145/358476.358504|s2cid=15558835 |doi-access=free}}</ref>

A way to interpret this endianness is that it stores a 32-bit integer as two little-endian 16-bit words, with a big-endian word ordering:

{| class="wikitable"
|+ Storage of a 32-bit integer, <kbd>0x0A0B0C0D</kbd>, on a PDP-11
|-
! scope="col" | byte offset
! scope="col" | 8-bit value
! scole="col" | 16-bit little-endian value
|-
! scope="row" | 0
| <kbd>0B<sub>h</sub></kbd>
| rowspan="2" | <kbd>0A0B<sub>h</sub></kbd>
|-
! scope="row" | 1
| <kbd>0A<sub>h</sub></kbd>
|-
! scope="row" | 2
| <kbd>0D<sub>h</sub></kbd>
| rowspan="2" | <kbd>0C0D<sub>h</sub></kbd>
|-
! scope="row" | 3
| <kbd>0C<sub>h</sub></kbd>
|}

[[Segment descriptors]] of [[IA-32]] and compatible processors keep a 32-bit base address of the segment stored in little-endian order, but in four nonconsecutive bytes, at relative positions 2, 3, 4 and 7 of the descriptor start.<ref>{{Cite tech report|title=AMD64 Architecture Programmer's Manual Volume 2: System Programming|page=80|url=http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf|year=2013|archiveurl=https://web.archive.org/web/20180218024045/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf|archivedate=2018-02-18}}</ref>