Editing Instruction cycle (section)

==Fetch stage==
The fetch stage is the same for each instruction:

# The PC contains the address of the instruction to be fetched.
# This address is copied to the MAR, where this address is used to poll for the location of the instruction in memory.
# The CU sends a signal to the [[control bus]] to read the memory at the address in MAR - the data read is placed in the [[Bus (computing)|data bus]].<ref>{{Cite book |last=Aryal |first=Er. Hari |url=https://www.ioenotes.edu.np/media/notes/computer-organization-and-architecture-coa/Chapter2-Central-Processing-Unit.pdf |title=Central Processing Unit}}</ref>
# The data is transferred to the CPU via the data bus, where it's loaded into the MDR - at this stage, the PC increments by one.
# The contents (instruction to-be-executed) of the MDR are copied into the CIR (where the instruction opcode and data operand can be decoded).