Editing Integrated circuit (section)

=== Fabrication ===
{{Main|Semiconductor device fabrication|l1=Semiconductor fabrication}}
[[File:Silicon chip 3d.png|right|thumb|Rendering of a small [[standard cell]] with three metal layers ([[dielectric]] has been removed). The sand-colored structures are metal [[Interconnects (integrated circuits)|interconnect]], with the vertical pillars being contacts, typically plugs of [[tungsten]]. The reddish structures are polysilicon gates, and the solid at the bottom is the [[Monocrystalline silicon|crystalline silicon]] bulk.]]
[[File:Cmos-chip structure in 2000s (en).svg|right|thumb|Schematic structure of a [[CMOS]] chip, as built in the early 2000s. The graphic shows LDD-MISFET's on an SOI substrate with five metallization layers and solder bump for flip-chip bonding. It also shows the section for [[FEOL]] (front-end of line), [[BEOL]] (back-end of line) and first parts of back-end process.]]

The [[semiconductor]]s of the [[periodic table]] of the [[chemical element]]s were identified as the most likely materials for a ''[[Solid-state electronics|solid-state]] [[vacuum tube]]''. Starting with [[copper(I) oxide|copper oxide]], proceeding to [[germanium]], then [[silicon]], the materials were systematically studied in the 1940s and 1950s. Today, [[monocrystalline silicon]] is the main [[Substrate (printing)|substrate]] used for ICs although some III-V [[compound semiconductor|compounds of the periodic table]] such as [[gallium arsenide]] are used for specialized applications like [[Light-emitting diode|LEDs]], [[laser]]s, [[solar cell]]s and the highest-speed integrated circuits. It took decades to perfect methods of creating [[crystal]]s with minimal [[Crystal defects|defects]] in semiconducting materials' [[crystal structure]].

[[Semiconductor]] ICs are fabricated in a [[planar process]] which includes three key process steps{{snd}} [[photolithography]], deposition (such as [[chemical vapor deposition]]), and [[Etching (microfabrication)|etching]]. The main process steps are supplemented by doping and cleaning. More recent or high-performance ICs may instead use [[multigate device|multi-gate]] [[FinFET]] or [[GAAFET]] transistors instead of planar ones, starting at the 22&nbsp;nm node (Intel) or 16/14&nbsp;nm nodes.<ref>{{cite web | title=16nm/14nm FinFETs: Enabling The New Electronics Frontier | website=electronicdesign.com| url=https://www.electronicdesign.com/technologies/embedded/digital-ics/article/21795644/16nm14nm-finfets-enabling-the-new-electronics-frontier | date=January 17, 2013}}</ref>

[[Monocrystalline silicon|Mono-crystal silicon]] [[wafer (electronics)|wafers]] are used in most applications (or for special applications, other semiconductors such as [[gallium arsenide]] are used). The wafer need not be entirely silicon. [[Photolithography]] is used to mark different areas of the substrate to be [[Doping (semiconductor)|doped]] or to have polysilicon, insulators or metal (typically aluminium or copper) tracks deposited on them. [[Dopant]]s are impurities intentionally introduced to a semiconductor to modulate its electronic properties. Doping is the process of adding dopants to a semiconductor material.
{{anchor|circuitLayers}} 
* Integrated circuits are composed of many overlapping layers, each defined by photolithography, and normally shown in different colors. Some layers mark where various dopants are diffused into the substrate (called diffusion layers), some define where additional ions are implanted (implant layers), some define the conductors (doped polysilicon or metal layers), and some define the connections between the conducting layers (via or contact layers). All components are constructed from a specific combination of these layers.
* In a self-aligned [[CMOS]] process, a [[transistor]] is formed wherever the gate layer (polysilicon or metal) [[CMOS#Example: NAND gate in physical layout|crosses]] a diffusion layer (this is called [[#The self-aligned gate|"the self-aligned gate"]]).<ref name="selfAlignedCmos">{{cite book |last1=Mead |first1=Carver |last2=Conway |first2=Lynn |year=1991 |title=Introduction to VLSI systems |publisher=Addison Wesley Publishing Company |isbn=978-0-201-04358-7 |oclc=634332043 |url=https://archive.org/details/introductiontovl00mead |author-link1 = Carver Mead | author-link2 = Lynn Conway}}</ref>{{rp|p.1 (see Fig. 1.1)}}
* [[capacitor|Capacitive structures]], in form very much like the [[Parallel-plate capacitor|parallel conducting plates]] of a traditional electrical [[capacitor]], are formed according to the area of the "plates", with insulating material between the plates. Capacitors of a wide range of sizes are common on ICs.
* Meandering stripes of varying lengths are sometimes used to form on-chip [[resistor]]s, though most [[logic circuit]]s do not need any resistors. The ratio of the length of the resistive structure to its width, combined with its sheet resistivity, determines the resistance.
* More rarely, [[inductor|inductive structures]] can be built as tiny on-chip coils, or simulated by [[gyrator]]s.

Since a CMOS device only draws current on the ''[[State transition function|transition]]'' between [[boolean algebra (logic)|logic]] [[State (computer science)|states]], CMOS devices consume much less current than [[bipolar junction transistor]] devices.

A [[random-access memory]] is the most regular type of integrated circuit; the highest density devices are thus memories; but even a [[microprocessor]] will have memory on the chip. (See the regular array structure at the bottom of the first image.{{Which|date=October 2018}}) Although the structures are intricate – with widths which have been shrinking for decades – the layers remain much thinner than the device widths. The layers of material are fabricated much like a photographic process, although light [[wave]]s in the [[visible spectrum]] cannot be used to "expose" a layer of material, as they would be too large for the features. Thus [[photon]]s of higher frequencies (typically [[ultraviolet]]) are used to create the patterns for each layer. Because each feature is so small, [[electron microscope]]s are essential tools for a [[Industrial processes|process]] engineer who might be [[debugging]] a fabrication process.

Each device is tested before packaging using automated test equipment (ATE), in a process known as [[wafer testing]], or wafer probing. The wafer is then cut into rectangular blocks, each of which is called a ''[[die (integrated circuit)|die]]''. Each good die (plural ''dice'', ''dies'', or ''die'') is then connected into a package using [[aluminium]] (or gold) [[Wire bonding|bond wires]] which are [[Thermosonic bonding|thermosonically bonded]]<ref><!-- Coucoulas, A., http://commons.wikimedia.org/wiki/File:Hot_Work_Ultrasonic_(Thermosonic)_Bonding_549-556.pdf DELETED--> [https://sites.google.com/site/hotworkultrasonicbonding/ "Hot Work Ultrasonic Bonding – A Method Of Facilitating Metal Flow By Restoration Processes"], Proc. 20th IEEE Electronic Components Conf. Washington, D.C., May 1970, pp. 549–556.]</ref> to ''pads'', usually found around the edge of the die. [[Thermosonic bonding]] was first introduced by A. Coucoulas which provided a reliable means of forming these vital electrical connections to the outside world. After packaging, the devices go through final testing on the same or similar ATE used during wafer probing. [[Industrial CT scanning]] can also be used. Test cost can account for over 25% of the cost of fabrication on lower-cost products, but can be negligible on low-yielding, larger, or higher-cost devices.

{{As of|2022}}, a [[Semiconductor fabrication plant|fabrication facility]] (commonly known as a ''semiconductor fab'') can cost over US$12 billion to construct.<ref>{{cite web |title=TSMC to build 5nm fab in arizona, set to come online in 2024 |date=15 May 2020 |author1=Chafkin |publisher=Anandtech |url=https://www.anandtech.com/show/15803/tsmc-build-5nm-fab-in-arizona-for-2024}}</ref> The cost of a fabrication facility rises over time because of increased complexity of new products; this is known as [[Rock's law]]. Such a facility features:
* The [[Wafer (electronics)|wafers]] up to 300&nbsp;mm in diameter (wider than a common [[Plate (dishware)|dinner plate]]).
* {{As of|2022}}, 5&nbsp;nm transistors.
* [[Copper interconnect]]s where copper wiring replaces aluminum for interconnects.
* [[Low-κ dielectric]] [[Insulator (electricity)|insulators]].
* [[Silicon on insulator]] (SOI).
* [[Strained silicon]] in a process used by [[IBM]] known as [[Strained silicon directly on insulator]] (SSDOI).
* [[Multigate device]]s such as tri-gate transistors.

ICs can be manufactured either in-house by [[integrated device manufacturer]]s (IDMs) or using the [[foundry model]]. IDMs are vertically integrated companies (like [[Intel]] and [[Samsung]]) that design, manufacture and sell their own ICs, and may offer design and/or manufacturing (foundry) services to other companies (the latter often to [[fabless company|fabless companies]]). In the foundry model, fabless companies (like [[Nvidia]]) only design and sell ICs and outsource all manufacturing to [[pure play#pure play foundries|pure play foundries]] such as [[TSMC]]. These foundries may offer IC design services.