Editing Intel 4004 (section)

==Description==
[[File:KL National INS4004 (cropped).jpg|thumb|National Semiconductor was a [[second-source]] manufacturer of the 4004, under their part number INS4004.<ref>[http://www.cpu-world.com/CPUs/4004/index.html Intel 4004 microprocessor family], retrieved December 14, 2011.</ref>]]

The 4004 employs a [[10 μm process]] silicon-gate enhancement-load [[PMOS logic|pMOS]] technology on a {{nowrap|12 mm<sup>2</sup> die<ref>{{cite web |title=History of Computing Industrial Era 1970–1971 |date=October 19, 2010 |access-date=May 5, 2016 |url=http://www.thocp.net/timeline/1970.htm |quote=In February Intel releases the 4004 microprocessor to the market. It has 12 sq mm die size and 16 pins which fit into a motherboard. |archive-date=June 25, 2012 |archive-url=https://web.archive.org/web/20120625060215/http://www.thocp.net/timeline/1970.htm |url-status=dead }}</ref>}} and can execute approximately {{val|92,000}} [[instructions per second]]; a single instruction cycle is {{nowrap|10.8 [[microsecond]]s.<ref name=i4004data>{{cite web |title=Intel 4004 datasheet |url=http://www.intel.com/Assets/PDF/DataSheet/4004_datasheet.pdf |date=1987 |publication-date=July 6, 2010 |access-date=December 18, 2020 |archive-url=https://web.archive.org/web/20110601032753/http://www.intel.com/Assets/PDF/DataSheet/4004_datasheet.pdf |archive-date=June 1, 2011}}</ref>}} The original [[clock rate]] design goal was 1&nbsp;MHz, the same as the [[IBM 1620 Model&nbsp;I]].{{Citation needed|date=July 2011}}

The Intel 4004 was fabricated using masks produced by physically cutting each pattern at 500x magnification on a large sheet of [[Rubylith]] photo-reducing it, and repeating, a process made obsolete by current computer graphic design capabilities.<ref>{{cite web |title=Intel's Accidental Revolution |publisher=CNet.com |url=http://news.cnet.com/Intels+accidental+revolution/2009-1001_3-275806.html |access-date=July 30, 2009 |archive-url=https://archive.today/20120711020441/http://news.cnet.com/Intels-accidental-revolution/2009-1001_3-275806.html |archive-date=July 11, 2012 |url-status=dead }}</ref>

For the purpose of testing the produced chips, Faggin developed a tester for silicon [[Wafer (electronics)|wafers]] of MCS-4 family that was itself driven by 4004 chip. The tester also served as a proof for the management that Intel 4004 microprocessor could be used not only in calculator-like products, but also for control applications.<ref>{{cite web
 |url          = http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf
 |title        = Oral History of Federico Faggin
 |last         = Hendrie
 |first        = Gardner
 |date         = 2006
 |publisher    = Computer History Museum
 |access-date  = January 24, 2017
 |archive-url  = https://web.archive.org/web/20170110232713/http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf
 |archive-date = January 10, 2017 
 |url-status   = dead
}}</ref>

The 4004 includes functions for direct low-level control of memory-chip selection and I/O, which are not normally handled by the microprocessor; however, its functionality is limited in that it cannot execute code from RAM and is limited to whatever instructions are provided in ROM (or an independently loaded RAM working as ROM—in either case, the processor is itself unable to write or transfer data into an executable memory space). The RAM and ROM parts chips also unusual in their integration of I/O functions together with their primary memory function. This partitioning significantly reduced the minimum part count in an MCS-4 system, but required inclusion of a certain amount of processor-like logic on the memory chips themselves to accept, decode and execute relatively high-level data-transfer instructions.

The standard arrangement for a 4004 system is anything up to 16 × 4001 ROM chips (in a single bank) and 16 × 4002 RAM chips (in four banks of four), which together provide the 4&nbsp;KB program storage, 1024 + 256 nibbles of data/status storage, plus 64 output and 64 input/output external data/control lines (which can themselves be used to operate, e.g. a 4003). Intel's MCS-4 documentation, however, claims that up to 48 ROM and RAM chips (providing up to 192 external control lines) "in any combination" can be connected to the 4004 "with simple gating hardware", but declines to give any further detail or examples of how this would actually be achieved.