Editing Itanium (section)

=== Itanium 9300 (Tukwila): 2010 ===
{{Infobox CPU
 | name=9300 series
 | produced-start=8 February 2010
 | produced-end=2nd quarter of 2014
 | slowest=1.33
 | fastest=1.73
 | slow-unit=
 | fast-unit=GHz
 | fsb-slowest=
 | fsb-fastest=
 | fsb-slow-unit=
 | fsb-fast-unit=
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[65 nm]]
 | size-to=
 | soldby=
 | designfirm=
 | manuf1=
 | sock1=FC-LGA6 ([[LGA1248]])
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=
 | numcores=2 or 4
 | l1cache=
 | l2cache=256&nbsp;KB&nbsp;(D) + 512&nbsp;KB&nbsp;(I)
 | l3cache=10–24&nbsp;MB
 | application=
}}
{{Infobox CPU
 | name=9500 and 9700 series
 | produced-start=8 November 2012
 | produced-end=30 January 2020<ref>{{cite web |last1=Shilov |first1=Anton |title=Intel to Discontinue Itanium 9700 'Kittson' Processor, the Last of the Itaniums |url=https://www.anandtech.com/show/13924/intel-to-discontinue-itanium-9700-kittson-processor-the-last-itaniums |website=[[AnandTech]] |access-date=28 April 2022}}</ref>
 | slowest=1.73
 | fastest=2.67
 | slow-unit=
 | fast-unit=GHz
 | fsb-slowest=
 | fsb-fastest=
 | fsb-slow-unit=
 | fsb-fast-unit=
 | hypertransport-slowest=
 | hypertransport-fastest=
 | hypertransport-slow-unit=
 | hypertransport-fast-unit=
 | size-from=[[32 nm]]
 | size-to=
 | soldby=
 | designfirm=
 | manuf1=
 | sock1=FC-LGA6 ([[LGA1248]])
 | pack1=
 | brand1=
 | arch=
 | microarch=
 | cpuid=
 | code=Poulson, Kittson
 | numcores=4 or 8
 | l1cache=
 | l2cache=256&nbsp;KB&nbsp;(D) + 512&nbsp;KB&nbsp;(I)
 | l3cache=20–32&nbsp;MB
 | application=
}}
[[File:Intel Itanium 9300 CPU Top with cap.png|thumb|Intel Itanium 9300 CPU]]
[[File:Intel Itanium 9300 CPU bottom.png|thumb|Intel Itanium 9300 CPU LGA]]
[[File:Intel Itanium 9300 Socket Intel LGA 1248.JPG|thumb|Intel Itanium 9300 Socket Intel LGA 1248]]
[[File:Intel Itanium 9300 with cap removed.jpg|thumb|Intel Itanium 9300 with cap removed]]
{{Main|Tukwila (processor)|}}
The original code name for the first Itanium with more than two cores was Tanglewood, but it was changed to Tukwila in late 2003 due to trademark issues.<ref>{{cite web |last1=Kanellos |first1=Michael |title=Intel changes code name of future Itanium |url=https://www.cnet.com/tech/tech-industry/intel-changes-code-name-of-future-itanium/ |website=[[CNET]] |access-date=4 July 2023}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Trademark flap prompts Intel to rename Tanglewood |url=https://www.infoworld.com/article/2678103/trademark-flap-prompts-intel-to-rename-tanglewood.html |website=[[InfoWorld]] |date=18 December 2003 |access-date=31 March 2022}}</ref> Intel discussed a "middle-of-the-decade Itanium" to succeed Montecito, achieving ten times the performance of Madison.<ref>{{cite news |last1=Vance |first1=Ashlee |author-link=Ashlee Vance |title=Tanglewood to run 10x faster than Madison |url=https://www.theregister.com/2003/05/01/tanglewood_to_run_10x_faster1/ |work=[[The Register]] |access-date=27 April 2022}}</ref><ref name="qa"/> It was being designed by the famed [[DEC Alpha]] team and was expected have eight new multithreading-focused cores. Intel claimed "a lot more than two" cores and more than seven times the performance of Madison.<ref>{{cite web |last1=McMillan |first1=Robert |title=FALL IDF: Intel readies 8-core, 16-core Itanium 2 |url=https://www.infoworld.com/article/2676169/fall-idf--intel-readies-8-core--16-core-itanium-2.html |website=[[InfoWorld]] |date=17 September 2003 |access-date=31 March 2022}}</ref><ref>{{cite web |last1=Shankland |first1=Stephen |title='Tanglewood' to top Intel chip show |url=https://www.cnet.com/tech/tech-industry/tanglewood-to-top-intel-chip-show/ |website=[[CNET]] |access-date=31 March 2022}}</ref><ref>{{cite web |last1=McMillan |first1=Robert |title=Itanium 2 Montecito to be multithreaded |url=https://www.computerweekly.com/news/2240053525/Itanium-2-Montecito-to-be-multithreaded |website=[[Computer Weekly]] |access-date=31 March 2022}}</ref> In early 2004 Intel told of "plans to achieve up to double the performance over the Intel Xeon processor family at platform cost parity by 2007".<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel}}</ref> By early 2005 Tukwila was redefined, now having fewer cores but focusing on single-threaded performance and multiprocessor scalability.<ref>{{cite web |last1=Shankland |first1=Stephen |title=Intel to spotlight new Itanium: 'Poulson' |url=https://www.cnet.com/tech/tech-industry/intel-to-spotlight-new-itanium-poulson/ |website=[[CNET]] |access-date=31 March 2022}}</ref>

In March 2005, Intel disclosed some details of Tukwila, the next Itanium processor after Montvale, to be released in 2007. Tukwila would have [[multi-core processor|four processor cores]] and would replace the Itanium bus with a new [[Common System Interface]], which would also be used by a new Xeon processor.<ref name="CSI">{{cite magazine
 |url          = https://www.eetimes.com/intel-preps-hypertransport-competitor-for-xeon-itanium-cpus/
 |title        = Intel preps HyperTransport competitor for Xeon, Itanium CPUs
 |access-date  = December 17, 2019
 |last         = Merritt
 |first        = Rick
 |date         = March 2, 2005
 |magazine     = EE Times
 |archive-date = December 17, 2019
 |archive-url  = https://web.archive.org/web/20191217201715/https://www.eetimes.com/intel-preps-hypertransport-competitor-for-xeon-itanium-cpus/
 |url-status   = live
}}</ref> Tukwila was to have a "common platform architecture" with a Xeon codenamed ''Whitefield'',<ref name="idf04f"/> which was canceled in October 2005,<ref>{{cite news |last1=Vance |first1=Ashlee |author-link=Ashlee Vance |title=Intel's Xeon chip kill is result of chaos in India |url=https://www.theregister.com/2005/10/28/intel_whitefield_india/ |work=[[The Register]] |access-date=28 April 2022}}</ref> when Intel revised Tukwila's delivery date to late 2008.<ref name="zdnet_2005_slip">{{cite web
 | url=https://www.zdnet.com/article/intel-pushes-back-itanium-chips-revamps-xeon/
 | title=Intel pushes back Itanium chips, revamps Xeon
 | access-date=January 1, 2019
 | last=Shankland
 | first=Stephen
 | date=October 24, 2005
 | work=[[ZDNet]] News
 | archive-date=August 2, 2020
 | archive-url=https://web.archive.org/web/20200802000438/https://www.zdnet.com/article/intel-pushes-back-itanium-chips-revamps-xeon/
 | url-status=live
 }}</ref> In May 2009, the schedule for Tukwila, was revised again, with the release to OEMs planned for the first quarter of 2010.<ref name="INQ09">{{cite web
 | url=http://www.theinquirer.net/inquirer/news/1137434/tukwila-delayed-2010
 | title=Tukwila delayed until 2010
 | access-date=May 21, 2009
 | last=Demerjian
 | first=Charlie
 | date=May 21, 2009
 | website=[[The Inquirer]]
 | url-status=unfit
 | archive-url=https://web.archive.org/web/20090523101543/http://www.theinquirer.net/inquirer/news/1137434/tukwila-delayed-2010
 | archive-date=May 23, 2009
}}</ref>
The '''Itanium 9300''' series processor, codenamed ''Tukwila'', was released on February 8, 2010, with greater performance and memory capacity.<ref name="eweek-tukwila">{{cite web|url=https://www.eweek.com/networking/new-intel-itanium-offers-greater-performance-memory-capacity/|title=New Intel Itanium Offers Greater Performance, Memory Capacity|first=Jeff|last=Burt|date=February 8, 2010|website=[[eWeek]]}}</ref>

The device uses a 65&nbsp;nm process, includes two to four cores, up to 24&nbsp;[[Mebibyte|MB]] on-die caches, [[Hyper-Threading]] technology and integrated memory controllers. It implements [[ECC memory|double-device data correction]], which helps to fix memory errors. Tukwila also implements [[Intel QuickPath Interconnect]] (QPI) to replace the Itanium bus-based architecture. It has a peak interprocessor bandwidth of 96&nbsp;GB/s and a peak memory bandwidth of 34&nbsp;GB/s. With QuickPath, the processor has integrated memory controllers and interfaces the memory directly, using QPI interfaces to directly connect to other processors and I/O hubs. QuickPath is also used on Intel [[x86-64]] processors using the ''[[Nehalem (microarchitecture)|Nehalem]]'' microarchitecture, which possibly enabled Tukwila and Nehalem to use the same chipsets.<ref name="Kittson">{{cite web
 | url=https://www.zdnet.com/article/intel-updates-itanium-line-with-kittson/
 | title=Intel updates Itanium line with 'Kittson'
 | access-date=June 15, 2007
 | last=Tan
 | first=Aaron
 | date=June 15, 2007
 | work=[[ZDNet]]
 }}</ref>
Tukwila incorporates two memory controllers, each of which has two links to Scalable Memory Buffers, which in turn support multiple [[DDR3 SDRAM|DDR3]] [[DIMM]]s,<ref name=TukwilaDelay>{{cite web
 | url=https://arstechnica.com/business/news/2009/02/intel-delays-quad-itanium-to-boost-platform-memory-capacity.ars
 | title=Intel delays quad Itanium to boost platform memory capacity
 | access-date=February 5, 2009
 | last=Stokes
 | first=Jon
 | date=February 5, 2009
 | work=ars technica
 | archive-date=January 22, 2012
 | archive-url=https://web.archive.org/web/20120122093011/http://arstechnica.com/business/news/2009/02/intel-delays-quad-itanium-to-boost-platform-memory-capacity.ars
 | url-status=live
 }}</ref>
much like the Nehalem-based Xeon processor code-named ''[[Beckton (microprocessor)|Beckton]]''.<ref name="DailyTech Server">{{cite news
 |url          = http://www.dailytech.com/Intel+Aims+for+Efficiency+With+New+Server+Roadmap/article14224.htm
 |first        = Jansen
 |last         = Ng
 |title        = Intel Aims for Efficiency With New Server Roadmap
 |date         = February 10, 2009
 |work    = [[DailyTech]]
 |access-date   = February 10, 2009
 |archive-url  = https://web.archive.org/web/20090213150005/http://www.dailytech.com/intel+aims+for+efficiency+with+new+server+roadmap/article14224.htm
 |archive-date = February 13, 2009
 |url-status   = dead
 |df           = mdy-all
}}</ref>