Editing Memory address (section)

==Memory models==
{{for|the specification of memory access semantics in multi-threading programs|Memory model (programming)}}

Many programmers prefer to address memory such that there is no distinction between code space and data space (see [[#Address space in application programming|above]]), as well as from physical and virtual memory (see [[#Types|above]]) — in other words, numerically identical pointers refer to exactly the same byte of RAM.

However, many early computers did not support such a ''flat memory model'' — in particular, [[Harvard architecture]] machines force program storage to be completely separate from data storage.
Many modern [[Digital signal processor|DSP]]s (such as the [[Motorola 56000]]) have three separate storage areas — program storage, coefficient storage, and data storage. Some commonly used instructions fetch from all three areas simultaneously — fewer storage areas (even if there were the same total bytes of storage) would make those instructions run slower.

===Memory models in x86 architecture===
{{main|x86 memory models}}
Early x86 processors use the [[memory segmentation|segmented memory model]] addresses based on a combination of two numbers: a [[x86 memory segmentation|memory segment]], and an [[offset (computer science)|offset]] within that segment.

Some segments are implicitly treated as ''code segments'', dedicated for [[instruction (computer science)|instruction]]s, ''[[call stack|stack]] segments'', or normal ''[[data (computing)|data]] segments''. Although the usages are different, the segments do not have different [[memory protection]]s reflecting this.
In the [[flat memory model]] all segments (segment registers) are generally set to zero, and only offsets are variable.
{{see also|Long mode}}

===Memory models in IBM S/360 and successors multiprocessors===
In the [[360/65]] and [[360/67]], IBM introduced a concept known as prefixing.<ref>{{cite book
 | title       = IBM System/360 Principles of Operation 
 | id          = A22-6821-7
 | date        = September 1968
 | edition     = Eighth
 | section     = Multisystem Operation
 | section-url = http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf#page=20
 | page        = 18
 | quote       = The relocation procedure applies to the first 4,096 bytes of storage. This area contains all permanent storage assignments and, generally, has special significance to supervisory programs. The relocation is accomplished by inserting a 12-bit prefix in each address which has the high-order 12 bits set to zero and hence, pertains to location 0-4095.
 | url         = http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf
 | series      = Systems Reference Library
 | access-date = July 21, 2024
 }}
</ref> Prefixing is a level of address translation that applies to addresses in real mode and to addresses generated by dynamic address translation, using a unique prefix assigned to each CPU in a multiprocessor system. On the 360/65, 360/67 and every successor prior to [[z/Architecture]], it logically swaps a 4096 byte block of storage with another block assigned to the CPU. On z/Architecture,<ref>{{cite book
 | title       = z/Architecture Principles of Operation 
 | id          = SA22-7832-13
 | date        = May 2022
 | edition     = Fourteenth
 | section     = Prefixing in the z/Architecture Architectural Mode
 | section-url = https://www.vm.ibm.com/library/other/22783213.pdf#page=128
 | page        = 3-21–3-23
 | quote       = Prefixing provides the ability to assign the block of real addresses containing assigned storage locations to a different block in absolute storage for each CPU, thus permitting more than one CPU sharing main storage to operate concurrently with a minimum of interference, especially in the processing of interruptions.
 | url         = https://www.vm.ibm.com/library/other/22783213.pdf
 | access-date = July 21, 2024
 }}
</ref> prefixing operates on 8196-byte blocks. IBM classifies addresses on these systems as:<ref>{{cite book
 | title       = z/Architecture Principles of Operation 
 | id          = SA22-7832-13
 | date        = May 2022
 | edition     = Fourteenth
 | section     = Address Types
 | section-url = https://www.vm.ibm.com/library/other/22783213.pdf#page=110
 | pages       = 3-4–3-5
 | url         = https://www.vm.ibm.com/library/other/22783213.pdf
 | access-date = July 21, 2024
 }}
</ref>

* Virtual addresses: addresses subject to dynamic address translation
* Real addresses: addresses generated from dynamic address translation, and addresses used by code running in real mode
* Absolute addresses: physical addresses

On the 360/65, on S/370 models without DAT and when running with translation turned off, there are only a flat real address space and a flat absolute address space.

On the 360/67, S/370 and successors through [[S/390]], when running with translation on, addresses contain a segment number, a page number and an offset. Although early models supported both 2 KiB and 4 KiB page sizes, later models only supported 4 KiB. IBM later added instructions to move data between a primary address space and a secondary address space.

[[S/370-XA]] added 31-bit addresses, but retained the segment/page/offset hierarchy with 4 KiB pages.

[[ESA/370]] added 16 access registers (ARs) and an AR access control mode, in which a 31-bit address was translated using the address space designated by a selected AR.

[[z/Architecture]] supports 64-bit virtual, real and absolute addresses, with multi-level page tables.