Editing Multiplexer (section)

== Unconventional use of multiplexers for arithmetic ==
Multiplexers have found application in unconventional [[stochastic computing]] (SC), particularly in facilitating arithmetic addition. In this paradigm, data is represented as a probability bitstream where the number of '1' bits signifies the magnitude of a value. Thus, the function of a 2-to-1 multiplexer can be conceptualized as a probability function denoted as:

<math>y = P(a) \times P(1-s)+P(b)\times P(s)</math>

, where a and b are the input bitstream and s is the select input. Using the select input = 0.5 yields:

<math>y=\frac{P(a)+P(b)}{2}</math>

While this approach doesn't yield exact addition but rather scaled addition, it is deemed acceptable in most SC studies. Multiplexers are extensively utilized for tasks such as average addition, average pooling, and median filtering within SC circuits. Moreover, more sophisticated applications of multiplexers include serving as Bernstein polynomial function generator,<ref>{{Cite journal |last1=Najafi |first1=M. Hassan |last2=Li |first2=Peng |last3=Lilja |first3=David J. |last4=Qian |first4=Weikang |last5=Bazargan |first5=Kia |last6=Riedel |first6=Marc |date=2017-06-29 |title=A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing |url=https://dl.acm.org/doi/10.1145/3060537 |journal=ACM Journal on Emerging Technologies in Computing Systems |volume=13 |issue=4 |pages=57:1–57:28 |doi=10.1145/3060537 |issn=1550-4832}}</ref> capable of producing arbitrary mathematical functions within the SC domain. Recent research has also revealed that combinations of multiplexers can facilitate large-scale [[multiply-accumulate]] operation,<ref>{{Cite journal |last1=Lee |first1=Yang Yang |last2=Halim |first2=Zaini Abdul |last3=Wahab |first3=Mohd Nadhir Ab |last4=Almohamad |first4=Tarik Adnan |date=2024-03-04 |title=Stochastic Computing Convolutional Neural Network Architecture Reinvented for Highly Efficient Artificial Intelligence Workload on Field-Programmable Gate Array |journal=Research |language=en |volume=7 |page=0307 |doi=10.34133/research.0307 |issn=2639-5274 |pmc=10911856 |pmid=38439995|bibcode=2024Resea...7..307L }}</ref> demonstrating feasibility in accelerating [[convolutional neural network]] on [[field-programmable gate array]]s.