Editing Page table (section)

=== {{Anchor|MULTILEVEL}}Multilevel page tables ===
[[File:X86 Paging 4K.svg|thumb|right|upright=2|Two-level page table structure in [[x86]] architecture (without [[Physical Address Extension|PAE]] or [[Page Size Extension|PSE]]).]]
[[File:X86 Paging PAE 4K.svg|thumb|right|upright=2|Three-level page table structure in x86 architecture (with [[Physical Address Extension|PAE]], without [[Page Size Extension|PSE]]).]]

The inverted page table keeps a listing of mappings installed for all frames in physical memory. However, this could be quite wasteful. Instead of doing so, we could create a page table structure that contains mappings for virtual pages. It is done by keeping several page tables that cover a certain block of virtual memory. For example, we can create smaller 1024-entry 4&nbsp;KB pages that cover 4&nbsp;MB of virtual memory.

This is useful since often the top-most parts and bottom-most parts of virtual memory are used in running a process - the top is often used for text and data segments while the bottom for stack, with free memory in between. The multilevel page table may keep a few of the smaller page tables to cover just the top and bottom parts of memory and create new ones only when strictly necessary.

Now, each of these smaller page tables are linked together by a master page table, effectively creating a [[Tree (data structure)|tree]] data structure. There need not be only two levels, but possibly multiple ones. For example, a virtual address in this schema could be split into three parts: the index in the root page table, the index in the sub-page table, and the offset in that page.

Multilevel page tables are also referred to as "hierarchical page tables".