Editing Phase-locked loop (section)

===Deskewing===
If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a [[delay-locked loop]] (DLL) is frequently used.<ref>{{cite web |url         = http://www-vlsi.stanford.edu/papers/mh_micro_98.pdf |author1     = M Horowitz |author2     = C. Yang |author3     = S. Sidiropoulos |title       = High-speed electrical signaling: overview and limitations |publisher   = IEEE Micro |date        = 1998-01-01 |url-status     = dead |archive-url  = https://web.archive.org/web/20060221015031/http://www-vlsi.stanford.edu/papers/mh_micro_98.pdf |archive-date = 2006-02-21}}</ref>