Editing Physical Address Extension (section)

=== x86-64 paging ===
On [[x86-64]] processors in native [[long mode]], the address translation scheme uses PAE but adds a fourth table, the 512-entry ''page-map level&nbsp;4'' table, and extends the page directory pointer table to 512&nbsp;entries instead of the original 4&nbsp;entries it has in protected mode. This means that 48&nbsp;bits of virtual page number are translated, giving a virtual address space of up to 256&nbsp;TB.  For some processors, a mode can be enabled with a fifth table, the 512-entry [[Intel 5-level paging|page-map level&nbsp;5 table]]; this means that 57&nbsp;bits of virtual page number are translated, giving a virtual address space of up to 128&nbsp;PB.<ref name="amd-24593"/>{{rp|pages=141–153}}
In the page table entries, in the original specification, 40&nbsp;bits of physical page number are implemented.