Editing SPARC (section)

====Branching====
Conditional branches test condition codes in a [[status register]], as seen in many instruction sets such the [[IBM System/360 architecture]] and successors and the [[x86]] architecture. This means that a test and branch is normally performed with two instructions; the first is an ALU instruction that sets the condition codes, followed by a branch instruction that examines one of those flags. The SPARC does not have specialized test instructions; tests are performed using normal ALU instructions with the destination set to %G0. For instance, to test if a register holds the value 10 and then branch to code that handles it, one would:

 subcc %L1,10,%G0 !subtract 10 from %L1, setting the zero flag if %L1 is 10
 be WASEQUAL      !if the zero flag is set, branch to the address marked WASEQUAL

In a conditional branch instruction, the '''icc''' or '''fcc''' field specifies the condition being tested. The 22-bit displacement field is the address, relative to the current PC, of the target, in words, so that conditional branches can go forward or backward up to 8 megabytes. The ''ANNUL'' (A) bit is used to get rid of some delay slots. If it is 0 in a conditional branch, the delay slot is executed as usual. If it is 1, the delay slot is only executed if the branch is taken. If it is not taken, the instruction following the conditional branch is skipped.

There are a wide variety of conditional branches: {{code|BA}} (branch always, essentially a jmp), {{code|BN}} (branch never), {{code|BE}} (equals), {{code|BNE}} (not equals), {{code|BL}} (less than), {{code|BLE}} (less or equal), {{code|BLEU}} (less or equal, unsigned), {{code|BG}} (greater), {{code|BGE}} (greater or equal), {{code|BGU}} (greater unsigned), {{code|BPOS}} (positive), {{code|BNEG}} (negative), {{code|BCC}} (carry clear), {{code|BCS}} (carry set), {{code|BVC}} (overflow clear), {{code|BVS}} (overflow set).<ref name="sparc-v8-whitepaper" />{{rp|119{{hyp}}120}}

The FPU and CP have sets of condition codes separate from the integer condition codes and from each other; two additional sets of branch instructions were defined to test those condition codes. Adding an F to the front of the branch instruction in the list above performs the test against the FPU's condition codes,<ref name="sparc-v8-whitepaper" />{{rp|121{{hyp}}122}} while, in SPARC V8, adding a C tests the flags in the otherwise undefined CP.<ref name="sparc-v8-whitepaper" />{{rp|123{{hyp}}124}}

The {{code|CALL}} (jump to subroutine) instruction uses a 30-bit [[program counter]]-relative ''word'' offset. As the target address is specifying the start of a word, not a byte, 30-bits is all that is needed to reach any address in the 4 gigabyte address space.<ref name=ncsu/> The CALL instruction deposits the return address in register R15, also known as output register O7.

The {{code|JMPL}} (jump and link) instruction is a three-operand instruction, with two operands representing values for the target address and one operand for a register in which to deposit the return address. The address is created by adding the two address operands to produce a 32-bit address. The second address operand may be a constant or a register.