Editing Soft error (section)

=== Detecting soft errors===
There has been  work addressing soft errors in processor and memory resources using both hardware and software techniques. Several research efforts addressed soft errors by proposing error detection and recovery via hardware-based redundant multi-threading.<ref name="ReinhardtMukherjee2000">{{cite journal |last1=Reinhardt |first1=Steven K. |last2=Mukherjee |first2=Shubhendu S. |title=Transient fault detection via simultaneous multithreading |journal=ACM SIGARCH Computer Architecture News |volume=28 |issue=2 |date=2000 |pages=25–36 |issn=0163-5964 |doi=10.1145/342001.339652|citeseerx=10.1.1.112.37}}</ref><ref name="MukherjeeKontz2002">{{cite journal |last1=Mukherjee |first1=Shubhendu S. |last2=Kontz |first2=Michael |last3=Reinhardt |first3=Steven K. |title=Detailed design and evaluation of redundant multithreading alternatives |journal=ACM SIGARCH Computer Architecture News |volume=30 |issue=2 |date=2002 |pages=99 |issn=0163-5964 |doi=10.1145/545214.545227 |citeseerx=10.1.1.13.2922|s2cid=1909214 }}</ref><ref name="VijaykumarPomeranz2002">{{cite journal |last1=Vijaykumar |first1=T. N. |last2=Pomeranz |first2=Irith|author2-link= Irith Pomeranz |last3=Cheng |first3=Karl |title=Transient-fault recovery using simultaneous multithreading |journal=ACM SIGARCH Computer Architecture News |volume=30 |issue=2 |date=2002 |pages=87 |issn=0163-5964 |doi=10.1145/545214.545226|s2cid=2270600 }}</ref>
These approaches used special hardware to replicate an application execution to identify errors in the output, which increased hardware design complexity and cost including high performance overhead. Software-based soft error tolerant schemes, on the other hand, are flexible and can be applied on commercial off-the-shelf microprocessors. Many works propose compiler-level instruction replication and result checking for soft error detection.
<ref name="oh2002error">{{cite journal |last1=Nahmsuk |first1=Oh |last2=Shirvani |first2=Philip P. |last3=McCluskey |first3=Edward J. |title= Error detection by duplicated instructions in super-scalar processors |journal=IEEE Transactions on Reliability |volume=51 |date=2002 |pages=63–75 |doi=10.1109/24.994913}}</ref><ref name="reis2005swift">{{cite book |last1=Reis A. |first1=George A. |title=International Symposium on Code Generation and Optimization |last2=Chang |first2=Jonathan |last3=Vachharajani |first3=Neil |last4=Rangan |first4=Ram |last5=August |first5=David I. |chapter=SWIFT: Software implemented fault tolerance |location=Proceedings of the international symposium on Code generation and optimization |date=2005 |pages=243–254 |doi=10.1109/CGO.2005.34 |isbn=978-0-7695-2298-2 |citeseerx=10.1.1.472.4177|s2cid=5746979 }}</ref> 
<ref name="Didehban2016nZDC">{{citation |last1=Didehban |first1=Moslem |last2=Shrivastava |first2=Aviral |title=Proceedings of the 53rd Annual Design Automation Conference |chapter=NZDC: A compiler technique for near zero silent data corruption |date=2016 |publisher=ACM |location=Proceedings of the 53rd Annual Design Automation Conference (DAC) |page=48 |doi=10.1145/2897937.2898054 |isbn=9781450342360|s2cid=5618907 }}</ref>