Editing 90 nm process

{{short description|Semiconductor device fabrication technology node}}
{{use dmy dates|date=March 2022}}
{{About|semiconductor manufacturing|the spaceport with FAA LID code of 90NM|Spaceport America}}
{{refimprove|date=September 2015}}
{{Semiconductor manufacturing processes}}
The '''90 nm process''' refers to the technology used in [[semiconductor manufacturing]] to create [[integrated circuit]]s with a minimum feature size of 90 nanometers. It was an advancement over the previous [[130 nm process]]. Eventually, it was succeeded by smaller process nodes, such as the [[65 nm]], [[45 nm]], and [[32 nm process]]es.

It was commercialized by the 2003–2005 timeframe, by semiconductor companies including [[Toshiba]], [[Sony]], [[Samsung]], [[IBM]], [[Intel]], [[Fujitsu]], [[TSMC]], [[Elpida Memory|Elpida]], [[AMD]], [[Infineon]], [[Texas Instruments]] and [[Micron Technology]].

The origin of the 90&nbsp;nm value is historical; it reflects a trend of 70% scaling every 2–3 years. The naming is formally determined by the [[International Technology Roadmap for Semiconductors]] (ITRS).

The 300&nbsp;mm wafer size became mainstream at the 90&nbsp;nm node. The previous wafer size was 200&nbsp;mm diameter.

The 193&nbsp;[[nanometre|nm]] wavelength was introduced by many (but not all) companies for [[photolithography|lithography]] of critical layers mainly during the 90&nbsp;nm node. Yield issues associated with this transition (due to the use of new [[photoresist]]s) were reflected in the high costs associated with this transition.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;<ref name="urlNo More Nanometers – EEJournal">{{cite web |url=https://www.eejournal.com/article/no-more-nanometers/ |title=No More Nanometers – EEJournal |date=23 July 2020 |format= }}</ref> neither gate length, metal pitch or gate pitch on a "90nm" device is ninety nanometers.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09}}</ref><ref>{{cite web|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...|last=Hruska|first=Joel|website=[[ExtremeTech]]|date=23 June 2014 }}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10}}</ref><ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12}}</ref> 

==History==
A 90{{nbsp}}nm [[silicon]] [[MOSFET]] was [[semiconductor device fabrication|fabricated]] by Iranian engineer [[Ghavam Shahidi]] (later [[IBM]] director) with D.A. Antoniadis and H.I. Smith at [[MIT]] in 1988. The device was fabricated using [[X-ray lithography]].<ref>{{cite journal |last1=Shahidi |first1=Ghavam G. |last2=Antoniadis |first2=D. A. |last3=Smith |first3=H. I. |title=Reduction of hot-electron-generated substrate current in sub-100-nm channel length Si MOSFET's |journal=IEEE Transactions on Electron Devices |date=December 1988 |volume=35 |issue=12 |pages=2430– |doi=10.1109/16.8835|bibcode=1988ITED...35.2430S }}</ref>

Toshiba, Sony and Samsung developed a 90{{nbsp}}nm process during 2001{{ndash}}2002, before being introduced in 2002 for Toshiba's [[eDRAM]] and Samsung's 2{{nbsp}}[[Gibibit|Gb]] [[NAND flash]] memory.<ref>{{cite news |title=Toshiba and Sony Make Major Advances in Semiconductor Process Technologies |url=https://www.toshiba.co.jp/about/press/2002_12/pr0301.htm |access-date=26 June 2019 |work=[[Toshiba]] |date=3 December 2002}}</ref><ref name="samsung2000s">{{cite web |title=Our Proud Heritage from 2000 to 2009 |url=https://www.samsung.com/semiconductor/about-us/history-03/ |website=[[Samsung Semiconductor]] |publisher=[[Samsung]] |access-date=25 June 2019}}</ref> IBM demonstrated a 90{{nbsp}}nm [[silicon-on-insulator]] (SOI) [[CMOS]] process, with development led by Shahidi, in 2002. The same year, Intel demonstrated a 90{{nbsp}}nm [[strained-silicon]] process.<ref>{{cite news |title=IBM, Intel wrangle at 90 nm |url=https://www.eetimes.com/document.asp?doc_id=1145379 |access-date=17 September 2019 |work=[[EE Times]] |date=13 December 2002}}</ref> Fujitsu commercially introduced its 90{{nbsp}}nm process in 2003<ref name="fujitsu">{{Cite web |url=http://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf |title=65nm CMOS Process Technology |access-date=20 June 2019 |archive-date=16 May 2020 |archive-url=https://web.archive.org/web/20200516015827/https://www.fujitsu.com/downloads/MICRO/fma/pr/PressKit/65nmProcessTechnology.pdf |url-status=dead }}</ref> followed by TSMC in 2004.<ref>{{cite web |title=90nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/90nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>

[[Gurtej Sandhu|Gurtej Singh Sandhu]] of Micron Technology initiated the development of [[atomic layer deposition]] high-k [[Thin film|films]] for [[Dynamic random-access memory|DRAM]] memory devices. This helped drive cost-effective implementation of [[semiconductor memory]], starting with 90{{nbsp}}nm [[Semiconductor node|node]] DRAM.<ref name="ieee">{{cite web |title=IEEE Andrew S. Grove Award Recipients |url=https://www.ieee.org/about/awards/bios/grove-recipients.html |archive-url=https://web.archive.org/web/20180909112404/https://www.ieee.org/about/awards/bios/grove-recipients.html |url-status=dead |archive-date=9 September 2018 |website=[[IEEE Andrew S. Grove Award]] |publisher=[[Institute of Electrical and Electronics Engineers]] |access-date=4 July 2019}}</ref> 

Intel's 90nm process has a transistor density of 1.45 million transistors per square millimeter (MTr/mm2).<ref>{{cite web | url=https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review/3 | title=Intel's 10nm Cannon Lake and Core i3-8121U Deep Dive Review }}</ref>

==Example: Elpida 90&nbsp;nm DDR2 SDRAM process==
[[Elpida Memory]]'s 90&nbsp;nm [[DDR2 SDRAM]] process.<ref>Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report</ref>

* Use of 300&nbsp;mm wafer size
* Use of KrF (248&nbsp;nm) lithography with [[optical proximity correction]]
* 512&nbsp;Mbit
* 1.8&nbsp;V operation
* Derivative of earlier 110&nbsp;nm and 100&nbsp;nm processes

==Processors using 90&nbsp;nm process technology==
* Sony/Toshiba [[Emotion Engine|EE]]+[[PlayStation 2 technical specifications|GS]] ([[PlayStation 2]]) - 2003<ref>{{cite news |title=EMOTION ENGINE® AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION® BECOME ONE CHIP |url=https://www.sie.com/content/dam/corporate/en/corporate/release/pdf/030421be.pdf |access-date=26 June 2019 |publisher=[[Sony]] |date=April 21, 2003}}</ref>
* Sony/Toshiba/IBM [[Cell (microprocessor)|Cell Processor]] - 2005
* IBM [[PowerPC G5#PowerPC 970FX|PowerPC G5 970FX]] - 2004
* IBM [[PowerPC G5#PowerPC 970MP|PowerPC G5 970MP]] - 2005
* IBM [[PowerPC G5#PowerPC 970GX|PowerPC G5 970GX]] - 2005
* IBM [[Xenon (processor)|"Waternoose"]] Xbox 360 Processor - 2005
* Intel [[Pentium 4]] Prescott - 2004-02
* Intel [[Celeron]] D Prescott-256 - 2004-05
* Intel [[Pentium M]] [[Dothan (microprocessor)|Dothan]] - 2004-05
* Intel [[Celeron]] M [[Dothan (microprocessor)|Dothan]]-1024 - 2004-08
* Intel [[Xeon]] Nocona, Irwindale, Cranford, Potomac, Paxville - 2004-06
* Intel [[Pentium D]] Smithfield - 2005-05
* AMD [[Athlon 64]] Winchester, Venice, San Diego, Orleans - 2004-10
* AMD [[Athlon 64 X2]] Manchester, Toledo, Windsor - 2005-05
* AMD [[Sempron]] Palermo and Manila - 2004-08
* AMD [[Turion 64]] Lancaster and Richmond - 2005-03
* [[NVIDIA]] [[GeForce]] 8800 GTS (G80) - 2006
* AMD [[Turion 64 X2]] Taylor and Trinidad - 2006-05
* AMD [[Opteron]] Venus, Troy, and Athens - 2005-08
* AMD Dual-core [[Opteron]] Denmark, Italy, Egypt, Santa Ana, and Santa Rosa
* [[VIA C7]] - 2005-05
* Loongson (Godson) [[Loongson#Loongson microprocessor specifications|2Е]] STLS2E02 - 2007-04
* Loongson (Godson) [[Loongson#Loongson microprocessor specifications|2F]] STLS2F02 - 2008-07
* [[MCST-4R]] - 2010-12
* [[Elbrus-2S+]] - 2011-11

==See also==
{{Portal|Companies}}

==References==
{{reflist}}

==External links==
*[https://web.archive.org/web/20060529035720/http://www.pcworld.com/reviews/article/0,aid,104975,src,ov,00.asp PC World Review]
*[https://web.archive.org/web/20080531133521/http://www.itworld.com/Comp/1982/030924nano/ Review] [[ITworld]]
*[https://archive.today/20130102094011/http://investor.com.com/AMD+enters+the+90-nanometer+zone/2100-1006_3-5313410.html AMD]
*[http://www.keepmedia.com/pubs/ECN/2002/08/01/239576?extID=10032&oliID=213 Fujitsu]{{Dead link|date=September 2018 |bot=InternetArchiveBot |fix-attempted=yes }}
*[http://www.intel.com/technology/silicon/nanotechnology.htm Intel]
*[http://www.intel.com/pressroom/archive/releases/20020813tech.htm August, 2002 release by Intel]

{{sequence|
prev=[[130 nm process|130 nm]]|
next=[[65 nm process|65 nm]]|
list=[[MOSFET]] [[semiconductor device fabrication|manufacturing processes]]
}}

{{DEFAULTSORT:90 Nanometre}}
[[Category:2004 introductions]]
[[Category:International Technology Roadmap for Semiconductors lithography nodes|*00090]]
[[Category:American inventions]]