Editing ARM architecture family

{{Short description|Family of computer architectures}}
{{Redirect|ARM architecture|the Australian architectural firm|ARM Architecture (company)}}
{{Use British English|date=June 2012}}<!--Possibly we want to make exceptions for technical non-British spelled words ARM uses like "virtualization"-->
{{Use dmy dates|date=July 2020}}
{{Infobox CPU architecture <!-- Common info belongs in this infobox -->
|name         = ARM
|image        = Arm logo 2025.svg
|designer     = {{plainlist|
* [[Sophie Wilson]]
* [[Steve Furber]]
* [[Acorn Computers]]/[[Arm Holdings]]}}
|bits         = [[32-bit computing|32-bit]], [[64-bit computing|64-bit]]
|introduced   = {{Start date and age|1985|df=yes}}
|design       = [[Reduced instruction set computer|RISC]]
|type         = [[Load–store architecture|Load–store]]
|branching    = [[Status register|Condition code]], compare and branch
|open         = Proprietary
}}
{{Infobox CPU architecture<!-- 64-bit architecture info belongs in this infobox -->
|image        = AArch64 logo.svg
|name         = ARM ''AArch64'' (64/32-bit)
|introduced   = {{start date and age|2011|df=yes}}
|version      = ARMv8-R, ARMv8-A, ARMv8.1-A, ARMv8.2-A, ARMv8.3-A, ARMv8.4-A, ARMv8.5-A, ARMv8.6-A, ARMv8.7-A, ARMv8.8-A, ARMv8.9-A, ARMv9.0-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A, ARMv9.4-A, ARMv9.5-A, ARMv9.6-A <!--note ARMv8-M does not really fit here or anywhere as only 32-bit.-->
|encoding     = [[AArch64]]/A64 and [[#AArch32|AArch32]]/A32 use 32-bit instructions, AArch32/T32 (Thumb-2) uses mixed 16- and 32-bit instructions<ref name="v8arch"/>
|endianness   = [[Endianness#Bi-endianness|Bi]] (little as default)
|extensions   = <!--Complementary: --> [[ARMv8-A SVE|SVE]], SVE2, SME, AES, SM3, SM4, SHA, CRC32, RNDR, TME; All mandatory: [[#Thumb-2|Thumb-2]], [[#Advanced SIMD (Neon)|Neon]], VFPv4-D16, VFPv4; obsolete: [[#Thumb|Thumb]] and [[Jazelle]]
|gpr          = 31 × 64-bit integer registers<ref name="v8arch"/>
|fpr          = 32 × [[128-bit computing|128-bit]] registers<ref name="v8arch"/> for scalar 32- and 64-bit [[IEEE 754|FP]] or [[single instruction, multiple data|SIMD]] FP or integer; or cryptography
}}
{{Infobox CPU architecture <!-- 32-bit Cortex architecture info belongs in this infobox -->
|name         = ARM ''AArch32'' (32-bit)
|introduced   = <!-- please investigate the years each of these architectures were announced -->
|version      = ARMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M
|encoding     = 32-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.
|endianness   = [[Bi-endian|Bi]] (little as default)
|extensions   = [[#Thumb|Thumb]], [[#Thumb-2|Thumb-2]], [[#Advanced SIMD (Neon)|Neon]], [[Jazelle]], AES, SM3, SM4, SHA, CRC32, RNDR, DSP, Saturated, FPv4-SP, FPv5, Helium; obsolete since ARMv8: [[#Thumb|Thumb]] and [[Jazelle]]
|gpr          = 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC)
|fpr          = Up to 32 × 64-bit registers,<ref>{{cite web |url=https://github.com/ARM-software/abi-aa/blob/2a70c42d62e9c3eb5887fa50b71257f20daca6f9/aapcs32/aapcs32.rst#6121vfp-register-usage-conventions |title=6.1.2.1 VFP register usage conventions |work=Procedure Call Standard for the ARM Architecture |publisher=[[Arm Holdings]] |date=6 October 2023 |access-date=22 August 2024}}</ref> SIMD/floating-point (optional)
}}
{{Infobox CPU architecture <!-- 32-bit legacy architecture info belongs in this infobox -->
|name         = ARM 32-bit (legacy)
|introduced   = <!-- please investigate the years each of these architectures were announced -->
|version      = ARMv6, ARMv5, ARMv4T, ARMv3, ARMv2
|encoding     = 32-bit, except Thumb extension uses mixed 16- and 32-bit instructions.
|endianness   = [[Bi-endian|Bi]] (little as default) in ARMv3 and above
|extensions   = [[ARM Thumb|Thumb]], [[Jazelle]] <!-- please investigate and clarify -->
|gpr          = 15 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)
|fpr          = None
}}

'''ARM''' (stylised in lowercase as '''arm''', formerly an acronym for '''Advanced RISC Machines''' and originally '''Acorn RISC Machine''') is a family of [[reduced instruction set computer|RISC]] [[instruction set architecture]]s (ISAs) for [[central processing unit|computer processors]]. [[Arm Holdings]] develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses [[semiconductor intellectual property core|cores]] that implement these ISAs.

Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, including [[smartphone]]s, [[laptop]]s, and [[tablet computer]]s, as well as [[embedded system]]s.<ref name="ARM1">{{cite newsgroup |url=https://groups.google.com/group/comp.arch/msg/269fe7defd51f29e |title=Some facts about the Acorn RISC Machine |author-link=Sophie Wilson |first=Roger |last=Wilson |newsgroup=comp.arch |date=2 November 1988 |access-date=25 May 2007}}</ref><ref name="extremetech-3g-territory">{{cite news |url=https://www.extremetech.com/extreme/52180-arm-cores-climb-into-3g-territory |title=ARM Cores Climb into 3G Territory |date=14 October 2002 |first=Mark |last=Hachman |work=ExtremeTech |access-date=24 May 2018}}</ref><ref>{{cite news |url=https://www.embedded.com/the-two-percent-solution/ |title=The Two Percent Solution |last=Turley |first=Jim |work=Embedded |date=18 December 2002 |access-date=14 February 2023}}</ref> However, ARM processors are also used for [[desktop computer|desktops]] and [[server (computing)|server]]s, including [[Fugaku (supercomputer)|Fugaku]], the world's fastest [[supercomputer]] from 2020<ref>{{cite news |last1=Cutress |first1=Ian |title=New #1 Supercomputer: Fujitsu's Fugaku and A64FX take Arm to the Top with 415 PetaFLOPs |url=https://www.anandtech.com/show/15869/new-1-supercomputer-fujitsus-fugaku-and-a64fx-take-arm-to-the-top-with-415-petaflops |access-date=2021-01-25 |work=anandtech.com |date=22 June 2020}}</ref> to 2022. With over 230 billion ARM chips <!--thereof at least 130 billion ARM processors--> produced,<ref>{{cite press release |title=Arm Partners Have Shipped 200 Billion Chips |url=https://www.arm.com/blogs/blueprint/200bn-arm-chips |access-date=2021-11-03 |website=Arm |language=en}}</ref><ref>{{cite web |url=https://community.arm.com/iot/b/internet-of-things/posts/enabling-mass-iot-connectivity-as-arm-partners-ship-100-billion-chips |title=Enabling Mass IoT connectivity as ARM partners ship 100 billion chips |website=community.arm.com |date=27 February 2017 |quote=the cumulative deployment of 100 billion chips, half of which shipped in the last four years. [..] why not a trillion or more? That is our target, seeing a trillion connected devices deployed over the next two decades. |access-date=8 April 2020}}</ref> {{as of|2024|alt=since at least 2003, and with its dominance increasing every year}},<!-- source for older 2014 claim:<ref>{{cite news |last=Robinson |first=Tracy |date=12 February 2014 |url=https://community.arm.com/community/news/blog/2014/02/12/celebrating-50-billion-shipped-arm-powered-chips |title=Celebrating 50 Billion shipped ARM-powered Chips |access-date=31 January 2016}}</ref> --> ARM is the most widely used family of instruction set architectures.<ref>{{cite web |url=https://www.icinsights.com/news/bulletins/MCU-Market-On-Migration-Path-To-32bit-And-ARMbased-Devices/ |title=MCU Market on Migration Path to 32-bit and ARM-based Devices: 32-bit tops in sales; 16-bit leads in unit shipments |publisher=IC Insights |date=25 April 2013 |access-date=1 July 2014}}</ref><ref name="extremetech-3g-territory"/><ref>{{cite web |last=Turley |first=Jim |year=2002 |title=The Two Percent Solution |url=https://www.embedded.com/electronics-blogs/significant-bits/4024488/The-Two-Percent-Solution |archive-url=https://web.archive.org/web/20230215003436/https://www.embedded.com/the-two-percent-solution/ |archive-date=15 February 2023 |publisher=embedded.com}}</ref><ref>{{cite web |url=https://www.theregister.co.uk/2011/02/01/arm_holdings_q4_2010_numbers/ |title=Arm Holdings eager for PC and server expansion |website=[[The Register]] |date=1 February 2011|author-first1=Timothy|author-last1=Prickett Morgan}}</ref><ref>{{cite news |last=McGuire-Balanza |first=Kerry |date=11 May 2010 |url=https://community.arm.com/groups/internet-of-things/blog/2010/05/11/arm-from-zero-to-billions-in-25-short-years |title=ARM from zero to billions in 25 short years |publisher=[[Arm Holdings]] |access-date=8 November 2012|url-access=registration}}</ref>

There have been several generations of the ARM design. The original ARM1 used a [[32-bit computing|32-bit]] internal structure but had a 26-bit [[address space]] that limited it to 64&nbsp;MB of [[main memory]]. This limitation was removed in the ARMv3 series, which has a 32-bit address space, and several additional generations up to ARMv7 remained 32-bit. Released in 2011, the ARMv8-A architecture added support for a [[64-bit computing|64-bit]] address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set.<ref name="armv8-a-announcement">{{cite press release |url=https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php |title=ARM Discloses Technical Details of the Next Version of the ARM Architecture |date=27 October 2011 |publisher=[[Arm Holdings]] |access-date=20 September 2013 |archive-url=https://web.archive.org/web/20190101024118/https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php |archive-date=1 January 2019}}</ref> Arm Holdings has also released a series of additional instruction sets for different roles: the "Thumb" extensions add both 32- and 16-bit instructions for improved [[code density]], while [[Jazelle]] added instructions for directly handling [[Java bytecode]]. More recent changes include the addition of [[simultaneous multithreading]] (SMT) for improved performance or [[fault tolerance]].<ref>{{cite web |url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-neoverse-n1-platform-accelerating-the-transformation-to-a-scalable-cloud-to-edge-infrastructure |title=Announcing the ARM Neoverse N1 Platform |website=community.arm.com |date=20 February 2019 |access-date=8 April 2020}}</ref>

==History==

===BBC Micro===
{{Main|BBC Micro}}
[[Acorn Computers]]' first widely successful design was the [[BBC Micro]], introduced in December 1981. This was a relatively conventional machine based on the [[MOS Technology 6502]] CPU but ran at roughly double the performance of competing designs like the [[Apple II]] due to its use of faster [[dynamic random-access memory]] (DRAM). Typical DRAM of the era ran at about 2&nbsp;MHz; Acorn arranged a deal with [[Hitachi]] for a supply of faster 4&nbsp;MHz parts.<ref>{{cite web |last=Fairbairn |first=Douglas |date=31 January 2012 |title=Oral History of Sophie Wilson |url=http://archive.computerhistory.org/resources/access/text/2012/06/102746190-05-01-acc.pdf |access-date=2 February 2016 |url-status=live |archive-url=https://web.archive.org/web/20160303221351/http://archive.computerhistory.org/resources/access/text/2012/06/102746190-05-01-acc.pdf |archive-date=3 March 2016 |df=dmy-all}}</ref>

Machines of the era generally shared memory between the processor and the [[framebuffer]], which allowed the processor to quickly update the contents of the screen without having to perform separate [[input/output]] (I/O). As the timing of the video display is exacting, the video hardware had to have priority access to that memory. Due to a quirk of the 6502's design, the CPU left the memory untouched for half of the time. Thus by running the CPU at 1&nbsp;MHz, the video system could read data during those down times, taking up the total 2&nbsp;MHz bandwidth of the RAM. In the BBC Micro, the use of 4&nbsp;MHz RAM allowed the same technique to be used, but running at twice the speed. This allowed it to outperform any similar machine on the market.<ref name="reghardware">{{cite news |last=Smith |first=Tony |date=30 November 2011 |title=The BBC Micro turns 30 |website=The Register Hardware |url=http://www.reghardware.com/2011/11/30/bbc_micro_model_b_30th_anniversary/ |access-date=12 December 2011 |url-status=live |archive-url=https://web.archive.org/web/20111212044749/http://www.reghardware.com/2011/11/30/bbc_micro_model_b_30th_anniversary/ |archive-date=12 December 2011 |df=dmy-all}}</ref>

===Acorn Business Computer===
{{Main|Acorn Business Computer}}
1981 was also the year that the [[IBM Personal Computer]] was introduced. Using the recently introduced [[Intel 8088]], a [[16-bit computing|16-bit]] CPU compared to the 6502's [[8-bit computing|8-bit]] design, it offered higher overall performance. Its introduction changed the desktop computer market radically: what had been largely a hobby and gaming market emerging over the prior five years began to change to a must-have business tool where the earlier 8-bit designs simply could not compete. Even newer [[32-bit computing|32-bit]] designs were also coming to market, such as the [[Motorola 68000]]<ref>{{cite web |last=Polsson |first=Ken |title=Chronology of Microprocessors |url=https://processortimeline.info/ |url-status=live |archive-url=https://web.archive.org/web/20180809022013/http://processortimeline.info/ |archive-date=2018-08-09 |access-date=2013-09-27 |website=Processortimeline.info}}</ref> and [[National Semiconductor NS32016]].<ref name="leedy198304">{{cite news |last=Leedy |first=Glenn |date=April 1983 |url=https://archive.org/details/byte-magazine-1983-04/page/n53/mode/2up |title=The National Semiconductor NS16000 Microprocessor Family |work=Byte |access-date=22 August 2020 |pages=53–66}}</ref>

Acorn began considering how to compete in this market and produced a new paper design named the [[Acorn Business Computer]]. They set themselves the goal of producing a machine with ten times the performance of the BBC Micro, but at the same price.{{sfn|Evans|2019|loc=6:00}} This would outperform and underprice the PC. At the same time, the recent introduction of the [[Apple Lisa]] brought the [[graphical user interface]] (GUI) concept to a wider audience and suggested the future belonged to machines with a GUI.<ref>{{cite news |url=https://www.electronicsweekly.com/Articles/29/04/1998/7242/ARM39s-way.htm |title=ARM's way |work=[[Electronics Weekly]] |date=29 April 1998 |access-date=26 October 2012 |author=Manners, David |url-status=dead |archive-url=https://web.archive.org/web/20120729024818/http://www.electronicsweekly.com/Articles/29/04/1998/7242/ARM39s-way.htm |archive-date=29 July 2012}}</ref> The Lisa, however, cost $9,995, as it was packed with support chips, large amounts of memory, and a [[hard disk drive]], all very expensive then.{{sfn|Evans|2019|loc=5:30}}

The engineers then began studying all of the CPU designs available. Their conclusion about the existing 16-bit designs was that they were a lot more expensive and were still "a bit crap",{{sfn|Evans|2019|loc=7:45}} offering only slightly higher performance than their BBC Micro design. They also almost always demanded a large number of support chips to operate even at that level, which drove up the cost of the computer as a whole. These systems would simply not hit the design goal.{{sfn|Evans|2019|loc=7:45}} They also considered the new 32-bit designs, but these cost even more and had the same issues with support chips.{{sfn|Evans|2019|loc=8:30}} According to [[Sophie Wilson]], all the processors tested at that time performed about the same, with about a 4&nbsp;Mbit/s bandwidth.<ref>{{cite AV media |url=https://www.youtube.com/watch?v=D4nWLIeBuf4 |archive-url=https://ghostarchive.org/varchive/youtube/20211211/D4nWLIeBuf4 |archive-date=2021-12-11 |url-status=live |title=Sophie Wilson at Alt Party 2009 (Part 3/8)}}{{cbignore}}</ref>{{efn|Using 32-bit words, 4&nbsp;Mbit/s corresponds to 1 [[Instructions per second#Millions of instructions per second (MIPS)|MIPS]].}}

Two key events led Acorn down the path to ARM. One was the publication of a series of reports from the [[University of California, Berkeley]], which suggested that a simple chip design could nevertheless have extremely high performance, much higher than the latest 32-bit designs on the market.<ref name="informit">{{cite book |last=Chisnall |first=David |date=23 August 2010 |url=https://www.informit.com/articles/article.aspx?p=1620207 |title=Understanding ARM Architectures |access-date=26 May 2013}}</ref> The second was a visit by [[Steve Furber]] and Sophie Wilson to the [[Western Design Center]], a company run by [[Bill Mensch]] and his sister, which had become the logical successor to the MOS team and was offering new versions like the [[WDC 65C02]]. The Acorn team saw high school students producing chip layouts on Apple II machines, which suggested that anyone could do it.{{sfn|Evans|2019|loc=9:00}}<ref>{{cite book |last=Furber |first=Stephen B. |year=2000 |title=ARM system-on-chip architecture |publisher=Addison-Wesley |location=Boston |isbn=0-201-67519-6 |title-link=ARM system-on-chip architecture}}</ref> In contrast, a visit to another design firm working on modern 32-bit CPU revealed a team with over a dozen members who were already on revision H of their design and yet it still contained bugs.{{efn|Available references do not mention which design team this was, but given the timing and known history of designs of the era, it is likely this was the National Semiconductor team whose NS32016 suffered from a large number of bugs.}} This cemented their late 1983 decision to begin their own CPU design, the Acorn RISC Machine.{{sfn|Evans|2019|loc=9:50}}

===Design concepts===
The original [[Berkeley RISC]] designs were in some sense teaching systems, not designed specifically for outright performance. To the RISC's basic register-heavy and load/store concepts, ARM added a number of the well-received design notes of the 6502. Primary among them was the ability to quickly serve [[interrupt]]s, which allowed the machines to offer reasonable [[input/output]] performance with no added external hardware. To offer interrupts with similar performance as the 6502, the ARM design limited its physical [[address space]] to 64&nbsp;MB of total addressable space, requiring 26 bits of address. As instructions were 4 bytes (32 bits) long, and required to be aligned on 4-byte boundaries, the lower 2 bits of an instruction address were always zero. This meant the [[program counter]] (PC) only needed to be 24 bits, allowing it to be stored along with the eight bit [[processor flag]]s in a single 32-bit register. That meant that upon receiving an interrupt, the entire machine state could be saved in a single operation, whereas had the PC been a full 32-bit value, it would require separate operations to store the PC and the status flags. This decision halved the interrupt overhead.{{sfn|Evans|2019|loc=23:30}}

Another change, and among the most important in terms of practical real-world performance, was the modification of the [[instruction set]] to take advantage of [[page mode DRAM]]. Recently introduced, page mode allowed subsequent accesses of memory to run twice as fast if they were roughly in the same location, or "page", in the DRAM chip. Berkeley's design did not consider page mode and treated all memory equally. The ARM design added special vector-like memory access instructions, the "S-cycles", that could be used to fill or save multiple registers in a single page using page mode. This doubled memory performance when they could be used, and was especially important for graphics performance.{{sfn|Evans|2019|loc=26:00}}

The Berkeley RISC designs used [[register window]]s to reduce the number of register saves and restores performed in [[procedure call]]s; the ARM design did not adopt this.

Wilson developed the instruction set, writing a simulation of the processor in [[BBC&nbsp;BASIC]] that ran on a BBC Micro with a [[BBC Micro expansion unit#6502 Second Processor|second 6502 processor]].<ref>{{cite web |title=ARM Instruction Set design history with Sophie Wilson (Part 3) |url=https://www.youtube.com/watch?v=QqxThgLTLyk&t=960 |url-status=live |archive-url=https://ghostarchive.org/varchive/youtube/20211211/QqxThgLTLyk |archive-date=2021-12-11 |via=YouTube |date=10 May 2015 |access-date=25 May 2020}}{{cbignore}}</ref><ref>{{cite web |title=Oral History of Sophie Wilson – 2012 Computer History Museum Fellow |url=http://archive.computerhistory.org/resources/access/text/2012/06/102746190-05-01-acc.pdf |work=Computer History Museum |date=31 January 2012 |access-date=25 May 2020}}</ref> This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO, [[Hermann Hauser]], and requested more resources. Hauser gave his approval and assembled a small team to design the actual processor based on Wilson's ISA.<ref>{{cite journal |last=Harker |first=T. |date=Summer 2009 |title=ARM gets serious about IP (Second in a two-part series [Associated Editors' View] |url=https://ieeexplore.ieee.org/document/5191430 |journal=IEEE Solid-State Circuits Magazine |volume=1 |issue=3 |pages=8–69 |doi=10.1109/MSSC.2009.933674 |s2cid=36567166 |issn=1943-0590|url-access=subscription }}</ref> The official Acorn RISC Machine project started in October 1983.

===ARM1===
[[File:Acorn-ARM-Evaluation-System.jpg|thumb|right|upright=1.4|ARM1 2nd processor for the BBC&nbsp;Micro]]
Acorn chose [[VLSI Technology]] as the "silicon partner", as they were a source of ROMs and custom chips for Acorn. Acorn provided the design and VLSI provided the layout and production. The first samples of ARM silicon worked properly when first received and tested on 26 April 1985.<ref name="ARM1"/> Known as ARM1, these versions ran at 6&nbsp;MHz.{{sfn|Evans|2019|loc=20:30}}

The first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips (VIDC, IOC, MEMC), and sped up the [[CAD software]] used in ARM2 development. Wilson subsequently rewrote [[BBC BASIC]] in ARM [[assembly language]]. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, making ARM BBC BASIC an extremely good test for any ARM emulator.

===ARM2===
The result of the simulations on the ARM1 boards led to the late 1986 introduction of the ARM2 design running at 8&nbsp;MHz, and the early 1987 speed-bumped version at 10 to 12&nbsp;MHz.{{efn|Matt Evans notes that it appears the faster versions were simply binned higher, and appear to have no underlying changes.{{sfn|Evans|2019|loc=22:00}}}} A significant change in the underlying architecture was the addition of a [[Booth's multiplication algorithm|Booth multiplier]], whereas formerly multiplication had to be carried out in software.{{sfn|Evans|2019|loc=21:30}} Further, a new Fast Interrupt reQuest mode, FIQ for short, allowed registers 8 through 14 to be replaced as part of the interrupt itself. This meant FIQ requests did not have to save out their registers, further speeding interrupts.{{sfn|Evans|2019|loc=22:0030}}

The first use of the ARM2 were in ARM Evaluations systems, supplied as a second processor for BBC Micro and Master machines, from July 1986,<ref>{{Cite web |title=Chris's Acorns: Acorn OEM Products |url=http://chrisacorns.computinghistory.org.uk/docs/Acorn/OEM/OEM.html |access-date=2025-04-24 |website=chrisacorns.computinghistory.org.uk}}</ref> internal Acorn A500 development machines,<ref>{{Cite web |title=Chris's Acorns: Acorn A500 (prototype) |url=http://chrisacorns.computinghistory.org.uk/Computers/A500.html |access-date=2025-04-24 |website=chrisacorns.computinghistory.org.uk}}</ref> and the [[Acorn Archimedes]] personal computer models A305, A310, and A440, launched on the 6th June 1987.

According to the [[Dhrystone]] benchmark, the ARM2 was roughly seven times the performance of a typical 7&nbsp;MHz 68000-based system like the [[Amiga]] or [[Macintosh SE]]. It was twice as fast as an [[i386|Intel 80386]] running at 16&nbsp;MHz, and about the same speed as a multi-processor [[VAX-11#VAX-11/784|VAX-11/784]] [[superminicomputer]]. The only systems that beat it were the [[Sun SPARC]] and [[R2000 microprocessor|MIPS R2000]] RISC-based [[workstation]]s.{{sfn|Evans|2019|loc=14:00}} Further, as the CPU was designed for high-speed I/O, it dispensed with many of the support chips seen in these machines; notably, it lacked any dedicated [[direct memory access]] (DMA) controller which was often found on workstations. The graphics system was also simplified based on the same set of underlying assumptions about memory and timing. The result was a dramatically simplified design, offering performance on par with expensive workstations but at a price point similar to contemporary desktops.{{sfn|Evans|2019|loc=14:00}}

The ARM2 featured a [[32-bit computing|32-bit]] [[Bus (computing)|data bus]], [[26-bit computing|26-bit]] address space and 27&nbsp;32-bit [[processor register|registers]], of which 16 are accessible at any one time (including the [[program counter|PC]]).<ref>{{cite web |url=https://www.cs.umd.edu/~meesh/cmsc411/website/proj01/arm/armchip.html |title=From one Arm to the next! ARM Processors and Architectures |access-date=31 May 2022}}</ref> The ARM2 had a [[transistor count]] of just 30,000,<ref name="Markus Levy, Convergence Promotions">{{cite web |url=https://reds.heig-vd.ch/share/cours/ReCo/documents/TheHistoryOfTheARMArchitecture.pdf |title=The History of The ARM Architecture: From Inception to IPO |access-date=18 July 2022 |last=Levy |first=Markus}}</ref> compared to Motorola's six-year-older 68000 model with around 68,000. Much of this simplicity came from the lack of [[microcode]], which represents about one-quarter to one-third of the 68000's transistors, and the lack of (like most CPUs of the day) a [[CPU cache|cache]]. This simplicity enabled the ARM2 to have a low power consumption and simpler thermal packaging by having fewer powered transistors. Nevertheless, ARM2 offered better performance than the contemporary 1987 [[IBM PS/2 Model 50]], which initially utilised an [[Intel 80286]], offering 1.8 MIPS @ 10&nbsp;MHz, and later in 1987, the 2 MIPS of the PS/2 70, with its [[i386|Intel 386]] DX @ 16&nbsp;MHz.<ref>{{Cite book |url=http://oldcomputers.net/Amiga_3000_manual.pdf |title=Introducing the Commodore Amiga 3000 |date=1991 |publisher=Commodore-Amiga, Inc.}}</ref><ref>{{Cite web |title=Computer MIPS and MFLOPS Speed Claims 1980 to 1996 |url=http://www.roylongbottom.org.uk/mips.htm#anchorAcorn |access-date=2023-06-17 |website=www.roylongbottom.org.uk}}</ref>

A successor, ARM3, was produced with a 4 KB cache, which further improved performance.<ref name="Chattopadhyay2010">{{cite book |author=Santanu Chattopadhyay |title=Embedded System Design |url=https://books.google.com/books?id=4Bir9Kw059gC&pg=PA9 |year=2010 |publisher=PHI Learning Pvt. Ltd. |isbn=978-81-203-4024-4 |page=9}}</ref> The address bus was extended to 32&nbsp;bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.<ref>{{cite web |url=https://www.heyrick.co.uk/assembler/32bit.html |title=32&nbsp;bit operation |author=Richard Murray}}</ref>

===Advanced RISC Machines Ltd. – ARM6===
[[File:ARMSoCBlockDiagram.svg|right|upright=2.1|thumbnail|Microprocessor-based system on a chip]]

[[File:GPS ARM610 die.JPG|thumb|right|upright=1.4|[[Die (integrated circuit)|Die]] of an ARM610 microprocessor]]
In the late 1980s, [[Apple Inc.|Apple Computer]] and [[VLSI Technology]] started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Advanced RISC Machines Ltd.,<ref>{{cite web |url=https://www.arm.com/about/company-profile/milestones.php |title=ARM Company Milestones |website=ARM |access-date=8 April 2015 |archive-url=https://web.archive.org/web/20150420050600/https://www.arm.com/about/company-profile/milestones.php |archive-date=20 April 2015 |url-status=dead}}</ref><ref name="andrews-co-verification-of-hardware-and-software-for-ARM-SoC-design">{{cite book |last1=Andrews |first1=Jason |title=Co-verification of hardware and software for ARM SoC design |url=https://archive.org/details/coverificationha00andr_198 |url-access=limited |chapter=3 SoC Verification Topics for the ARM Architecture |publisher=[[Elsevier]] |year=2005 |location=Oxford, UK |pages=[https://archive.org/details/coverificationha00andr_198/page/n93 69] |isbn=0-7506-7730-9 |quote=ARM started as a branch of Acorn Computer in Cambridge, England, with the formation of a joint venture between Acorn, Apple and VLSI Technology. A team of twelve employees produced the design of the first ARM microprocessor between 1983 and 1985.}}</ref><ref name="latimes apple to join acorn">{{cite news |url=https://www.latimes.com/archives/la-xpm-1990-11-28-fi-4993-story.html |title=Apple to Join Acorn, VLSI in Chip-Making Venture |work=Los Angeles Times |date=28 November 1990 |access-date=6 February 2012 |author=Weber, Jonathan |location=Los Angeles |quote=Apple has invested about $3 million (roughly 1.5 million pounds) for a 30% interest in the company, dubbed Advanced Risc Machines Ltd. (ARM) [...]}}</ref> which became ARM Ltd. when its parent company, [[Arm Holdings]] plc, floated on the [[London Stock Exchange]] and [[Nasdaq]] in 1998.<ref>{{cite web |url=https://www.arm.com/miscPDFs/3822.pdf |title=ARM Corporate Backgrounder |website=ARM |archive-url=https://web.archive.org/web/20061004150423/https://www.arm.com/miscPDFs/3822.pdf |archive-date=4 October 2006 |url-status=dead}}</ref> The new Apple–ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM610 as the basis for their [[Apple Newton]] PDA.

===Early licensees===
In 1994, Acorn used the ARM610 as the main [[central processing unit]] (CPU) in their [[RiscPC]] computers. [[Digital Equipment Corporation|DEC]] licensed the ARMv4 architecture and produced the [[StrongARM]].<ref>{{cite journal |last1=Montanaro |first1=James |first2=Richard T. |last2=Witek |first3=Krishna |last3=Anne |first4=Andrew J. |last4=Black |first5=Elizabeth M. |last5=Cooper |first6=Daniel W. |last6=Dobberpuhl |author-link6=Daniel W. Dobberpuhl |first7=Paul M. |last7=Donahue |first8=Jim |last8=Eno |first9=Gregory W. |last9=Hoeppner |first10=David |last10=Kruckemyer |first11=Thomas H. |last11=Lee |first12=Peter C. M. |last12=Lin |first13=Liam |last13=Madden |first14=Daniel |last14=Murray |first15=Mark H. |last15=Pearce |first16=Sribalan |last16=Santhanam |first17=Kathryn J. |last17=Snyder |first18=Ray |last18=Stephany |first19=Stephen C. |last19=Thierauf |display-authors=1 |date=1997 |url=https://www.hpl.hp.com/hpjournal/dtj/vol9num1/vol9num1art5.pdf |title=A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor |journal=Digital Technical Journal |volume=9 |issue=1 |pages=49–62}}</ref> At 233&nbsp;[[Hertz|MHz]], this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as part of a lawsuit settlement, and Intel took the opportunity to supplement their [[Intel i960|i960]] line with the StrongARM. Intel later developed its own high performance implementation named [[XScale]], which it has since sold to [[Marvell Technology Group|Marvell]]. Transistor count of the ARM core remained essentially the same throughout these changes; ARM2 had 30,000&nbsp;transistors,<ref name=deMone>{{cite web |last1=DeMone |first1=Paul |title=ARM's Race to Embedded World Domination |url=https://www.realworldtech.com/arms-race/ |website=Real World Technologies |access-date=6 October 2015 |date=9 November 2000}}</ref> while ARM6 grew only to 35,000.<ref>{{cite web |url=https://www.technologyreview.com/article/418585/march-of-the-machines/ |title=March of the Machines |website=technologyreview.com |publisher=[[MIT Technology Review]] |access-date=6 October 2015 |date=20 April 2010 |archive-date=16 October 2015 |archive-url=https://web.archive.org/web/20151016102603/http://www.technologyreview.com/article/418585/march-of-the-machines/ |url-status=dead }}</ref>

===Market share===
In 2005, about 98% of all mobile phones sold used at least one ARM processor.<ref name=Krazit>{{cite news |url=https://www.cnet.com/tech/tech-industry/armed-for-the-living-room/ |title=ARMed for the living room |first=Tom |last=Krazit |date=3 April 2006 |publisher=CNET}}</ref> In 2010, producers of chips based on ARM architectures reported shipments of 6.1&nbsp;billion [[list of products using ARM processors|ARM-based processors]], representing 95% of [[smartphone]]s, 35% of [[integrated digital television|digital television]]s and [[set-top box]]es, and 10% of [[mobile computer]]s. In 2011, the 32-bit ARM architecture was the most widely used architecture in mobile devices and the most popular 32-bit one in embedded systems.<ref name="popular"/> In 2013, 10 billion were produced<ref>{{cite web |url=https://community.arm.com/community/news/blog/2014/02/12/celebrating-50-billion-shipped-arm-powered-chips |title=Celebrating 50 Billion shipped ARM-powered Chips |author1=Tracy Robinson |date=12 February 2014}}</ref> and "ARM-based chips are found in nearly 60 percent of the world's mobile devices".<ref>{{cite web |url=https://www.broadcom.com/blog/chip-design/arms-reach-50-billion-chip-milestone-video/ |title=ARM's Reach: 50 Billion Chip Milestone |author1=Sarah Murry |date=3 March 2014 |archive-url=https://web.archive.org/web/20150916101815/https://www.broadcom.com/blog/chip-design/arms-reach-50-billion-chip-milestone-video/ |archive-date=16 September 2015 |url-status=dead}}</ref>

==Licensing==
{{See also|Arm Holdings#Licensees}}
[[File:STM32F103VGT6-HD.jpg|thumb|upright=1.4|[[Die (integrated circuit)|Die]] of a [[STM32]]&shy;F103VGT6 [[ARM Cortex-M3]] microcontroller with 1&nbsp;[[megabyte|MB]] [[flash memory]] by [[STMicroelectronics]] ]]

===Core licence===
Arm Holdings's primary business is selling [[IP core]]s, which licensees use to create [[microcontroller]]s (MCUs), [[CPU]]s, and [[system on a chip|systems-on-chips]] based on those cores. The [[original design manufacturer]] combines the ARM core with other parts to produce a complete device, typically one that can be built in existing [[semiconductor fabrication plant]]s (fabs) at low cost and still deliver substantial performance. The most successful implementation has been the [[ARM7#ARM7TDMI|ARM7TDMI]] with hundreds of millions sold. [[Atmel]] has been a precursor design center in the ARM7TDMI-based embedded system.

The ARM architectures used in smartphones, PDAs and other [[mobile device]]s range from ARMv5 to {{nowrap|ARMv8-A}}.

In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based on [[Intel Atom]].<ref>{{cite news |url=http://www.linuxfordevices.com/c/a/News/Always-Innovating-Touch-Book/ |title=ARM netbook ships with detachable tablet |first=Eric |last=Brown |year=2009 |access-date=19 August 2009 |archive-url=https://archive.today/20130103181613/http://www.linuxfordevices.com/c/a/News/Always-Innovating-Touch-Book/ |archive-date=3 January 2013 |url-status=dead}}</ref>

Arm Holdings offers a variety of licensing terms, varying in cost and deliverables. Arm Holdings provides to all licensees an integratable hardware description of the ARM core as well as complete software development toolset ([[compiler]], [[debugger]], [[software development kit]]), and the right to sell manufactured [[semiconductor device|silicon]] containing the ARM CPU.

SoC packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's [[OMAP]] products, Samsung's Hummingbird and [[Exynos]] products, Apple's [[Apple A4|A4]], [[Apple A5|A5]], and [[Apple A5X|A5X]],<!-- but not later Apple SoCs, which have Apple-designed cores --> and [[NXP Semiconductors|NXP]]'s [[i.MX]].

[[Fabless manufacturing|Fabless]] licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified [[semiconductor intellectual property core]]. For these customers, Arm Holdings delivers a [[netlist|gate netlist]] description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in [[logic synthesis|synthesizable]] [[register-transfer level|RTL]] ([[Verilog]]) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist ([[clock rate|high clock speed]], very low power consumption, instruction set extensions, etc.). While Arm Holdings does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured products such as chip devices, evaluation boards and complete systems. [[Foundry model|Merchant foundries]] can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to re-manufacture ARM cores for other customers.

Arm Holdings prices its IP based on perceived value. Lower performing ARM cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesisable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry that holds an ARM licence, such as Samsung or Fujitsu, can offer fab customers reduced licensing costs. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee.

Compared to dedicated semiconductor foundries (such as [[TSMC]] and [[United Microelectronics Corporation|UMC]]) without in-house design services, Fujitsu/Samsung charge two- to three-times more per manufactured [[wafer (electronics)|wafer]].{{citation needed|date=May 2013}} For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE ([[non-recurring engineering]]) costs, making the dedicated foundry a better choice.

Companies that have developed chips with cores designed by Arm include [[Amazon.com]]'s [[Annapurna Labs]] subsidiary,<ref>{{cite news |url=https://www.eetimes.com/document.asp?doc_id=1328624& |title=Amazon Now Sells Own ARM chips |author=Peter Clarke |date=7 January 2016}}</ref> [[Analog Devices]], [[Apple Inc.|Apple]], [[AppliedMicro]] (now: [[MACOM Technology Solutions]]<ref>{{cite press release |url=https://www.macom.com/about/news-and-events/press-release-archive/row-col1/news--event-archive/macom-successfully-completes-a-1 |title=MACOM Successfully Completes Acquisition of AppliedMicro |date=26 January 2017}}</ref>), [[Atmel]], [[Broadcom]], [[Cavium]], [[Cypress Semiconductor]], [[Freescale Semiconductor]] (now [[NXP Semiconductors]]), [[Huawei]], [[Intel]],{{Dubious|ARM-based chips and Intel|reason=StrongARM and XScale did not use cores designed by Arm, and no other ARM-based Intel chips are known|date=December 2019}} [[Maxim Integrated]], [[Nvidia]], [[NXP]], [[Qualcomm]], [[Renesas Electronics|Renesas]], [[Samsung Electronics]], [[ST Microelectronics]], [[Texas Instruments]], and [[Xilinx]].

===Built on ARM Cortex Technology licence===
In February 2016, ARM announced the Built on ARM Cortex Technology licence, often shortened to Built on Cortex (BoC) licence. This licence allows companies to partner with ARM and make modifications to ARM Cortex designs. These design modifications will not be shared with other companies. These semi-custom core designs also have brand freedom, for example [[Kryo#Kryo 280|Kryo 280]].

Companies that are current licensees of Built on ARM Cortex Technology include [[Qualcomm]].<ref>{{cite web |url=https://www.anandtech.com/show/10366/arm-built-on-cortex-license |title=ARM Details Built on ARM Cortex Technology License |last=Frumusanu |first=Andrei |website=[[AnandTech]] |access-date=26 May 2019}}</ref>

===Architectural licence===
Companies can also obtain an ARM ''architectural licence'' for designing their own CPU cores using the ARM instruction sets. These cores must comply fully with the ARM architecture. Companies that have designed cores that implement an ARM architecture include Apple, AppliedMicro (now: [[Ampere Computing]]), Broadcom, [[Cavium]] (now: Marvell), [[Digital Equipment Corporation]], Intel, Nvidia, Qualcomm, Samsung Electronics, [[Fujitsu]], and NUVIA Inc. (acquired by Qualcomm in 2021).

===ARM Flexible Access===
On 16 July 2019, ARM announced ARM Flexible Access. ARM Flexible Access provides unlimited access to included ARM [[intellectual property]] (IP) for development. Per product licence fees are required once a customer reaches foundry tapeout or prototyping.<ref>{{cite web |url=https://www.anandtech.com/show/14644/arm-flexible-access-design-the-soc-before-spending-money |title=ARM Flexible Access: Design the SoC Before Spending Money |last=Cutress |first=Ian |website=[[AnandTech]] |access-date=9 October 2019}}</ref><ref>{{cite web |url=https://www.arm.com/products/flexible-access/faqs |title=ARM Flexible Access Frequently Asked Questions |website=ARM |access-date=9 October 2019}}</ref>

75% of ARM's most recent IP over the last two years are included in ARM Flexible Access. As of October 2019:
* CPUs: [[ARM Cortex-A5|Cortex-A5]], [[ARM Cortex-A7|Cortex-A7]], [[ARM Cortex-A32|Cortex-A32]], [[ARM Cortex-A34|Cortex-A34]], [[ARM Cortex-A35|Cortex-A35]], [[ARM Cortex-A53|Cortex-A53]], [[ARM Cortex-R5|Cortex-R5]], [[ARM Cortex-R8|Cortex-R8]], [[ARM Cortex-R52|Cortex-R52]], [[ARM Cortex-M0|Cortex-M0]], [[ARM Cortex-M0+|Cortex-M0+]], [[ARM Cortex-M3|Cortex-M3]], [[ARM Cortex-M4|Cortex-M4]], [[ARM Cortex-M#Cortex-M7|Cortex-M7]], [[ARM Cortex-M#Cortex-M23|Cortex-M23]], [[ARM Cortex-M#Cortex-M33|Cortex-M33]]
* GPUs: [[Mali (GPU)|Mali-G52]], [[Mali (GPU)|Mali-G31]]. Includes Mali Driver Development Kits (DDK).
* Interconnect: CoreLink NIC-400, CoreLink NIC-450, CoreLink CCI-400, CoreLink CCI-500, CoreLink CCI-550, ADB-400 AMBA, XHB-400 AXI-AHB
* System Controllers: CoreLink GIC-400, CoreLink GIC-500, PL192 VIC, BP141 TrustZone Memory Wrapper, CoreLink TZC-400, CoreLink L2C-310, CoreLink MMU-500, BP140 Memory Interface
* Security IP: CryptoCell-312, CryptoCell-712, TrustZone True Random Number Generator
* Peripheral Controllers: PL011 UART, PL022 SPI, PL031 RTC
* Debug & Trace: CoreSight SoC-400, CoreSight SDC-600, CoreSight STM-500, CoreSight System Trace Macrocell, CoreSight Trace Memory Controller
* Design Kits: Corstone-101, Corstone-201
* Physical IP: Artisan PIK for Cortex-M33 TSMC 22ULL including memory compilers, logic libraries, GPIOs and documentation
* Tools & Materials: Socrates IP ToolingARM Design Studio, Virtual System Models
* Support: Standard ARM Technical support, ARM online training, maintenance updates, credits toward onsite training and design reviews

==Cores==
{{Main|List of ARM processors}}
{| class="wikitable sortable"
|-
! rowspan=2 | Architecture
! rowspan=2 | Core<br>bit-width
! colspan=2 | Cores
! rowspan=2 | Profile
! rowspan=2 | Refe-<br>rences
|-
! Arm Ltd.
! Third-party
|-
| {{center|ARMv1}} || {{center|[[32-bit|32]]}} || [[ARM1]] || || {{center|Classic}} || {{center|<ref name="26bitaddr" group="a">Although most [[datapath]]s and [[CPU register]]s in the early ARM processors were 32-bit, [[26-bit#Early ARM processors|addressable memory was limited to 26 bits]]; with upper bits, then, used for status flags in the program counter register.</ref>}}
|-
| {{center|ARMv2}} || {{center|32}} || [[ARM2]], ARM250, [[ARM3]] || [[Amber (processor core)|Amber]], STORM Open Soft Core<ref>{{cite web |url=https://opencores.org/websvn,filedetails?repname=storm_core&path=%2Fstorm_core%2Ftrunk%2Fdoc%2FSTORM+CORE+datasheet.pdf |title=STORM CORE Processor System |first=Stephan |last=Nolting |publisher=[[OpenCores]] |access-date=1 April 2014}}</ref> || {{center|Classic}} || {{center|<ref name="26bitaddr" group="a"/>}}
|-
| {{center|ARMv3}} || {{center|32}} || [[ARM6]], [[ARM7]] || || {{center|Classic}} || {{center|<ref name="26bitcomp" group="a">ARMv3 included a compatibility mode to support the [[26-bit#Early ARM processors|26-bit addresses]] of earlier versions of the architecture. This compatibility mode ''optional'' in ARMv4, and removed entirely in ARMv5.</ref>}}
|-
| {{center|ARMv4}} || {{center|32}} || [[List of ARM microprocessor cores|ARM8]]|| [[StrongARM]], FA526, ZAP Open Source Processor Core || {{center|Classic}} || {{center|<ref name="26bitcomp" group="a"/>}}

{{center|<ref>{{GitHub|krevanth/ZAP}}</ref>}}
|-
| {{center|ARMv4T}} || {{center|32}} || [[ARM7TDMI]], [[ARM9TDMI]], [[ARM SecurCore|SecurCore]] SC100 || || {{center|Classic}} || {{center|<ref name="26bitcomp" group="a"/>}}
|-
| {{center|ARMv5TE}} || {{center|32}} || [[ARM7EJ]], [[ARM9E]], [[ARM10E]] || [[XScale]], FA626TE, Feroceon, PJ1/Mohawk || {{center|Classic}} ||
|-
| {{center|ARMv6}} || {{center|32}} || [[ARM11]] || || {{center|Classic}} ||
|-
| {{center|ARMv6-M}} || {{center|32}} || [[ARM Cortex-M#Cortex-M0|ARM Cortex-M0]], {{nowrap|[[ARM Cortex-M#Cortex-M0+|ARM Cortex-M0+]]}}, {{nowrap|[[ARM Cortex-M#Cortex-M1|ARM Cortex-M1]]}}, [[ARM SecurCore|SecurCore]] SC000 || || {{center|[[Microcontroller]]}} ||
|-
| {{center|ARMv7-M}} || {{center|32}} || [[ARM Cortex-M#Cortex-M3|ARM Cortex-M3]], [[ARM SecurCore|SecurCore]] SC300 || [[Apple M7]] motion coprocessor|| {{center|Microcontroller}} ||
|-
| {{center|ARMv7E-M}} || {{center|32}} || [[ARM Cortex-M#Cortex-M4|ARM Cortex-M4]], {{nowrap|[[ARM Cortex-M#Cortex-M7|ARM Cortex-M7]]}} || || {{center|Microcontroller}} ||
|-
| {{center|ARMv8-M}} || {{center|32}} || [[ARM Cortex-M#Cortex-M23|ARM Cortex-M23]],<ref>{{cite web |url=https://www.arm.com/products/processors/cortex-m/cortex-m23-processor.php |title=Cortex-M23 Processor |publisher=ARM |access-date=27 October 2016}}</ref> [[ARM Cortex-M#Cortex-M33|ARM Cortex-M33]]<ref>{{cite web |url=https://www.arm.com/products/processors/cortex-m/cortex-m33-processor.php |title=Cortex-M33 Processor |publisher=ARM |access-date=27 October 2016}}</ref> || || {{center|Microcontroller}} || {{center|<ref>{{cite web |url=https://www.arm.com/about/newsroom/armv8-m-architecture-simplifies-security-for-smart-embedded-devices.php |title=ARMv8-M Architecture Simplifies Security for Smart Embedded |publisher=ARM |access-date=10 November 2015}}</ref>}}
|-
|{{center|ARMv8.1-M}}
|{{center|32}}
|[[ARM Cortex-M#Cortex-M55|ARM Cortex-M55]], [[ARM Cortex-M#Cortex-M85|ARM Cortex-M85]]
|
|{{center|Microcontroller}}
|{{center|<ref>{{Cite web |last=Ltd |first=Arm |title=M-Profile Architectures |url=https://www.arm.com/architecture/cpu/m-profile |access-date=2023-08-29 |website=Arm {{!}} The Architecture for the Digital World |language=en}}</ref>}}
|-
| {{center|ARMv7-R}} || {{center|32}} || [[ARM Cortex-R4]], {{nowrap |[[ARM Cortex-R5]]}}, {{nowrap|[[ARM Cortex-R7]]}}, {{nowrap|[[ARM Cortex-R8]]}} || || {{center|[[Real-time computing|Real-time]]}} ||
|-
| rowspan="2" | {{center|ARMv8-R}} || {{center|32}} || [[ARM Cortex-R52]] || || {{center|Real-time}} || {{center|<ref>{{cite web |url=https://www.arm.com/products/processors/instruction-set-architectures/armv8-r-architecture.php |title=ARMv8-R Architecture |access-date=10 July 2015}}</ref><ref>{{cite web |url=https://arm.com/files/pdf/ARMv8R__Architecture_Oct13.pdf |title=ARM Cortex-R Architecture |first=Simon |last=Craske |publisher=Arm Holdings |date=October 2013 |access-date=1 February 2014 |archive-url=https://web.archive.org/web/20140406081724/https://arm.com/files/pdf/ARMv8R__Architecture_Oct13.pdf |archive-date=6 April 2014}}</ref><ref>{{cite news |last1=Smith |first1=Ryan |title=ARM Announces Cortex-R52 CPU: Deterministic & Safe, for ADAS & More |url=https://www.anandtech.com/show/10690/arm-announces-the-cortexr52-cpu-deterministic-safe-for-adas-more |access-date=20 September 2016 |website=[[AnandTech]] |date=20 September 2016}}</ref>}}
|-
|{{center|64}}
|[https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82 ARM Cortex-R82]
|
|{{center|Real-time}}
|
|-
| {{center|ARMv7-A}} || {{center|32}} || [[ARM Cortex-A5]], {{nowrap|[[ARM Cortex-A7]]}}, {{nowrap|[[ARM Cortex-A8]]}}, {{nowrap|[[ARM Cortex-A9]]}}, {{nowrap |[[ARM Cortex-A12]]}}, {{nowrap|[[ARM Cortex-A15]]}}, {{nowrap|[[ARM Cortex-A17]]}} || [[Qualcomm Snapdragon|Qualcomm]] [[Scorpion (CPU)|Scorpion]]/[[Krait (CPU)|Krait]], PJ4/Sheeva, Apple Swift ([[Apple A6|A6]], [[Apple A6X|A6X]]) || {{center|[[Application software|Application]]}} ||
|-
| rowspan="3" | {{center|ARMv8-A}} || {{center|32}} || {{nowrap |[[ARM Cortex-A32]]<ref>{{cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a32 |title=Cortex-A32 Processor |publisher=ARM |access-date=10 October 2019}}</ref>}} || || {{center|Application}} ||
|-
|{{center|[[64-bit computing|64]]/32}} || {{nowrap|[[ARM Cortex-A35]],<ref name="Cortex-A35 Processor">{{cite web |url=https://www.arm.com/products/processors/cortex-a/cortex-a35-processor.php |title=Cortex-A35 Processor |publisher=ARM |access-date=10 November 2015}}</ref>}} {{nowrap|[[ARM Cortex-A53]]}}, {{nowrap |[[ARM Cortex-A57]],<ref name="cortex-a50 announce"/>}} {{nowrap|[[ARM Cortex-A72]],<ref>{{cite web |url=https://www.arm.com/products/processors/cortex-a/cortex-a72-processor.php |title=Cortex-A72 Processor |publisher=ARM |access-date=10 July 2015}}</ref>}} {{nowrap|[[ARM Cortex-A73]]<ref>{{cite web |url=https://www.arm.com/products/processors/cortex-a/cortex-a73-processor.php |title=Cortex-A73 Processor |publisher=ARM |access-date=2 June 2016}}</ref>}} || [[Applied Micro Circuits Corporation#History|X-Gene]], [[Project Denver|Nvidia Denver 1/2]], [[Cavium ThunderX]], [[AMD K12]], Apple Cyclone ([[Apple A7|A7]])/Typhoon ([[Apple A8|A8]], [[Apple A8X|A8X]])/Twister ([[Apple A9|A9]], [[Apple A9X|A9X]])/Hurricane+Zephyr ([[Apple A10|A10]], [[Apple A10X|A10X]]), [[Qualcomm Snapdragon|Qualcomm]] [[Kryo (microarchitecture)|Kryo]], Samsung M1/M2 ("Mongoose") /M3 ("Meerkat") || {{center|Application}} ||
{{center|<ref>{{cite web |url=https://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php |title=ARMv8-A Architecture |access-date=10 July 2015}}</ref><ref name="v8arch"/><ref>{{cite web |url=https://semiaccurate.com/2014/06/03/cavium-thunder-x-ups-arm-core-count-48-single-chip/ |title=Cavium Thunder X ups the ARM core count to 48 on a single chip |date=3 June 2014 |publisher=[[SemiAccurate]]}}</ref><ref>{{cite web |url=https://finance.yahoo.com/news/cavium-supercomputing-2014-120500860.html |title=Cavium at Supercomputing 2014 |date=17 November 2014 |website=Yahoo Finance |url-status=dead |archive-url=https://web.archive.org/web/20151016102603/http://finance.yahoo.com/news/cavium-supercomputing-2014-120500860.html |archive-date=16 October 2015 |access-date=15 January 2017}}</ref><ref>{{cite web |url=https://www.eweek.com/servers/cray-to-evaluate-arm-chips-in-its-supercomputers/ |title=Cray to Evaluate ARM Chips in Its Supercomputers |first=Jeff |last=Burt |date=17 November 2014 |website=eWeek}}</ref><ref>{{cite web |url=https://www.anandtech.com/show/9781/samsung-announces-exynos-8890-with-cat1213-modem-and-custom-cpu |title=Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU |website=[[AnandTech]]}}</ref>
}}
|-
|{{center|[[64-bit computing|64]]}}
|{{nowrap|[[ARM Cortex-A34]]<ref>{{cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34 |title=Cortex-A34 Processor |publisher=ARM |access-date=10 October 2019}}</ref>}}
|
|{{center|Application}}
|
|-
| {{center|ARMv8.1-A}}|| {{center|64/32}} ||  || [[Cavium ThunderX2]]|| {{center|Application}}|| {{center|<ref>{{cite web |url=https://reviews.llvm.org/D21500 |title=D21500 [AARCH64] Add support for Broadcom Vulcan |website=reviews.llvm.org}}</ref>}}
|-
| rowspan="2" | {{center|ARMv8.2-A}}|| {{center|64/32}} || {{nowrap|[[ARM Cortex-A55]],<ref>{{cite web |url=https://developer.arm.com/products/processors/cortex-a/cortex-a55 |title=Cortex-A55 Processor |publisher=ARM |access-date=29 May 2017}}</ref>}} {{nowrap|[[ARM Cortex-A75]],<ref>{{cite web |url=https://developer.arm.com/products/processors/cortex-a/cortex-a75 |title=Cortex-A75 Processor |publisher=ARM |access-date=29 May 2017}}</ref>}} {{nowrap|[[ARM Cortex-A76]]}},<ref>{{cite web |url=https://developer.arm.com/products/processors/cortex-a/cortex-a76 |title=Cortex-A76 Processor |publisher=ARM |access-date=11 October 2018}}</ref> {{nowrap|[[ARM Cortex-A77]]}}, {{nowrap|[[ARM Cortex-A78]]}}, {{nowrap|[[ARM Cortex-X1]]}}, {{nowrap|[[ARM Neoverse N1]]}}
|[[Project Denver|Nvidia Carmel]], Samsung M4 ("Cheetah"), [[Fujitsu A64FX]] (ARMv8 SVE 512-bit) || {{center|Application}}|| {{center|<ref>{{cite web |url=https://community.arm.com/processors/b/blog/posts/arm-architecture-armv8-2-a-evolution-and-delivery |title=ARM Architecture – ARMv8.2-A evolution and delivery |author=Berenice Mann |website=community.ARM.com |date=April 2017}}</ref><ref>{{cite web |url=https://www.anandtech.com/show/14645/samsung-announces-exynos-9825-first-7nm-euv-silicon-chip |title=Samsung Announces the Exynos 9825 SoC: First 7nm EUV Silicon Chip |last=Frumusanu |first=Andrei |website=[[AnandTech]] |access-date=11 October 2019}}</ref><ref>{{cite web |url=http://images.firstxw.com/view/230119.html |title=Fujitsu began to produce Japan's billions of super-calculations with the strongest ARM processor A64FX |website=China IT News |access-date=17 August 2019 |quote=ARMv8 SVE (Scalable Vector Extension) chip, which uses 512bit floating point. |archive-url=https://web.archive.org/web/20190620065621/http://images.firstxw.com/view/230119.html |archive-date=20 June 2019 |url-status=dead}}</ref>
}}
|-
|{{center|64}} || {{nowrap|ARM Cortex-A65}}, {{nowrap|[[ARM Neoverse E1]]}} with [[simultaneous multithreading]] (SMT), {{nowrap|ARM Cortex-A65AE}}<ref>{{cite web |url=https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a65ae |title=Cortex-A65AE – ARM |website=ARM |quote=can execute two-threads in parallel on each cycle. Each thread can be at different exception levels and run different operating systems. |access-date=8 April 2020}}</ref> (also having <!--ARMv8.3 (LDAPR instructions only) and--> e.g. ARMv8.4 Dot Product; made for <!-- automotive applications and --> safety critical tasks such as [[advanced driver-assistance systems]] (ADAS)<!-- , "multicore fault-tolerance with ASIL D hardware metrics"-->) || Apple Monsoon+Mistral ([[Apple A11|A11]]) (September 2017) || {{center|Application}}||
|-
| rowspan="2" |{{center|ARMv8.3-A}}
|{{center|64/32}} || 
|
|{{center|Application}}
|
|-
|{{center|64}} ||  || Apple Vortex+Tempest ([[Apple A12|A12]], [[Apple A12X|A12X]], [[Apple A12Z|A12Z]]), Marvell ThunderX3 (v8.3+)<ref>{{cite web |title=Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen ARM Server Processor |url=https://www.anandtech.com/show/15621/marvell-announces-thunderx3-96-cores-384-thread-3rd-gen-arm-server-processor |last=Frumusanu |first=Andrei |website=[[AnandTech]] |access-date=26 May 2020}}</ref>
|{{center|Application}}||
|-
| rowspan="2" | {{center|ARMv8.4-A}} || {{center|64/32}} || || || {{center|Application}} ||
|-
|{{center|64}} || [[ARM Neoverse V1]] || Apple Lightning+Thunder ([[Apple A13|A13]]), Apple Firestorm+Icestorm ([[Apple A14|A14]], [[Apple M1|M1]]) || {{center|Application}}||
|-
| rowspan="2" |{{center|ARMv8.5-A}}
|{{center|64/32}} || 
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|{{center|Application}}
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|-
|{{center|64}} || 
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|{{center|Application}}
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|-
|{{center|ARMv8.6-A}}
|{{center|64}} || 
|Apple Avalanche+Blizzard ([[Apple A15|A15]], [[Apple M2|M2]]), Apple Everest+Sawtooth ([[Apple A16|A16]]),<ref>{{Cite web |title=AArch64: add support for newer Apple CPUs · apple/llvm-project@677da09 |url=https://github.com/apple/llvm-project/commit/677da09d0259d7530d32e85cb561bee15f0066e2 |access-date=2022-09-23 |website=GitHub |language=en}}</ref> Apple Coll ([[Apple A17|A17]]), Apple Ibiza/Lobos/Palma ([[Apple M3|M3]])
|{{center|Application}}
|
|-
|{{center|ARMv8.7-A}}
|{{center|64}}|| 
|
|{{center|Application}}
|{{center|<ref>{{cite web |title=New features for the Armv8-A architecture - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020 |access-date=2021-12-28 |website=community.arm.com |date=21 September 2020 |language=en}}</ref>}}
|-
|{{center|ARMv8.8-A}}
|{{center|64}}
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|{{center|ARMv8.9-A}}
|{{center|64}}
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|{{center|ARMv9.0-A}}
|{{center|64}}
| [[ARM Cortex-A510]], [[ARM Cortex-A710]], [[ARM Cortex-A715]], [[ARM Cortex-X2]], [[ARM Cortex-X3]], [[ARM Neoverse E2]], [[ARM Neoverse N2]], [[ARM Neoverse V2]]
|
|{{center|Application}}
|{{center|<ref>{{cite web |title=Arm's solution to the future needs of AI, security and specialized computing is v9 |url=https://www.arm.com/company/news/2021/03/arms-answer-to-the-future-of-ai-armv9-architecture |access-date=2021-08-16 |website=Arm}}</ref><ref>{{cite web |title=First Armv9 Cortex CPUs for Consumer Compute |url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/first-armv9-cpu-cores |access-date=2021-08-16 |website=community.arm.com|date=25 May 2021 }}</ref>}}
|-
|{{center|ARMv9.1-A}}
|{{center|64}}
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|{{center|Application}}
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|{{center|ARMv9.2-A}}
|{{center|64}}
|[[ARM Cortex-A520]], [[ARM Cortex-A720]], [[ARM Cortex-X4]], [[ARM Neoverse#Neoverse V3|ARM Neoverse V3]],<ref>{{Cite web |title=Documentation – Arm Developer |url=https://developer.arm.com/documentation/107734/0001/The-Neoverse--V3--core |access-date=2024-10-03 |website=developer.arm.com}}</ref> [[ARM Cortex-X925]],<ref>{{Cite web |title=Documentation – Arm Developer |url=https://developer.arm.com/documentation/102807/0001/The-Cortex-X925--core?lang=en |access-date=2024-10-03 |website=developer.arm.com}}</ref> [[ARM Cortex-A320]]<ref>{{Cite web |title=Documentation – Arm Developer |url=https://developer.arm.com/Processors/Cortex-A320 |access-date=2024-10-03 |website=developer.arm.com}}</ref>
|Apple Donan/BravaChop/Brava ([[Apple M4]]),<ref>{{Cite web |title=Apple M4 Support Added To The LLVM Compiler, Confirming Its ISA Capabilities |url=https://www.phoronix.com/news/Apple-M4-Added-To-LLVM-Clang |access-date=2024-06-15 |website=www.phoronix.com |language=en}}</ref> Apple Tupai/Tahiti ([[Apple A18|A18]])
|{{center|Application}}
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|-
|{{center|ARMv9.3-A}}
|{{center|64}}
|{{TBA}}
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|{{center|Application}}
|{{center|<ref>{{Cite web |date=2021-09-08 |title=Arm A-Profile Architecture Developments 2021 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2021 |access-date=2023-09-25 |website=community.arm.com |language=en}}</ref>}}
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|{{center|ARMv9.4-A}}
|{{center|64}}
|{{TBA}}
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|{{center|Application}}
|{{center|<ref>{{Cite web |date=2022-09-29 |title=Arm A-Profile Architecture Developments 2022 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022 |access-date=2023-09-25 |website=community.arm.com |language=en}}</ref>}}
|-
|{{center|ARMv9.5-A}}
|{{center|64}}
|{{TBA}}
|
|{{center|Application}}
|{{center|<ref>{{Cite web |date=2022-09-29 |title=Arm A-Profile Architecture Developments 2023 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023 |access-date=2024-10-11 |website=community.arm.com |language=en}}</ref>}}
|-
|{{center|ARMv9.6-A}}
|{{center|64}}
|{{TBA}}
|
|{{center|Application}}
|{{center|<ref>{{Cite web |date=2022-09-29 |title=Arm A-Profile Architecture Developments 2024 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2024 |access-date=2024-10-11 |website=community.arm.com |language=en}}</ref>}}
|}
{{reflist|group=a}}

Arm provides a list of vendors who implement ARM cores in their design (application specific standard products (ASSP), microprocessor and microcontrollers).<ref>{{cite web |url=http://infocenter.arm.com/help/topic/com.arm.doc.faqs/attached/6745/0141_5linecard.pdf |title=Line Card |year=2003 |access-date=1 October 2012}}</ref>

===Example applications of ARM cores===
[[File:Quad-core Android "mini PC", with a microSD card next to it for a size comparison.jpg|thumb|right|upright=1.2|[[Tronsmart]] MK908, a [[Rockchip]]-based quad-core Android "mini PC", with a microSD card next to it for a size comparison]]
{{Main |List of products using ARM processors}}
<!-- Please consider carefully before expanding the list below. The main list is in the article linked to above. -->
ARM cores are used in a number of products, particularly [[personal digital assistant|PDA]]s and [[smartphone]]s. Some [[computing]] examples are [[Microsoft]]'s [[Surface (2012 tablet)|first generation Surface]], [[Surface 2]] and [[Pocket PC]] devices (following [[Pocket PC 2002|2002]]), [[Apple Inc.|Apple]]'s [[iPad]]s, and [[Asus]]'s [[Asus Eee Pad Transformer|Eee Pad Transformer]] [[tablet computer]]s, and several [[Chromebook]] laptops. Others include Apple's [[iPhone]] [[smartphone]]s and [[iPod]] [[portable media player]]s, [[Canon PowerShot]] [[digital camera]]s, [[Nintendo Switch]] hybrid, the [[Wii]] security processor and [[Nintendo 3DS|3DS]] [[handheld game console]]s, and [[TomTom]] turn-by-turn [[GPS navigation device|navigation systems]].

In 2005, Arm took part in the development of [[Manchester University]]'s computer [[SpiNNaker]], which used ARM cores to simulate the [[human brain]].<ref>{{cite magazine |url=https://www.eetimes.com/electronics-news/4217840/Million-ARM-cores-brain-simulator |title=One Million ARM Cores Linked to Simulate Brain |access-date=2 August 2011 |last=Parrish |first=Kevin |date=14 July 2011 |magazine=EE Times}}</ref>

ARM chips are also used in [[Raspberry Pi]], [[BeagleBoard]], [[BeagleBone]], [[PandaBoard]], and other [[single-board computer]]s, because they are very small, inexpensive, and consume very little power.

=={{anchor|32-bit|ARMv7-A|AArch32}}32-bit architecture==
[[File:Raspberry-Pi-2-Bare-BR.jpg|alt=|thumb|An ARMv7 was used to power older versions of the popular [[Raspberry Pi]] single-board computers like this Raspberry Pi 2 from 2015.]]
[[File:Cubox.png|thumb|right|upright=1.2|An ARMv7 is also used to power the [[CuBox]] family of single-board computers.]]

{{See also|Comparison of ARMv7-A processors}}
The 32-bit ARM architecture ('''ARM32'''), such as '''ARMv7-A''' (implementing AArch32; see [[#Armv8-A|section on Armv8-A]] for more on it), was the most widely used architecture in mobile devices {{as of|2011|lc=y}}.<ref name="popular">{{cite journal |last1=Fitzpatrick |first1=J. |title=An Interview with Steve Furber |doi=10.1145/1941487.1941501 |journal=[[Communications of the ACM]] |volume=54 |issue=5 |pages=34–39 |year=2011 |doi-access=free}}</ref>

Since 1995, various versions of the ''ARM Architecture Reference Manual'' (see {{section link||External links}}) have been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and version seven of the architecture, ARMv7, defines three architecture "profiles":
* A-profile, the "Application" profile, implemented by 32-bit cores in the [[ARM Cortex-A|Cortex-A]] series and by some non-ARM cores
* R-profile, the "Real-time" profile, implemented by cores in the [[ARM Cortex-R|Cortex-R]] series
* M-profile, the "Microcontroller" profile, implemented by most cores in the [[ARM Cortex-M|Cortex-M]] series

Although the architecture profiles were first defined for ARMv7, ARM subsequently defined the ARMv6-M architecture (used by the Cortex [[ARM Cortex-M0|M0]]/[[ARM Cortex-M0+|M0+]]/[[ARM Cortex-M1|M1]]) as a subset of the ARMv7-M profile with fewer instructions.

===CPU modes===
Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes, depending on the implemented architecture features. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.<ref name="Chdddhea">{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdddhea.html |title=Processor mode |publisher=[[Arm Holdings]] |access-date=26 March 2013}}</ref>
* ''User mode:'' The only non-privileged mode.
* ''FIQ mode:'' A privileged mode that is entered whenever the processor accepts a [[fast interrupt request]].
* ''IRQ mode:'' A privileged mode that is entered whenever the processor accepts an interrupt.
* ''Supervisor (svc) mode:'' A privileged mode entered whenever the CPU is reset or when an SVC instruction is executed.
* ''Abort mode:'' A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.
* ''Undefined mode:'' A privileged mode that is entered whenever an undefined instruction exception occurs.
* ''System mode (ARMv4 and above):'' The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the Current Program Status Register (CPSR) from another privileged mode (not from user mode).
* ''Monitor mode (ARMv6 and ARMv7 Security Extensions, ARMv8 EL3):'' A monitor mode is introduced to support TrustZone extension in ARM cores.
* ''Hyp mode (ARMv7 Virtualization Extensions, ARMv8 EL2):'' A hypervisor mode that supports [[Popek and Goldberg virtualization requirements]] for the non-secure operation of the CPU.<ref name="2012-lpc-arm-zyngier">{{cite web |url=https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-arm-zyngier.pdf |title=KVM/ARM |access-date=14 February 2023}}</ref><ref>{{cite conference |title=Extensions to the ARMv7-A Architecture |first=David |last=Brash |conference=2010 IEEE Hot Chips 22 Symposium (HCS) |date=August 2010 |pages=1–21 |doi=10.1109/HOTCHIPS.2010.7480070 |isbn=978-1-4673-8875-7 |s2cid=46339775 }}</ref>
* ''Thread mode (ARMv6-M, ARMv7-M, ARMv8-M):'' A mode which can be specified as either privileged or unprivileged. Whether the Main Stack Pointer (MSP) or Process Stack Pointer (PSP) is used can also be specified in CONTROL register with privileged access. This mode is designed for user tasks in RTOS environment but it is typically used in bare-metal for super-loop.
* ''Handler mode (ARMv6-M, ARMv7-M, ARMv8-M):'' A mode dedicated for exception handling (except the RESET which are handled in Thread mode). Handler mode always uses MSP and works in privileged level.

===Instruction set===
The original (and subsequent) ARM implementation was hardwired without [[microcode]], like the much simpler [[8-bit computing|8-bit]] [[MOS Technology 6502|6502]] processor used in prior Acorn microcomputers.

The 32-bit ARM architecture (and the 64-bit architecture for the most part) includes the following RISC features:
* [[Load–store architecture]].
* No support for [[data structure alignment|unaligned memory accesses]] in the original version of the architecture. ARMv6 and later, except some microcontroller versions, support unaligned accesses for half-word and single-word load/store instructions with some limitations, such as no guaranteed [[linearizability|atomicity]].<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15414.html |title=How does the ARM Compiler support unaligned accesses? |year=2011 |access-date=5 October 2013 |url-status=dead |archive-url=https://web.archive.org/web/20131014084800/http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka15414.html |archive-date=14 October 2013}}</ref><ref>{{cite web |url=http://www.heyrick.co.uk/armwiki/Unaligned_data_access |title=Unaligned data access |access-date=5 October 2013}}</ref>
* Uniform 16 × 32-bit [[register file]] (including the program counter, stack pointer and the link register).
* Fixed instruction width of 32&nbsp;bits to ease decoding and [[instruction pipelining|pipelining]], at the cost of decreased [[code density]]. Later, the [[#Thumb|Thumb instruction set]] added 16-bit instructions and increased code density.
* Mostly single clock-cycle execution.

To compensate for the simpler design, compared with processors like the Intel 80286 and [[Motorola 68020]], some additional design features were used:
* Conditional execution of most instructions reduces branch overhead and compensates for the lack of a [[branch predictor]] in early chips.
* Arithmetic instructions alter [[Condition Code Register|condition code]]s only when desired.
* 32-bit [[barrel shifter]] can be used without performance penalty with most arithmetic instructions and address calculations.
* Has powerful indexed [[addressing mode]]s.
* A [[link register]] supports fast leaf function calls.
* A simple, but fast, 2-priority-level [[interrupt]] subsystem has switched register banks.

====Arithmetic instructions====
ARM includes integer arithmetic operations for add, subtract, and multiply; some versions of the architecture also support divide operations.

ARM supports 32-bit × 32-bit multiplies with either a 32-bit result or 64-bit result, though Cortex-M0 / M0+ / M1 cores do not support 64-bit results.<ref name="M0-TRM">{{cite web |url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf |title=Cortex-M0 r0p0 Technical Reference Manual |website=Arm}}</ref> Some ARM cores also support 16-bit × 16-bit and 32-bit × 16-bit multiplies.

The divide instructions are only included in the following ARM architectures:
* Armv7-M and Armv7E-M architectures always include divide instructions.<ref>{{cite web |url=https://developer.arm.com/documentation/ddi0403/latest/ |title=ARMv7-M Architecture Reference Manual |publisher=Arm |access-date=18 July 2022}}</ref>
* Armv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in its 32-bit instruction set.<ref name="ARMv7-AR-Ref">{{cite web |url=https://developer.arm.com/documentation/ddi0406/latest |title=ARMv7-A and ARMv7-R Architecture Reference Manual; Arm Holdings |publisher=arm.com |access-date=19 January 2013}}</ref>
* Armv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instruction sets, or implemented if the Virtualization Extensions are included.<ref name="ARMv7-AR-Ref"/>

====Registers====
{| class="wikitable" style="float: right; margin-left: 1.5em; margin-right: 0; margin-top: 0;"
|+ Registers across CPU modes
|-
! usr !! sys !! svc !! abt !! und !! [[Interrupt request|irq]] !! [[Fast interrupt request|fiq]]
|-
| colspan="7" style="text-align:center;"| R0
|-
| colspan="7" style="text-align:center;"| R1
|-
| colspan="7" style="text-align:center;"| R2
|-
| colspan="7" style="text-align:center;"| R3
|-
| colspan="7" style="text-align:center;"| R4
|-
| colspan="7" style="text-align:center;"| R5
|-
| colspan="7" style="text-align:center;"| R6
|-
| colspan="7" style="text-align:center;"| R7
|- align=center
| colspan=6 | R8 || R8_fiq
|- align=center
| colspan=6 | R9 || R9_fiq
|- align=center
| colspan=6 | R10 || R10_fiq
|- align=center
| colspan=6 | R11 || R11_fiq
|- align=center
| colspan=6 | R12 || R12_fiq
|- align=center
| colspan=2 | R13 || R13_svc || R13_abt || R13_und || R13_irq || R13_fiq
|- align=center
| colspan=2 | R14 || R14_svc || R14_abt || R14_und || R14_irq || R14_fiq
|-
| colspan="7" style="text-align:center;"| R15
|-
| colspan="7" style="text-align:center;"| CPSR
|- align=center
| colspan=2 | || SPSR_svc || SPSR_abt || SPSR_und || SPSR_irq || SPSR_fiq
|}

Registers R0 through R7 are the same across all CPU modes; they are never banked.

Registers R8 through R12 are the same across all CPU modes except FIQ mode.  FIQ mode has its own distinct R8 through R12 registers.

R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.

Aliases:
* R13 is also referred to as SP, the [[stack pointer]].
* R14 is also referred to as LR, the [[link register]].
* R15 is also referred to as PC, the [[program counter]].

The Current Program Status Register (CPSR) has the following 32&nbsp;bits.<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/I27695.html |title=ARM Information Center |access-date=10 July 2015}}</ref>
* M (bits 0–4) is the processor mode bits.
* T (bit 5) is the Thumb state bit.
* F (bit 6) is the FIQ disable bit.
* I (bit 7) is the IRQ disable bit.
* A (bit 8) is the imprecise data abort disable bit.
* E (bit 9) is the data endianness bit.
* IT (bits 10–15 and 25–26) is the if-then state bits.
* GE (bits 16–19) is the greater-than-or-equal-to bits.
* DNM (bits 20–23) is the do not modify bits.
* J (bit 24) is the Java state bit.
* Q (bit 27) is the sticky overflow bit.
* V (bit 28) is the overflow bit.
* C (bit 29) is the carry/borrow/extend bit.
* Z (bit 30) is the zero bit.
* N (bit 31) is the negative/less than bit.

====Conditional execution====
Almost every ARM instruction has a conditional execution feature called [[predication (computer architecture)|predication]], which is implemented with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU architectures only have condition codes on branch instructions.<ref>{{cite web |title=Condition Codes 1: Condition flags and codes |url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/condition-codes-1-condition-flags-and-codes |website=ARM Community |date=11 September 2013 |access-date=26 September 2019}}</ref>

Though the predicate takes up four of the 32&nbsp;bits in an instruction code, and thus cuts down significantly on the encoding bits available for displacements in memory access instructions, it avoids branch instructions when generating code for small [[conditional (programming)|<code>if</code> statements]]. Apart from eliminating the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.

An algorithm that provides a good example of conditional execution is the subtraction-based [[Euclidean algorithm]] for computing the [[greatest common divisor]].  In the [[C (programming language)|C programming language]], the algorithm can be written as:

<syntaxhighlight lang="c">
int gcd(int a, int b) {
  while (a != b)  // We enter the loop when a < b or a > b, but not when a == b
    if (a > b)   // When a > b we do this
      a -= b;
    else         // When a < b we do that (no "if (a < b)" needed since a != b is checked in while condition)
      b -= a;
  return a;
}
</syntaxhighlight>

The same algorithm can be rewritten in a way closer to target ARM [[instruction set architecture|instructions]] as:

<syntaxhighlight lang="c">
loop:
    // Compare a and b
    GT = a > b;
    LT = a < b;
    NE = a != b;

    // Perform operations based on flag results
    if (GT) a -= b;    // Subtract *only* if greater-than
    if (LT) b -= a;    // Subtract *only* if less-than
    if (NE) goto loop; // Loop *only* if compared values were not equal
    return a;
</syntaxhighlight>
and coded in [[assembly language]] as:<!-- using nasm because "gas", although correct, does not recognize all the insns. the nasm lexer just looks for all uppercase on the other hand. -->
<syntaxhighlight lang="nasm">
; assign a to register r0, b to r1
loop:   CMP    r0, r1       ; set condition "NE" if (a ≠ b),
                            ;               "GT" if (a > b),
                            ;            or "LT" if (a < b)
        SUBGT  r0, r0, r1   ; if "GT" (Greater Than), then a = a − b
        SUBLT  r1, r1, r0   ; if "LT" (Less    Than), then b = b − a
        BNE  loop           ; if "NE" (Not Equal), then loop
        B    lr             ; return
</syntaxhighlight>
which avoids the branches around the <code>then</code> and <code>else</code> clauses. If <code>r0</code> and <code>r1</code> are equal then neither of the <code>SUB</code> instructions will be executed, eliminating the need for a conditional branch to implement the <code>while</code> check at the top of the loop, for example had <code>SUBLE</code> (less than or equal) been used.

One of the ways that Thumb code provides a more dense encoding is to remove the four-bit selector from non-branch instructions.

====Other features====
Another feature of the [[instruction set]] is the ability to fold shifts and rotates into the ''data processing'' (arithmetic, logical, and register-register move) instructions, so that, for example, the statement in [[C (programming language)|C]] language:

<syntaxhighlight lang="c">a += (j << 2);</syntaxhighlight>

could be rendered as a one-word, one-cycle instruction:<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0214b/ch09s01s02.html |title=9.1.2. Instruction cycle counts}}</ref>

<syntaxhighlight lang="nasm">ADD  Ra, Ra, Rj, LSL #2</syntaxhighlight>

This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently.

The ARM processor also has features rarely seen in other RISC architectures, such as [[program counter|PC]]-relative addressing (indeed, on the 32-bit<ref name="v8arch">{{cite web |url=https://www.arm.com/files/downloads/ARMv8_Architecture.pdf |title=ARMv8-A Technology Preview |year=2011 |access-date=31 October 2011 |first=Richard |last=Grisenthwaite |archive-url=https://web.archive.org/web/20111111161327/https://www.arm.com/files/downloads/ARMv8_Architecture.pdf |archive-date=11 November 2011}}</ref> ARM the [[program counter|PC]] is one of its 16&nbsp;registers) and pre- and post-increment addressing modes.

The ARM instruction set has increased over time. Some early ARM processors (before ARM7TDMI), for example, have no instruction to store a two-byte quantity.

====Pipelines and other implementation issues====
The ARM7 and earlier implementations have a three-stage [[instruction pipelining|pipeline]]; the stages being fetch, decode, and execute. Higher-performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster [[adder (electronics)|adder]] and more extensive [[branch prediction]] logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier; hence the added "M".

====Coprocessors====
The ARM architecture (pre-Armv8) provides a non-intrusive way of extending the instruction set using "coprocessors" that can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logically into 16&nbsp;coprocessors with numbers from 0 to 15, coprocessor&nbsp;15 (cp15) being reserved for some typical control functions like managing the caches and [[memory management unit|MMU]] operation on processors that have one.

In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space, into the coprocessor space, or by connecting to another device (a bus) that in turn attaches to the processor. Coprocessor accesses have lower latency, so some peripherals—for example, an XScale interrupt controller—are accessible in both ways: through memory and through coprocessors.

In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operations to support a specific set of HDTV transcoding primitives.

==={{Anchor|CoreSight}}Debugging===
{{More citations needed section|date=March 2011}}
All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using [[JTAG]] support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de facto debug standard, though not architecturally guaranteed.

The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.

There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.

====Debug Access Port====
The Debug Access Port (DAP) is an implementation of an ARM Debug Interface.<ref>
{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0314h/Babdadfc.html |title=CoreSight Components: About the Debug Access Port}}
</ref>
There are two different supported implementations, the Serial Wire [[JTAG]] Debug Port (SWJ-DP) and the Serial Wire Debug Port (SW-DP).<ref>
{{cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0179b/ar01s01s03.html |title=The Cortex-M3: Debug Access Port (DAP)}}
</ref>
CMSIS-DAP is a standard interface that describes how various debugging software on a host PC can communicate over USB to firmware running on a hardware debugger, which in turn talks over SWD or JTAG to a CoreSight-enabled ARM Cortex CPU.<ref>
{{cite web |first=Mike |last=Anderson
|url=https://elinux.org/images/7/7f/Manderson5.pdf |title=Understanding ARM HW Debug Options}}
</ref><ref>
{{cite web |url=http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm |title=CMSIS-DAP Debugger User's Guide}}
</ref><ref>
{{cite web |url=https://www.nimblemachines.com/cmsis-dap/ |title=CMSIS-DAP}}
</ref>

===DSP enhancement instructions===
To improve the ARM architecture for [[digital signal processing]] and multimedia applications, DSP instructions were added to the instruction set.<ref>{{cite web |url=https://www.arm.com/products/CPUs/cpu-arch-DSP.html |title=ARM DSP Instruction Set Extensions |website=arm.com |access-date=18 April 2009 |archive-url=https://web.archive.org/web/20090414011837/https://www.arm.com/products/CPUs/cpu-arch-DSP.html |archive-date=14 April 2009 |url-status=live}}</ref> These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T, D, M, and I.

The new instructions are common in [[digital signal processor]] (DSP) architectures. They include variations on signed [[multiply–accumulate operation|multiply–accumulate]], [[saturation arithmetic|saturated add and subtract]], and [[count leading zeros]].

First introduced in 1999, this extension of the core instruction set contrasted with ARM's earlier DSP coprocessor known as Piccolo, which employed a distinct, incompatible instruction set whose execution involved a separate program counter.<ref name="eetimes19990503">{{ cite magazine | url=https://www.eetimes.com/epf-arc-arm-add-dsp-extensions-to-their-risc-cores/ | title=EPF: ARC, ARM add DSP extensions to their RISC cores | website=EE Times | last1=Clarke | first1=Peter | date=3 May 1999 | access-date=15 March 2024 }}</ref> Piccolo instructions employed a distinct register file of sixteen 32-bit registers, with some instructions combining registers for use as 48-bit accumulators and other instructions addressing 16-bit half-registers. Some instructions were able to operate on two such 16-bit values in parallel. Communication with the Piccolo register file involved ''load to Piccolo'' and ''store from Piccolo'' coprocessor instructions via two buffers of eight 32-bit entries. Described as reminiscent of other approaches, notably Hitachi's SH-DSP and Motorola's 68356, Piccolo did not employ dedicated local memory and relied on the bandwidth of the ARM core for DSP operand retrieval, impacting concurrent performance.<ref name="microprocessorreport19961118_piccolo">{{ cite magazine | url=https://www.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/101504.PDF | title=ARM Tunes Piccolo for DSP Performance | magazine=Microprocessor Report | last1=Turley | first1=Jim | date=18 November 1996 | access-date=15 March 2024 }}</ref> Piccolo's distinct instruction set also proved not to be a "good compiler target".<ref name="eetimes19990503"/>

===SIMD extensions for multimedia===
Introduced in the ARMv6 architecture, this was a precursor to Advanced SIMD, also named [[#Advanced SIMD (Neon)|Neon]].<ref>{{cite web |url=https://www.arm.com/products/processors/technologies/dsp-simd.php |title=DSP & SIMD |access-date=10 July 2015}}</ref>

===Jazelle===
<!-- Section header used in redirects -->
{{Main|Jazelle}}
Jazelle DBX (Direct Bytecode eXecution) is a technique that allows [[Java bytecode]] to be executed directly in the ARM architecture as a third execution state (and instruction set) alongside the existing ARM and Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this state is required starting in ARMv6 (except for the ARMv7-M profile), though newer cores only include a trivial implementation that provides no hardware acceleration.

==={{anchor|THUMB}}Thumb===
To improve compiled code density, processors since the ARM7TDMI (released in 1994<ref>{{cite web |url=http://www.atmel.com/Images/DDI0029G_7TDMI_R3_trm.pdf |title=ARM7TDMI Technical Reference Manual |page=ii}}</ref>) have featured the ''Thumb'' [[compressed instruction set]], which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM instruction set.<ref>{{cite book |last=Jaggar |first=Dave |title=ARM Architecture Reference Manual |year=1996 |publisher=Prentice Hall |isbn=978-0-13-736299-8 |pages=6–1}}</ref> Most of the Thumb instructions are directly mapped to normal ARM instructions. The space saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state.

In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general-purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32&nbsp;bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.

Unlike processor architectures with variable length (16- or 32-bit) instructions, such as the Cray-1 and [[Hitachi]] [[SuperH]], the ARM and Thumb instruction sets exist independently of each other. Embedded hardware, such as the [[Game Boy Advance]], typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16-bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory.

The first processor with a Thumb [[instruction decoder]] was the ARM7TDMI. All processors supporting 32-bit instruction sets, starting with ARM9, and including XScale, have included a Thumb instruction decoder. It includes instructions adopted from the Hitachi [[SuperH]] (1992), which was licensed by ARM.<ref name="lwn">{{cite web |url=http://lwn.net/Articles/647636 |title=Resurrecting the SuperH architecture |author=Nathan Willis |date=10 June 2015 |publisher=[[LWN.net]]}}</ref> ARM's smallest processor families (Cortex M0 and M1) implement only the 16-bit Thumb instruction set for maximum performance in lowest cost applications. ARM processors that don't support 32-bit addressing also omit Thumb.

===Thumb-2===
<!-- Section header used in redirects -->
''Thumb-2'' technology was introduced in the ''ARM1156&nbsp;core'', announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory.

Thumb-2 extends the Thumb instruction set with bit-field manipulation, table branches and conditional execution. At the same time, the ARM instruction set was extended to maintain equivalent functionality in both instruction sets. A new "Unified Assembly Language" (UAL) supports generation of either Thumb or ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition, or on its inverse. When compiling into ARM code, this is ignored, but when compiling into Thumb it generates an actual instruction. For example:

<syntaxhighlight lang="nasm">
; if (r0 == r1)
CMP r0, r1
ITE EQ        ; ARM: no code ... Thumb: IT instruction
; then r0 = r2;
MOVEQ r0, r2  ; ARM: conditional; Thumb: condition via ITE 'T' (then)
; else r0 = r3;
MOVNE r0, r3  ; ARM: conditional; Thumb: condition via ITE 'E' (else)
; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE".
</syntaxhighlight>

All ARMv7 chips support the Thumb instruction set. All chips in the Cortex-A series that support ARMv7, all Cortex-R series, and all ARM11 series support both "ARM instruction set state" and "Thumb instruction set state", while chips in the [[ARM Cortex-M|Cortex-M]] series support only the Thumb instruction set.<ref>{{cite web |url=https://www.arm.com/products/CPUs/architecture.html |title=ARM Processor Instruction Set Architecture |publisher=ARM.com |access-date=18 April 2009 |archive-url=https://web.archive.org/web/20090415171228/http://arm.com/products/CPUs/architecture.html |archive-date=15 April 2009 |url-status=live}}</ref><ref>{{cite web |url=http://www.linuxdevices.com/news/NS7814673959.html |title=ARM aims son of Thumb at uCs, ASSPs, SoCs |publisher=Linuxdevices.com |access-date=18 April 2009 |archive-url=https://archive.today/20121209133741/http://www.linuxfordevices.com/c/a/News/ARM-aims-son-of-Thumb-at-uCs-ASSPs-SoCs/ |archive-date=9 December 2012 |url-status=dead}}</ref><ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/I1005458.html |title=ARM Information Center |publisher=Infocenter.arm.com |access-date=18 April 2009}}</ref>

==={{anchor|ThumbEE}}Thumb Execution Environment (ThumbEE)===
''ThumbEE'' (erroneously called ''Thumb-2EE'' in some ARM documentation), which was marketed as Jazelle RCT<ref>{{cite web |url=https://www.arm.com/products/processors/technologies/jazelle.php |archive-url=https://web.archive.org/web/20170602084751/https://www.arm.com/products/processors/technologies/jazelle.php |title=Jazelle |publisher=ARM Ltd. |url-status=dead |archive-date=2 June 2017}}</ref> (Runtime Compilation Target), was announced in 2005 and deprecated in 2011. It first appeared in the ''Cortex-A8'' processor. ThumbEE is a fourth instruction set state, making small changes to the Thumb-2 extended instruction set. These changes make the instruction set particularly suited to code generated at runtime (e.g. by [[just-in-time compilation|JIT compilation]]) in managed ''Execution Environments''. ThumbEE is a target for languages such as [[Java (programming language)|Java]], [[C Sharp (programming language)|C#]], [[Perl]], and [[Python (programming language)|Python]], and allows [[Just-in-time compilation|JIT compilers]] to output smaller compiled code without reducing performance.{{citation needed|date=June 2020}}

New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, and special instructions that call a handler. In addition, because it utilises Thumb-2 technology, ThumbEE provides access to registers r8–r15 (where the Jazelle/DBX Java VM state is held).<ref>{{cite web |url=https://www.arm.com/miscPDFs/10069.pdf |title=ARM strengthens Java compilers: New 16-Bit Thumb-2EE Instructions Conserve System Memory |author=Tom R. Halfhill |year=2005 |archive-url=https://web.archive.org/web/20071005161753/https://www.arm.com/miscPDFs/10069.pdf |archive-date=5 October 2007}}</ref> Handlers are small sections of frequently called code, commonly used to implement high level languages, such as allocating memory for a new object. These changes come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE state.

On 23 November 2011, Arm deprecated any use of the ThumbEE instruction set,<ref>ARM Architecture Reference Manual, Armv7-A and Armv7-R edition, issue C.b, Section A2.10, 25 July 2012.</ref> and Armv8 removes support for ThumbEE.

==={{anchor|VFP}}Floating-point (VFP)===
''VFP'' (Vector Floating Point) technology is a [[floating-point unit]] (FPU) coprocessor extension to the ARM architecture<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473e/CHDHAGGE.html |title=ARM Compiler toolchain Using the Assembler – VFP coprocessor |publisher=ARM.com |access-date=20 August 2014}}</ref> (implemented differently in Armv8 – coprocessors not defined there). It provides low-cost [[single-precision floating-point format|single-precision]] and [[double-precision floating-point format|double-precision floating-point]] computation fully compliant with the ''[[IEEE 754|ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic]]''. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true [[single instruction, multiple data]] (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction,<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdehgeh.html |title=VFP directives and vector notation |publisher=ARM.com |access-date=21 November 2011}}</ref> to be replaced with the much more powerful Advanced SIMD, also named [[#Advanced SIMD (Neon)|Neon]].

Some devices such as the ARM Cortex-A8 have a cut-down ''VFPLite'' module instead of a full VFP module, and require roughly ten times more clock cycles per float operation.<ref name="cortex_a9">{{cite web |url=https://www.shervinemami.info/armAssembly.html#cortex-a9 |title=Differences between ARM Cortex-A8 and Cortex-A9 |publisher=Shervin Emami |access-date=21 November 2011}}</ref> Pre-Armv8 architecture implemented floating-point/SIMD with the coprocessor interface. Other floating-point and/or SIMD units found in ARM-based processors using the coprocessor interface include [[Floating Point Accelerator|FPA]], FPE, [[MMX (instruction set)|iwMMXt]], some of which were implemented in software by trapping but could have been implemented in hardware. They provide some of the same functionality as VFP but are not [[opcode]]-compatible with it. FPA10 also provides [[extended precision]], but implements correct rounding (required by IEEE&nbsp;754) only in single precision.<ref>{{cite web |url=http://chrisacorns.computinghistory.org.uk/docs/GECPlessey/GECPlessey_FPA10DataSheet.pdf |title=FPA10 Data Sheet |author=<!--Not stated--> |date=11 June 1993 |website=chrisacorns.computinghistory.org.uk |publisher=GEC Plessey Semiconductors |access-date=26 November 2020 |quote=In relation to IEEE 754-1985, the FPA achieves conformance in single-precision arithmetic [...] Occasionally, double- and extended-precision multiplications may be produced with an error of 1 or 2 units in the least significant place of the mantissa.}}</ref>

; VFPv1: Obsolete
; VFPv2: An optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures. VFPv2 has 16 64-bit FPU registers.
; VFPv3 or VFPv3-D32: Implemented on most Cortex-A8 and A9 ARMv7 processors.  It is backward-compatible with VFPv2, except that it cannot trap floating-point exceptions. VFPv3 has 32 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such that constants can be loaded into FPU registers.
; VFPv3-D16: As above, but with only 16 64-bit FPU registers. Implemented on Cortex-R4 and R5 processors and the [[Tegra|Tegra 2]] (Cortex-A9).
; VFPv3-F16: Uncommon; it supports [[half-precision floating-point format|IEEE754-2008 half-precision (16-bit) floating point]] as a storage format.
; VFPv4 or VFPv4-D32:Implemented on Cortex-A12 and A15 ARMv7 processors, Cortex-A7 optionally has VFPv4-D32 in the case of an FPU with Neon.<ref name="VFPv4.A7">{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464f/BABDAHCE.html |title=Cortex-A7 MPCore Technical Reference Manual – 1.3 Features |publisher=ARM |access-date=11 July 2014}}</ref> VFPv4 has 32 64-bit FPU registers as standard, adds both half-precision support as a storage format and [[fused multiply–add|fused multiply-accumulate]] instructions to the features of VFPv3.
; VFPv4-D16: As above, but it has only 16 64-bit FPU registers. Implemented on Cortex-A5 and A7 processors in the case of an FPU without Neon.<ref name="VFPv4.A7"/>
; VFPv5-D16-M: Implemented on Cortex-M7 when single and double-precision floating-point core option exists.

In [[Debian]] [[Linux]] and derivatives such as [[Ubuntu]] and [[Linux Mint]], '''armhf''' ('''ARM hard float''') refers to the ARMv7 architecture including the additional VFP3-D16 floating-point hardware extension (and Thumb-2) above. Software packages and cross-compiler tools use the armhf vs. arm/armel suffixes to differentiate.<ref>{{cite web |url=https://wiki.debian.org/ArmHardFloatPort |title=ArmHardFloatPort – Debian Wiki |publisher=Wiki.debian.org |date=20 August 2012 |access-date=8 January 2014}}</ref>

==={{anchor|NEON}}{{anchor|Advanced SIMD (NEON)}}Advanced SIMD (Neon)===
The ''Advanced SIMD'' extension (also known as ''Neon'' or "MPE" Media Processing Engine) is a combined 64- and [[128-bit computing|128-bit]] SIMD instruction set that provides standardised acceleration for media and signal processing applications. Neon is included in all Cortex-A8 devices, but is optional in Cortex-A9 devices.<ref>{{cite web |url=https://www.arm.com/products/processors/cortex-a/cortex-a9.php |title=Cortex-A9 Processor |website=arm.com |access-date=21 November 2011}}</ref> Neon can execute MP3 audio decoding on CPUs running at 10&nbsp;MHz, and can run the [[GSM]] [[adaptive Multi-Rate audio codec|adaptive multi-rate]] (AMR) speech codec at 13&nbsp;MHz. It features a comprehensive instruction set, separate register files, and independent execution hardware.<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0409f/Chdceejc.html |title=About the Cortex-A9 NEON MPE |website=arm.com |access-date=21 November 2011}}</ref> Neon supports 8-, 16-, 32-, and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics and gaming processing. In Neon, the SIMD supports up to 16&nbsp;operations at the same time. The Neon hardware shares the same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support 128-bit vectors, but will execute with 64&nbsp;bits at a time,<ref name="cortex_a9"/> whereas newer Cortex-A15 devices can execute 128&nbsp;bits at a time.<ref>{{cite web |url=https://patents.google.com/patent/US20050125476A1/en |title=US20050125476A1}}</ref><ref>{{cite web |url=https://patents.google.com/patent/US20080141004A1/en |title=US20080141004A1}}</ref>

A quirk of Neon in Armv7 devices is that it flushes all [[subnormal number]]s to zero, and as a result the [[GNU Compiler Collection|GCC]] compiler will not use it unless {{code|-funsafe-math-optimizations}}, which allows losing denormals, is turned on. "Enhanced" Neon defined since Armv8 does not have this quirk, but as of {{nowrap|GCC 8.2}} the same flag is still required to enable Neon instructions.<ref>{{cite web |title=ARM Options |url=https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html |website=GNU Compiler Collection Manual |access-date=20 September 2019}}</ref> On the other hand, GCC does consider Neon safe on AArch64 for Armv8.

ProjectNe10 is ARM's first open-source project (from its inception; while they acquired an older project, now named [[Mbed TLS]]<!--the sub-project https://github.com/ARMmbed/mbed-crypto seems to have only x86 assembly-->). The Ne10 library is a set of common, useful functions written in both Neon and C (for compatibility). The library was created to allow developers to use Neon optimisations without learning Neon, but it also serves as a set of highly optimised Neon intrinsic and assembly code examples for common DSP, arithmetic, and image processing routines. The source code is available on GitHub.<ref>{{GitHub|projectNe10/Ne10|Ne10: An open optimized software library project for the ARM Architecture}}</ref>

==={{Anchor|ARM Helium technology}}ARM Helium technology===
Helium is the M-Profile Vector Extension (MVE). It adds more than 150 scalar and vector instructions.<ref>{{cite web |url=https://www.arm.com/-/media/Files/pdf/white-paper/armv8.1-m-architecture.pdf |title=Introduction to ARMv8.1-M architecture |author=Joseph Yiu |access-date=18 July 2022}}</ref>

===Security extensions===

===={{anchor|TrustZone}}TrustZone (for Cortex-A profile)====
The Security Extensions, marketed as TrustZone Technology, is in ARMv6KZ and later application profile architectures. It provides a low-cost alternative to adding another dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control. This lets the application core switch between two states, referred to as ''worlds'' (to reduce confusion with other names for capability domains), to prevent information leaking from the more trusted world to the less trusted world.<ref>{{cite web |url=https://developer.arm.com/documentation/100935/0100/The-TrustZone-hardware-architecture- |title=The TrustZone hardware architecture |publisher=[[Arm Holdings|ARM Developer]]}}</ref> This world switch is generally orthogonal to all other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device.<ref>{{cite web |url=https://genode.org/documentation/articles/trustzone |title=Genode – An Exploration of ARM TrustZone Technology |access-date=10 July 2015}}</ref>

Typically, a rich operating system is run in the less trusted world, with smaller security-specialised code in the more trusted world, aiming to reduce the [[attack surface]].  Typical applications include [[digital rights management|DRM]] functionality for controlling the use of media on ARM-based devices,<ref>{{cite press release |url=https://news.thomasnet.com/companystory/476887 |title=ARM Announces Availability of Mobile Consumer DRM Software Solutions Based on ARM TrustZone Technology |publisher=News.thomasnet.com |access-date=18 April 2009}}</ref> and preventing any unapproved use of the device.

In practice, since the specific implementation details of proprietary TrustZone implementations have not been publicly disclosed for review, it is unclear what level of assurance is provided for a given [[threat model]], but they are not immune from attack.<ref>{{cite web |url=https://bits-please.blogspot.com/2015/08/full-trustzone-exploit-for-msm8974.html |title=Bits, Please!: Full TrustZone exploit for MSM8974 |last=Laginimaineb |date=8 October 2015 |website=Bits, Please! |access-date=3 May 2016}}</ref><ref>{{cite web |url=https://www.blackhat.com/docs/us-15/materials/us-15-Shen-Attacking-Your-Trusted-Core-Exploiting-Trustzone-On-Android.pdf |title=Attacking your 'Trusted Core' Exploiting TrustZone on Android |author=Di Shen |publisher=[[Black Hat Briefings]] |access-date=3 May 2016}}</ref>

Open Virtualization<ref>{{cite web |url=http://www.openvirtualization.org |title=ARM TrustZone and ARM Hypervisor Open Source Software |publisher=Open Virtualization |access-date=14 June 2013 |archive-url=https://web.archive.org/web/20130614081110/http://openvirtualization.org/ |archive-date=14 June 2013 |url-status=dead}}</ref> is an open source implementation of the trusted world architecture for TrustZone.

[[AMD]] has licensed and incorporated TrustZone technology into its [[AMD Platform Security Processor|Secure Processor Technology]].<ref>{{cite web |title=AMD Secure Technology |url=https://www.amd.com/en-us/innovations/software-technologies/security |website=AMD |access-date=6 July 2016 |archive-url=https://web.archive.org/web/20160723094537/https://www.amd.com/en-us/innovations/software-technologies/security |archive-date=23 July 2016}}</ref> AMD's [[AMD Accelerated Processing Unit|APU]]s include a Cortex-A5 processor for handling secure processing, which is enabled in some, but not all products.<ref>{{cite news |last1=Smith |first1=Ryan |title=AMD 2013 APUs to include ARM Cortex A5 Processor for Trustzone Capabilities |url=https://www.anandtech.com/show/6007/amd-2013-apus-to-include-arm-cortexa5-processor-for-trustzone-capabilities |access-date=6 July 2016 |website=[[AnandTech]] |date=13 June 2012}}</ref><ref name="beema">{{cite news |last1=Shimpi |first1=Anand Lal |title=AMD Beema Mullins Architecture A10 micro 6700T Performance Preview |url=https://www.anandtech.com/show/7974/amd-beema-mullins-architecture-a10-micro-6700t-performance-preview |access-date=6 July 2016 |website=[[AnandTech]] |date=29 April 2014}}</ref><ref>{{cite news |last1=Walton |first1=Jarred |title=AMD Launches Mobile Kaveri APUs |url=https://www.anandtech.com/show/8119/amd-launches-mobile-kaveri-apus |access-date=6 July 2016 |website=[[AnandTech]] |date=4 June 2014}}</ref> In fact, the Cortex-A5 TrustZone core had been included in earlier AMD products, but was not enabled due to time constraints.<ref name="beema"/>

[[Samsung Knox]] uses TrustZone for purposes such as detecting modifications to the kernel, storing certificates and attestating keys.<ref>{{cite web |url=https://docs.samsungknox.com/admin/whitepaper/kpe/hardware-backed-root-of-trust.htm |title=Root of Trust |type=white paper |date=April 2016 |publisher=[[Samsung Electronics]]}}</ref>

===={{anchor|TrustZone for ARMv8-M}}TrustZone for Armv8-M (for Cortex-M profile)====
The Security Extension, marketed as TrustZone for Armv8-M Technology, was introduced in the Armv8-M architecture. While containing similar concepts to TrustZone for Armv8-A, it has a different architectural design, as world switching is performed using branch instructions instead of using exceptions.<ref>{{cite web |url=https://developer.arm.com/documentation/100690/0100/Introduction/Secure-and-Non-secure-worlds/Relationship-between-ARM-TrustZone-technology-for-ARMv8-M-and-ARM-Cortex-A-processors?lang=en |title=Relationship between ARM TrustZone technology for ARMv8-M and ARM Cortex-A processors |publisher=[[Arm Holdings|ARM Developer]]}}</ref> It also supports safe interleaved interrupt handling from either world regardless of the current security state. Together these features provide low latency calls to the secure world and responsive interrupt handling. ARM provides a reference stack of secure world code in the form of Trusted Firmware for M and [[PSA Certified]].

===No-execute page protection===
As of ARMv6, the ARM architecture supports [[NX bit|no-execute page protection]], which is referred to as ''XN'', for ''eXecute Never''.<ref>{{cite web |quote=APX and XN (execute never) bits have been added in VMSAv6 [Virtual Memory System Architecture] |url=https://www.arm.com/miscPDFs/14128.pdf |title=ARM Architecture Reference Manual |page=B4-8 |archive-url=https://web.archive.org/web/20090206061248/http://arm.com/miscPDFs/14128.pdf |archive-date=6 February 2009}}</ref>

==={{anchor|LPAE}}Large Physical Address Extension (LPAE)===
The Large Physical Address Extension (LPAE), which extends the physical address size from 32 bits to 40 bits, was added to the Armv7-A architecture in 2011.<ref>{{cite book |title=ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition |publisher=ARM Limited}}</ref>

The physical address size may be even larger in processors based on the 64-bit (Armv8-A) architecture. For example, it is 44 bits in Cortex-A75 and Cortex-A65AE.<ref>{{cite web |url=https://developer.arm.com/ip-products/processors/cortex-a/cortex-a65ae |title=Cortex-A65AE |website=ARM Developer |access-date=26 April 2019}}</ref>

==={{anchor|ARM8-R}}Armv8-R and Armv8-M===
The '''Armv8-R''' and '''Armv8-M''' architectures, announced after the Armv8-A architecture, share some features with Armv8-A. However, Armv8-M does not include any 64-bit AArch64 instructions, and Armv8-R originally did not include any AArch64 instructions; those instructions were added to [[#Armv8-R|Armv8-R]] later.

===={{Anchor|ARMv8.1-M}}Armv8.1-M====
The Armv8.1-M architecture, announced in February 2019, is an enhancement of the Armv8-M architecture. It brings new features including:
* A new vector instruction set extension. The M-Profile Vector Extension (MVE), or Helium, is for signal processing and machine learning applications.
* Additional instruction set enhancements for loops and branches (Low Overhead Branch Extension).
* Instructions for [[half-precision floating-point format|half-precision floating-point]] support.
* Instruction set enhancement for TrustZone management for Floating Point Unit (FPU).
* New memory attribute in the Memory Protection Unit (MPU).
* Enhancements in debug including Performance Monitoring Unit (PMU), Unprivileged Debug Extension, and additional debug support focus on signal processing application developments.
* Reliability, Availability and Serviceability (RAS) extension.

=={{anchor|64-bit|AArch64}}64/32-bit architecture==
{{Main|AArch64}}
[[File:ARMCortexA57A53.jpg|thumb|Armv8-A Platform with Cortex A57/A53 MPCore big.LITTLE CPU chip]]

===Armv8===

===={{anchor|ARM8-A|Armv8-A}}Armv8-A====
{{See also|Comparison of Armv8-A processors}}
Announced in October 2011,<ref name="armv8-a-announcement"/> '''Armv8-A''' (often called ARMv8 while the Armv8-R is also available) represents a fundamental change to the ARM architecture. It supports two ''execution states'': a 64-bit state named ''AArch64'' and a 32-bit state named ''AArch32''. In the AArch64 state, a new 64-bit ''A64'' instruction set is supported; in the AArch32 state, two instruction sets are supported: the original 32-bit instruction set, named ''A32'', and the 32-bit Thumb-2 instruction set, named ''T32''. AArch32 provides [[user space|user-space]] compatibility with Armv7-A. The processor state can change on an Exception level change; this allows 32-bit applications to be executed in AArch32 state under a 64-bit OS whose kernel executes in AArch64 state, and allows a 32-bit OS to run in AArch32 state under the control of a 64-bit [[hypervisor]] running in AArch64 state.<ref name="v8arch"/> ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.<ref name="cortex-a50 announce">{{cite press release |url=https://www.arm.com/about/newsroom/arm-launches-cortex-a50-series-the-worlds-most-energy-efficient-64-bit-processors.php |title=ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors |publisher=[[Arm Holdings]] |access-date=31 October 2012}}</ref> Apple was the first to release an Armv8-A compatible core in a consumer product  ([[Apple A7]] in [[iPhone 5S]]). [[AppliedMicro]], using an [[FPGA]], was the first to demo Armv8-A.<ref name="AppliedMicro-First 64-bit ARM v8 Core">{{cite press release |url=https://www.businesswire.com/news/home/20111027006673/en/AppliedMicro-Showcases-World's-64-bit-ARM-v8-Core |title=AppliedMicro Showcases World's First 64-bit ARM v8 Core |publisher=AppliedMicro |date=28 October 2011 |access-date=11 February 2014}}</ref> The first Armv8-A [[system on a chip|SoC]] from [[Samsung Electronics|Samsung]] is the Exynos 5433 used in the [[Samsung Galaxy Note 4|Galaxy Note 4]], which features two clusters of four Cortex-A57 and Cortex-A53 cores in a [[ARM big.LITTLE|big.LITTLE]] configuration; but it will run only in AArch32 mode.<ref>{{cite web |title=Samsung's Exynos 5433 is an A57/A53 ARM SoC |website=[[AnandTech]] |url=https://www.anandtech.com/show/8537/samsungs-exynos-5433-is-an-a57a53-arm-soc |access-date=17 September 2014}}</ref>

To both AArch32 and AArch64, Armv8-A makes VFPv3/v4 and advanced SIMD (Neon) standard. It also adds cryptography instructions supporting [[Advanced Encryption Standard|AES]], [[SHA-1]]/[[SHA-256]] and [[finite field arithmetic]].<ref>{{cite web |title=ARM Cortex-A53 MPCore Processor Technical Reference Manual: Cryptography Extension |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500e/CJHDEBAF.html |publisher=ARM |access-date=11 September 2016}}</ref> AArch64 was introduced in Armv8-A and its subsequent revision.  AArch64 is not included in the 32-bit Armv8-R and Armv8-M architectures.

An ARMv8-A processor can support one or both of AArch32 and AArch64; it may support AArch32 and AArch64 at lower Exception levels and only AArch64 at higher Exception levels.<ref name="Execution-state-and-Exception-levels">{{cite web|url=https://developer.arm.com/documentation/102412/0103/Execution-and-Security-states/Impact-of-implemented-Exception-levels|title=Impact of implemented Exception levels|work=Learn the architecture - AArch64 Exception Model|publisher=Arm}}</ref> For example, the ARM Cortex-A32 supports only AArch32,<ref>{{cite web|url=https://developer.arm.com/Processors/Cortex-A32|title=Cortex-A32|website=Arm Developer}}</ref> the [[ARM Cortex-A34]] supports only AArch64,<ref>{{cite web|url=https://developer.arm.com/Processors/Cortex-A34|title=Cortex-A34|website=Arm Developer}}</ref> and the [[ARM Cortex-A72]] supports both AArch64 and AArch32.<ref>{{cite web|url=https://developer.arm.com/Processors/Cortex-A72|title=Cortex-A72|website=Arm Developer}}</ref> An ARMv9-A processor must support AArch64 at all Exception levels, and may support AArch32 at EL0.<ref name="Execution-state-and-Exception-levels" />

===={{anchor|ARM8-R}}Armv8-R====
Optional AArch64 support was added to the Armv8-R profile, with the first ARM core implementing it being the Cortex-R82.<ref>{{cite news |last=Frumusanu |first=Andrei |date=September 3, 2020 |url=https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor |title=ARM Announced Cortex-R82: First 64-bit Real Time Processor |website=[[AnandTech]]}}</ref> It adds the A64 instruction set.

===Armv9===

===={{anchor|ARM9-A|Armv9-A}}Armv9-A====
Announced in March 2021, the updated architecture places a focus on secure execution and [[Compartmentalization (engineering)|compartmentalisation]].<ref>{{cite news |last=Frumusanu |first=Andrei |date=March 30, 2021 |url=https://www.anandtech.com/show/16584/arm-announces-armv9-architecture |title=Arm Announces Armv9 Architecture: SVE2, Security, and the Next Decade |website=[[AnandTech]]}}</ref><ref>{{cite press release |last=Harrod |first=Alex |date=March 30, 2021 |url=https://newsroom.arm.com/news/arms-solution-to-the-future-needs-of-ai-security-and-specialized-computing-is-v9 |title=Arm's Solution to the Future Needs of AI, Security and Specialized Computing is v9 |publisher=[[Arm Holdings]]}}</ref> The first ARMv9-A processors were released later that year, including the Cortex-A510, Cortex-A710 and Cortex-X2.

==Arm SystemReady==
Arm SystemReady is a compliance program that helps ensure the interoperability of an operating system on Arm-based hardware from datacenter servers to industrial edge and IoT devices. The key building blocks of the program are the specifications for minimum hardware and firmware requirements that the operating systems and hypervisors can rely upon. These specifications are:<ref>{{cite web|url=https://www.arm.com/architecture/system-architectures/systemready-compliance-program|title=SystemReady Compliance Program|website=Arm}}</ref>

* Base System Architecture (BSA)<ref>{{cite web|url=https://developer.arm.com/documentation/den0094/latest|title=Arm Base System Architecture|website=Arm}}</ref> and the market segment specific supplements (e.g., Server BSA supplement)<ref>{{cite web|url=https://developer.arm.com/documentation/den0029/latest|title=Arm Server Base System Architecture|website=Arm}}</ref>
* Base Boot Requirements (BBR)<ref>{{cite web|url=https://developer.arm.com/documentation/den0044/latest|title=Arm Base Boot Requirements|website=Arm}}</ref> and Base Boot Security Requirements (BBSR)<ref>{{cite web|url=https://developer.arm.com/documentation/den0107/latest|title=Base Boot Security Requirements|website=Arm}}</ref>

These specifications are co-developed by [[Arm Holdings|Arm]] and its partners in the System Architecture Advisory Committee (SystemArchAC).

Architecture Compliance Suite (ACS) is the test tools that help to check the compliance of these specifications. The Arm SystemReady Requirements Specification documents the requirements of the certifications.<ref>{{cite web|url=https://developer.arm.com/documentation/den0109/latest|title=Arm SystemReady Requirements Specification|website=Arm}}</ref>

This program was introduced by [[Arm Holdings|Arm]] in 2020 at the first [[ARM DevSummit|DevSummit]] event. Its predecessor Arm ServerReady was introduced in 2018 at the Arm TechCon event. This program currently includes two bands:

* SystemReady Band: this band focuses on  operating system interoperability for Advanced Configuration and Power Interface [[ACPI]] environments, where generic operating systems can be installed on either new or old hardware without modification. This band is relevant for systems using [[Microsoft Windows|Windows]], [[Linux]], [[VMware]], and [[Berkeley Software Distribution|BSD]] environments.<ref>{{cite web|url=https://www.arm.com/architecture/system-architectures/systemready-compliance-program/systemready-band|title=Arm SystemReady Band|website=Arm}}</ref>
* SystemReady Devicetree Band: this band optimizes install and boot for embedded systems where [[device tree|devicetree]] is the preferred method of describing hardware, with a focus on forward compatibility. This applies to [[Linux]] distributions and [[Berkeley Software Distribution|BSD]] environments specifically.<ref>{{cite web|url=https://www.arm.com/architecture/system-architectures/systemready-compliance-program/systemready-devicetree-band|title=Arm SystemReady Devicetree Band|website=Arm}}</ref>

==PSA Certified==
[[PSA Certified]], formerly named Platform Security Architecture, is an architecture-agnostic security framework and evaluation scheme. It is intended to help secure [[Internet of things]] (IoT) devices built on system-on-a-chip (SoC) processors.<ref>{{cite web |last1=Osborne |first1=Charlie |title=ARM announces PSA security architecture for IoT devices |url=https://www.zdnet.com/article/arm-announces-security-architecture-for-iot-devices/ |publisher=ZDNet}}</ref> It was introduced to increase security where a full [[trusted execution environment]] is too large or complex.<ref name="electronicdesign"/>

The architecture was introduced by [[Arm Holdings|Arm]] in 2017 at the annual [[ARM DevSummit|TechCon]] event.<ref name="electronicdesign">{{cite web |last1=Wong |first1=William |title=ARM's Platform Security Architecture Targets Cortex-M |url=https://www.electronicdesign.com/industrial-automation/arm-s-platform-security-architecture-targets-cortex-m |website=Electronic Design |date=Oct 25, 2017 |url-status=live |archive-url=https://web.archive.org/web/20190508142933/https://www.electronicdesign.com/industrial-automation/arm-s-platform-security-architecture-targets-cortex-m |archive-date= May 8, 2019 }}</ref><ref>{{cite web |last1=Hoffenberg |first1=Steve |title=ARM: Security Isn't Just a Technological Imperative, It's a Social Responsibility |url=https://www.vdcresearch.com/News-events/iot-blog/ARM-Security-Isnt-Just-a-Technological-Imperative-Its-a-Social-Responsibility.html |website=VDC Research |date=2017-10-31 |url-status=live |archive-url=https://web.archive.org/web/20230928112955/https://www.vdcresearch.com/News-events/iot-blog/Arm-Security-Isnt-Just-a-Technological-Imperative-Its-a-Social-Responsibility.html |archive-date= Sep 28, 2023 }}</ref> Although the scheme is architecture agnostic, it was first implemented on Arm Cortex-M processor cores intended for microcontroller use. PSA Certified includes freely available threat models and security analyses that demonstrate the process for deciding on security features in common IoT products.<ref>{{cite web |last1=Armasu |first1=Lucian |title=ARM Reveals More Details About Its IoT Platform Security Architecture |url=https://www.tomshardware.com/news/arm-iot-platform-security-architecture,36564.html |date=22 February 2018 |website=Tom's Hardware}}</ref> It also provides freely downloadable application programming interface (API) packages, architectural specifications, open-source firmware implementations, and related test suites.<ref>{{cite web |last1=Williams |first1=Chris |title=ARM PSA IoT API? BRB... Toolbox of tech to secure net-connected kit opens up some more |url=https://www.theregister.co.uk/2018/10/17/arm_psa_iot/ |website=The Register}}</ref>

Following the development of the architecture security framework in 2017, the [[PSA Certified]] assurance scheme launched two years later at Embedded World in 2019.<ref name=electronicsweekly>{{cite web |last1=Hayes |first1=Caroline |title=Embedded World: Arm introduces fourth security element to PSA |url=https://www.electronicsweekly.com/market-sectors/internet-of-things/arm-introduces-fourth-security-element-psa-2019-02/ |publisher=[[Electronics Weekly]] |date=February 25, 2019}}</ref> PSA Certified offers a multi-level security evaluation scheme for chip vendors, OS providers and IoT device makers.<ref>{{cite web |url=https://www.psacertified.org/ |title=PSA Certified: building trust in IoT |website=PSA Certified}}</ref> The Embedded World presentation introduced chip vendors to Level 1 Certification. A draft of Level 2 protection was presented at the same time.<ref name=eetimes>{{cite web |title=PSA Certified–building trust, building value |url=https://www.eetimes.com/psa-certified-building-trust-building-value/ |publisher=[[EE Times]] |date=March 4, 2019}}</ref> Level 2 certification became a usable standard in February 2020.<ref>{{cite web |title=The $6trn importance of security standards and regulation in the IoT era |url=https://www.iot-now.com/2020/03/16/101805-6trn-importance-security-standards-regulation-iot-era/ |publisher=IoT Now |date=March 16, 2020}}</ref>

The certification was created by PSA Joint Stakeholders to enable a security-by-design approach for a diverse set of IoT products. PSA Certified specifications are implementation and architecture agnostic, as a result they can be applied to any chip, software or device.<ref name=forbes>{{cite web |last1=McGregor |first1=Jim |title=Arm Introduces Security Certification Testing For IoT |url=https://www.forbes.com/sites/tiriasresearch/2019/03/04/arm-introduces-security-certification-testing-for-iot/#7c4aa91d38eb |work=[[Forbes]] |date=March 4, 2019}}</ref><ref name=eetimes/> The certification also removes industry fragmentation for [[Internet of Things|IoT product]] manufacturers and developers.<ref>{{cite web |last1=Speed |first1=Richard |title=Azure IoT heads spaceward to maintain connectivity at the edge, courtesy of Inmarsat |url=https://www.theregister.co.uk/2019/02/25/azure_iot_takes_to_space/ |publisher=[[TheRegister]] |date=February 26, 2019}}</ref>

==Operating system support==

===32-bit operating systems===

====Historical operating systems====
The first 32-bit ARM-based personal computer, the [[Acorn Archimedes]], was originally intended to run an ambitious operating system called [[ARX (operating system)|ARX]]. The machines shipped with [[RISC OS]], which was also used on later ARM-based systems from Acorn and other vendors. Some early Acorn machines were also able to run a [[Unix]] port called [[RISC iX]]. (Neither is to be confused with [[MIPS RISC/os|RISC/os]], a contemporary Unix variant for the MIPS architecture.)

====Embedded operating systems====
The 32-bit ARM architecture is supported by a large number of [[embedded operating system|embedded]] and [[real-time operating system]]s, including:

{{Div col}}
* [[A2 (operating system)|A2]]
* [[Android (operating system)|Android]]
* [[ChibiOS/RT]]
* [[Deos]]
* [[DRYOS]]
* [[eCos]]
* [[embOS]]
* [[FreeBSD]]
* [[FreeRTOS]]
* [[Integrity (operating system)|INTEGRITY]]
* [[Linux kernel|Linux]]
* [[Micro-Controller Operating Systems]]
* [[Mbed]]
* [[MINIX 3]]
* [[MQX]]
* [[Nucleus RTOS|Nucleus PLUS]]
* [[NuttX]]
* [[L4 microkernel family|OKL4]]
* [[Operating System Embedded]] (OSE)
* [[OS-9]]<ref>{{cite web |url=http://www.microware.com/index.php/specifications |title=OS-9 Specifications |publisher=[[Microware]]}}</ref>
* Pharos<ref name="Pharos">{{cite web |url=https://sourceforge.net/projects/rtospharos/ |title=Pharos |website=SourceForge |access-date=24 May 2018}}</ref>
* [[Plan 9 from Bell Labs|Plan 9]]
* [[PikeOS]]<ref>{{cite web |url=https://www.arm.com/community/partners/display_product/rw/ProductId/4201/ |title=PikeOS Safe and Secure Virtualization |access-date=10 July 2013}}</ref>
* [[QNX]]
* [[RIOT (operating system)|RIOT]]
* [[RTEMS]]
* [[RTXC Quadros]]
* SCIOPTA<ref name="sciopta">{{cite web |url=http://www.sciopta.com/cpu/cpu.html |title=Safety Certified Real-Time Operating Systems – Supported CPUs}}</ref>
* [[ThreadX]]
* [[TizenRT]]
* [[T-Kernel]]
* [[VxWorks]]
* [[Windows CE|Windows Embedded Compact]]
* [[Windows 10 IoT Core]]
* [[Zephyr (operating system)|Zephyr]]
{{Div col end}}

====Mobile device operating systems====
As of March 2024, the 32-bit ARM architecture used to be the primary hardware environment for most mobile device operating systems such as the following but many of these platforms such as Android and Apple iOS have evolved to the 64-bit ARM architecture:

{{Div col}}
* [[Android (operating system)|Android]]<!--going with Android here as alphabetical and most popular, but not chronological..: -->
* [[ChromeOS]]
* [[Mobian]]
* [[Sailfish OS|Sailfish]]
* [[postmarketOS]]
* [[Tizen]]
* [[Ubuntu Touch]]
* [[webOS]]
{{Div col end}}

Formerly, but now discontinued:
{{Div col}}
* [[Bada (operating system)|Bada]]
* [[BlackBerry OS]]/[[BlackBerry 10]]
* [[Firefox OS]]
* [[MeeGo]]
* [[Newton OS]]
* [[iOS]] 10 and earlier
* [[Symbian]]
* [[Windows 10 Mobile]]
* [[Windows RT]]
* [[Windows Phone]]
* [[Windows Mobile]]
{{Div col end}}

====Desktop and server operating systems====
The 32-bit ARM architecture is supported by RISC OS and by multiple [[Unix-like]] operating systems including:
* [[FreeBSD]]
* [[NetBSD]]
* [[OpenBSD]]
* [[OpenSolaris]]<ref>{{cite web |title=ARM Platform Port |url=http://hub.opensolaris.org/bin/view/Project+osarm/WebHome |publisher=opensolaris.org |access-date=29 December 2012 |url-status=dead |archive-url=https://web.archive.org/web/20121202082808/http://hub.opensolaris.org/bin/view/Project%2Bosarm/WebHome |archive-date=2 December 2012}}</ref>
* several [[Linux]] distributions, such as:
** [[Debian]]
** [[Armbian]]
** [[Gentoo Linux|Gentoo]]
** [[Ubuntu]]
** [[Raspberry Pi OS]] (formerly Raspbian)
** [[Slackware ARM|Slackware]]

===64-bit operating systems===

====Embedded operating systems====
* [[Integrity (operating system)|INTEGRITY]]<ref>{{cite web |url=https://www.ghs.com/news/20160105_CES_CTS_INTEGRITY-64-bit-virtual.html |title=Green Hills Software's INTEGRITY-based Multivisor Delivers Embedded Industry's First 64-bit Secure Virtualization Solution |website=ghs.com |access-date=14 March 2018}}</ref>
* [[Operating System Embedded|OSE]]<ref>{{cite web |url=https://www.enea.com/products/operating-systems/enea-ose/ |title=Enea OSE real-time operating system for 5G and LTE-A {{!}} Enea |website=enea.com |access-date=17 April 2018 |archive-date=1 January 2019 |archive-url=https://web.archive.org/web/20190101024154/https://www.enea.com/products/operating-systems/enea-ose/ |url-status=dead }}</ref>
* SCIOPTA<ref name="sciopta"/>
* [[L4 microkernel family#High assurance: seL4|seL4]]<ref>{{cite web |url=https://docs.sel4.systems/Hardware/ |title=Supported Platforms |website=docs.sel4.systems |access-date=23 November 2018}}</ref>
* Pharos<ref name="Pharos"/>
* [[FreeRTOS]]
* [[QNX]]<ref>{{cite web |url=https://blackberry.qnx.com/en/sdp7 |title=QNX Software Development Platform (SDP 7.0) {{!}} BlackBerry QNX |website=blackberry.qnx.com |access-date=27 July 2020}}</ref>
* [[VxWorks]]<ref>{{cite press release |url=https://windriver.com/news/press/news-8881 |title=Wind River Releases 64-Bit VxWorks RTOS |date=28 February 2011 |publisher=[[Wind River Systems]] |access-date=24 October 2023}}</ref>
* [[Zephyr (operating system)|Zephyr]]

====Mobile device operating systems====
* [[Android (operating system)|Android]] supports Armv8-A in [[Android Lollipop]] (5.0) and later.
* [[iOS]] supports Armv8-A in [[iOS 7]] and later on 64-bit [[Apple silicon|Apple SoC]]s. [[iOS 11]] and later, and [[iPadOS]], only support 64-bit ARM processors and applications.
* [[HarmonyOS NEXT]] was developed specifically for ARM processors, starting from its launch in 2024.
* [[Mobian]]
* [[PostmarketOS]]
* [[Arch Linux ARM]]
* [[Manjaro]]<ref>{{cite web |url=https://wiki.manjaro.org/index.php/Manjaro-ARM |title=Manjaro-ARM |website=Manjaro wiki |date=20 June 2022}}</ref>

====Desktop and server operating systems====
* Support for Armv8-A was merged into the [[Linux kernel]] version 3.7 in late 2012.<ref>{{cite mailing list |url=https://lkml.org/lkml/2012/10/1/317 |title=Re: &#91;GIT PULL&#93; arm64: Linux kernel port |date=1 October 2012 |author=Linus Torvalds |mailing-list=Linux kernel mailing list |access-date=2 May 2019}}</ref> Armv8-A is supported by a number of [[Linux distribution]]s, such as:
** [[Debian]]<ref>{{cite web |url=https://www.phoronix.com/scan.php?page=news_item&px=MTMxMzU |title=64-bit ARM Version of Ubuntu/Debian Is Booting |last=Larabel |first=Michael |author-link=Michael Larabel |publisher=[[Phoronix]] |date=27 February 2013 |access-date=17 August 2014}}</ref><ref>{{cite web |url=https://www.debian.org/News/weekly/2014/12/#debianportsarms |title=Debian Project News – August 14th, 2014 |publisher=[[Debian]] |date=14 August 2014 |access-date=17 August 2014}}</ref>
** [[Armbian]]
** [[Alpine Linux]]
** [[Ubuntu]]<ref>{{cite web |url=https://ubuntu.com/download/server/arm |title=Ubuntu Server for ARM |website=ubuntu.com}}</ref>
** [[Fedora Linux|Fedora]]<ref>{{cite web |url=https://fedoraproject.org/wiki/Architectures/AArch64 |title=Architectures/AArch64 |access-date=16 January 2015}}</ref>
** [[NixOS]]<ref>{{cite web |url=https://wiki.nixos.org/wiki/NixOS_on_ARM |title=NixOS on ARM |access-date=21 March 2025}}</ref>
** [[openSUSE]]<ref>{{cite web |url=https://en.opensuse.org/Portal:ARM/AArch64 |title=Portal:ARM/AArch64 |access-date=16 January 2015}}</ref>
** [[SUSE Linux Enterprise]]<ref>{{cite web |url=https://www.suse.com/releasenotes/x86_64/SUSE-SLES/12-SP2/ |title=SUSE Linux Enterprise 12 SP2 Release Notes |access-date=11 November 2016}}</ref>
** [[Red Hat Enterprise Linux|RHEL]]<ref>{{cite web |url=https://www.redhat.com/en/blog/red-hat-introduces-arm-server-support-red-hat-enterprise-linux |title=Red Hat introduces ARM server support for Red Hat Enterprise Linux |website=redhat.com |access-date=18 January 2019}}</ref>
** [[Raspberry Pi OS]] (formerly Raspbian)
* Support for Armv8-A was merged into [[FreeBSD]] in late 2014.<ref>{{cite web |url=http://freebsdfoundation.blogspot.com/2014/11/64-bit-arm-architecture-project-update.html |title=64-bit ARM architecture project update |publisher=The FreeBSD Foundation |date=24 November 2014}}</ref>
* [[OpenBSD]] has Armv8 support {{as of|2023|lc=true}}.<ref>{{cite web |url=https://www.openbsd.org/arm64.html |title=OpenBSD/arm64 |access-date=25 September 2023}}</ref>
* [[NetBSD]] has Armv8 support since early 2018.<ref>{{cite web |url=https://mail-index.netbsd.org/port-arm/2018/04/01/msg004702.html |title=NetBSD/arm64 |access-date=5 August 2018}}</ref>
* [[Windows]] - [[Windows 10]] runs 32-bit "[[x86]] and 32-bit ARM applications",<ref>{{cite news |url=https://arstechnica.com/gadgets/2017/12/hp-asus-announce-first-windows-10-arm-pcs-20-hour-battery-life-gigabit-lte/ |title=HP, Asus announce first Windows 10 ARM PCs: 20-hour battery life, gigabit LTE |quote=This new version of Windows 10 is Microsoft's first 64-bit ARM operating system. It'll run x86 and 32-bit ARM applications from the Store, and in due course, 64-bit ARM applications. However, Microsoft hasn't yet finalised its 64-bit ARM SDK. Many pieces are in place (there's a 64-bit ARM compiler, for example), but the company isn't yet taking 64-bit ARM applications submitted to the Store, and there aren't any 64-bit ARM desktop applications either. |work=Ars Technica |access-date=22 January 2018}}</ref> as well as native ARM64 desktop apps;<ref>{{cite web |url=https://mspoweruser.com/windows-arm64-gets-first-compiled-apps/ |title=Windows 10 on ARM64 gets its first compiled apps |website=MSPoweruser |first=Mehedi |last=Hassan |date=10 December 2016}}</ref><ref>{{cite web |url=https://www.engadget.com/2018-06-01-vlc-one-of-first-arm64-windows-apps.html |title=VLC becomes one of first ARM64 Windows apps |website=Engadget |first1=Katrina |last1=Filippidis |date=1 June 2018 }}</ref> [[Windows 11]] runs native ARM64 apps and can also run x86 and x86-64 apps via emulation. Support for 64-bit ARM apps in the [[Microsoft Store]] has been available since November 2018.<ref>{{cite web |url=https://blogs.windows.com/windowsdeveloper/2018/11/15/official-support-for-windows-10-on-arm-development/ |title=Official support for Windows 10 on ARM development |website=Windows Blogs |department=Windows Developer |date=15 November 2018 |last1=Sweetgall |first1=Marc |publisher=[[Microsoft]] |access-date=17 December 2019}}</ref><!--Possibly Windows 10 IoT belongs here, but may have same "weak" support as Windows 10 Mobile. Do not add here without consensus/sure. See [[Talk:Windows 10 Mobile/Archive 2#No 64-bit ["ARMv8" support as implied in infobox?]: "Windows Mobile 10 without aarch64 support?"
]]-->
* [[macOS]] has ARM support since late 2020; the first release to support ARM is [[macOS Big Sur]].<ref>{{cite news |last=Gartenberg |first=Chaim |date=November 12, 2020 |title=macOS Big Sur is now available to download |work=[[The Verge]] |url=https://www.theverge.com/2020/11/12/21562585/macos-11-big-sur-apple-mac-download-available-now |access-date=November 13, 2020}}</ref> Rosetta 2 adds support for [[x86-64]] applications but not virtualization of x86-64 computer platforms.<ref>{{cite news |last=Clover |first=Juli |date=June 23, 2020 |title=Rosetta Won't Support x86 Virtualization Apps Running Windows |work=[[MacRumors]] |url=https://www.macrumors.com/2020/06/23/rosetta-wont-support-x86-virtualization-windows/ |access-date=November 13, 2020}}</ref>

===Porting to 32- or 64-bit ARM operating systems===
Windows applications recompiled for ARM and linked with Winelib, from the [[Wine (software)|Wine]] project, can run on 32-bit or 64-bit ARM in Linux, FreeBSD, or other compatible operating systems.<ref>{{cite web |url=https://wiki.winehq.org/ARM |title=ARM – The Official Wine Wiki |access-date=10 July 2015}}</ref><ref>{{cite web |url=https://wiki.winehq.org/ARM64 |title=ARM64 – The Official Wine Wiki |access-date=10 July 2015}}</ref> x86 binaries, e.g. when not specially compiled for ARM, have been demonstrated on ARM using [[QEMU]] with Wine (on Linux and more<!--Android-->),{{citation needed|date=February 2018}} but do not work at full speed or same capability as with Winelib.

==Notes==
{{Notelist}}

==See also==
{{Portal|Electronics}}
* [[Amber (processor)|Amber]] – an open-source ARM-compatible processor core
* [[AMULET (processor)|AMULET]] – an asynchronous implementation of the ARM architecture
* [[Apple silicon]]
* [[ARM Accredited Engineer]] – certification program
* [[ARM big.LITTLE]] – ARM's heterogeneous computing architecture
** [[DynamIQ]]
* [[ARMulator]] – an instruction set simulator
* [[Comparison of ARM processors]]
* [[Meltdown (security vulnerability)]]<ref>{{cite web |url=https://developer.arm.com/support/arm-security-updates |title=ARM Security Updates |website=ARM Developer |access-date=24 May 2018}}</ref>
* [[Reduced instruction set computer]] (RISC)
* [[RISC-V]]
* [[Spectre (security vulnerability)]]
* [[Unicore]] – a 32-register architecture based heavily on a 32-bit ARM

==References==

===Citations===
{{Reflist}}

===Bibliography===
* {{cite conference |last=Evans |first=Matt |date=27 December 2019 |conference=Schedule 36 Chaos Communication Congress |url=https://www.youtube.com/watch?v=Hf67JYkUCHQ |archive-url=https://ghostarchive.org/varchive/youtube/20211211/Hf67JYkUCHQ |archive-date=2021-12-11 |url-status=live |title=The Ultimate Acorn Archimedes talk |via=media.ccc.de |website=YouTube }}{{cbignore}}

==Further reading==
{{See also|ARM Cortex-M#Further reading|l1=List of books about ARM Cortex-M}}

==External links==
{{Commons category}}
* {{Official website}}, ARM Ltd.

===Architecture manuals===
* {{cite web |url=https://documentation-service.arm.com/static/5f8dacc8f86e16515cdb865a |title=ARM Architecture Reference Manual |author=ARM Limited |date=1996–2005 |website=documentation-service.arm.com |access-date=16 July 2021}} - covers ARMv4, ARMv4T, ARMv5T, (ARMv5TExP), ARMv5TE, ARMv5TEJ, and ARMv6
* {{cite web |url=https://developer.arm.com/documentation/ddi0419/latest |title=Armv6-M Architecture Reference Manual |author=ARM Limited |date=2007–2018 |website=ARM documentation |access-date=17 July 2021}}
* {{cite web |url=https://developer.arm.com/documentation/ddi0406/latest |title=ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition |author=ARM Limited |date=2007–2018 |website=ARM documentation |access-date=17 July 2021}}
* {{cite web |url=https://developer.arm.com/documentation/ddi0403/latest |title=ARMv7-M Architecture Reference Manual |author=ARM Limited |date=2006–2021 |website=ARM documentation |access-date=24 August 2022}}
* {{cite web |url=https://developer.arm.com/documentation/ddi0487/latest |title=Arm Architecture Reference Manual for A-profile architecture |author=ARM Limited |date=2013–2022 |website=ARM documentation |access-date=24 August 2022}}
* {{cite web |url=https://developer.arm.com/documentation/ddi0568/latest/ |title=ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R AArch32 architecture profile |author=ARM Limited |date=2016–2020 |website=ARM documentation |access-date=17 July 2021}}
* {{cite web |url=https://developer.arm.com/documentation/ddi0600/latest/ |title=Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile |author=ARM Limited |date=2020–2022 |website=ARM documentation |access-date=24 August 2022}}
* {{cite web |url=https://developer.arm.com/documentation/ddi0553/latest |title=Armv8-M Architecture Reference Manual |author=ARM Limited |date=2015–2022 |website=ARM documentation |access-date=24 August 2022}}
* {{cite web |url=https://developer.arm.com/documentation/ddi0602/latest |title=Arm Armv9-A A64 Instruction Set Architecture |author=ARM Limited |date=2021 |website=ARM documentation |access-date=17 July 2021}}
* {{cite web |url=http://www.futurechips.org/understanding-chips/arm-virtualization-extensions-introduction-part-1.html |title=ARM Virtualization Extensions |archive-url=https://web.archive.org/web/20131218195900/http://www.futurechips.org/understanding-chips/arm-virtualization-extensions-introduction-part-1.html |archive-date=18 December 2013}}

===Quick-reference cards===

====Instructions====
* [https://developer.arm.com/documentation/qrc0006/latest/ Thumb] {{webarchive |url=https://web.archive.org/web/20200620235725/http://infocenter.arm.com/help/topic/com.arm.doc.qrc0006e/QRC0006_UAL16.pdf |date=20 June 2020}}
* [https://developer.arm.com/documentation/qrc0001/latest/ ARM and Thumb-2] {{webarchive |url=https://web.archive.org/web/20200620113032/http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf |date=20 June 2020}}
* [https://developer.arm.com/documentation/qrc0007/latest/ Vector Floating Point] {{webarchive |url=https://web.archive.org/web/20200619101951/http://infocenter.arm.com/help/topic/com.arm.doc.qrc0007e/QRC0007_VFP.pdf |date=19 June 2020}}

====Opcodes====

* [https://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf Thumb] {{webarchive |url=https://web.archive.org/web/20220730025833/https://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf |date=30 July 2022 |url2=https://archive.today/20220822110824/https://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf |date2=22 August 2022}}
* [https://re-eject.gbadev.org/files/armref.pdf ARM] {{webarchive |url=https://web.archive.org/web/20220607075242/https://re-eject.gbadev.org/files/armref.pdf |date=7 June 2022 |url2=https://archive.today/20220822111018/https://re-eject.gbadev.org/files/armref.pdf |date2=22 August 2022}}
* [https://re-eject.gbadev.org/files/GasARMRef.pdf GNU Assembler Directives] {{webarchive |url=https://web.archive.org/web/20220430145554/https://re-eject.gbadev.org/files/GasARMRef.pdf |date=30 April 2022 |url2=https://archive.today/20220822105338/https://re-eject.gbadev.org/files/GasARMRef.pdf |date2=22 August 2022}}

{{Application ARM-based chips}}
{{Embedded ARM-based chips}}
{{Classic ARM-based chips}}
{{RISC architectures}}
{{Microcontrollers}}
{{Processor technologies}}
{{Authority control}}

[[Category:ARM architecture| ]]
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