Editing Application-specific integrated circuit

{{Short description|Integrated circuit customized for a specific task}}
{{Redirect|ASIC}}
{{Use dmy dates|date=July 2020}}
{{Use American English|date=December 2018}}
[[File:SSDTR-ASIC technology.jpg|thumb|A tray of application-specific integrated circuit (ASIC) chips]]
[[File:Network traffic processing ASIC inside an Ethernet switch.jpg|thumb|A packet processing ASIC inside an Ethernet switch]]
An '''application-specific integrated circuit''' ('''ASIC''' {{IPAc-en|ˈ|eɪ|s|ɪ|k}}) is an [[integrated circuit]] (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a [[digital voice recorder]] or a high-efficiency [[video codec]].<ref>{{Cite book |last=Golshan |first=Khosrow |title=Physical Design Essentials: An ASIC Design Implementation Perspective |date=2007 |publisher=Springer |isbn=978-0-387-36642-5 |location=Boston, MA}}</ref> [[#Application-specific standard product|Application-specific standard product]] chips are intermediate between ASICs and industry standard integrated circuits like the [[7400 series]] or the [[4000 series]].<ref name=":0">{{Cite book |last=Barr |first=Keith |url=https://archive.org/details/asicdesigninsili0000barr |title=ASIC Design in the Silicon Sandbox: A Complete Guide to Building Mixed-signal Integrated Circuits |date=2007 |publisher=McGraw-Hill |isbn=978-0-07-148161-8 |location=New York |oclc=76935560 |url-access=registration}}</ref> ASIC chips are typically [[semiconductor device fabrication|fabricated]] using [[metal–oxide–semiconductor]] (MOS) technology, as [[MOS integrated circuit]] chips.<ref name="computerhistory1967"/>

As feature sizes have shrunk and [[Electronic design automation|chip design tools]] improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 [[logic gate]]s to over 100 million. Modern ASICs often include entire [[Central processing unit|microprocessors]], [[memory]] blocks including [[Read-only memory|ROM]], [[Random-access memory|RAM]], [[EEPROM]], [[flash memory]] and other large building blocks. Such an ASIC is often termed a SoC ([[system-on-chip]]). Designers of digital ASICs often use a [[hardware description language]] (HDL), such as [[Verilog]] or [[VHDL]], to describe the functionality of ASICs.<ref name=":0" />

[[Field-programmable gate array]]s (FPGA) are the modern-day technology improvement on [[breadboard]]s, meaning that they are not made to be application-specific as opposed to ASICs. Programmable [[Logic block|logic blocks]] and programmable interconnects allow the same FPGA to be used in many different applications. For smaller designs or lower production volumes, FPGAs may be more cost-effective than an ASIC design, even in production. The [[non-recurring engineering]] (NRE) cost of an ASIC can run into the millions of dollars. Therefore, device manufacturers typically prefer FPGAs [[FPGA prototyping|for prototyping]] and devices with low production volume and ASICs for [[mass production|very large production volumes]] where NRE costs can be [[Amortized cost|amortized]] across many devices.<ref>{{cite web|url=https://www.eetimes.com/fpgas-vs-asics/|title=FPGA's vs. ASIC's|date=13 September 2004|website=[[EE Times]]|first=Jeff|last=Kriegbaum}}</ref>

== History ==
Early ASICs used [[gate array]] technology. By 1967, [[Ferranti]] and Interdesign were manufacturing early [[bipolar transistor|bipolar]] gate arrays. In 1967, [[Fairchild Semiconductor]] introduced the Micromatrix family of bipolar [[diode–transistor logic]] (DTL) and [[transistor–transistor logic]] (TTL) arrays.<ref name="computerhistory1967">{{cite web |title=1967: Application Specific Integrated Circuits employ Computer-Aided Design |url=https://www.computerhistory.org/siliconengine/application-specific-integrated-circuits-employ-computer-aided-design/ |website=The Silicon Engine |publisher=[[Computer History Museum]] |access-date=9 November 2019}}</ref>

[[Complementary metal–oxide–semiconductor]] (CMOS) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp,<ref>{{Cite book|url=http://www.computerhistory.org/collections/catalog/102706880|title=Lipp, Bob oral history|website=[[Computer History Museum]]|date=14 February 2017|publisher=Computer History Museum|access-date=2018-01-28}}</ref><ref>{{Cite web|url=http://www.computerhistory.org/siliconengine/people/|title=People|website=The Silicon Engine|publisher=Computer History Museum|access-date=2018-01-28}}</ref> in 1974 for International Microcircuits, Inc. (IMI).<ref name="computerhistory1967"/>

[[Metal–oxide–semiconductor]] (MOS) [[standard-cell]] technology was introduced by Fairchild and [[Motorola]], under the trade names Micromosaic and Polycell, in the 1970s. This technology was later successfully commercialized by [[VLSI Technology]] (founded 1979) and [[LSI Logic]] (1981).<ref name="computerhistory1967"/>

A successful commercial application of [[gate array]] circuitry was found in the low-end 8-bit [[ZX81]] and [[ZX Spectrum]] [[personal computer]]s, introduced in 1981 and 1982. These were used by [[Sinclair Research]] (UK) essentially as a low-cost [[Input/output|I/O]] solution aimed at handling the [[Computer graphics|computer's graphics]].

Customization occurred by varying a metal interconnect mask. Gate arrays had complexities of up to a few thousand gates; this is now called [[mid-scale integration]]. Later versions became more generalized, with different [[Die (integrated circuit)|base dies]] customized by both metal and [[Polycrystalline silicon|polysilicon]] layers. Some base dies also include [[random-access memory]] (RAM) elements.

== Standard-cell designs ==
{{Main|Standard cell}}

In the mid-1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third-party design tools were available, there was not an effective link from the third-party design tools to the [[Integrated circuit layout|layout]] and actual semiconductor process performance characteristics of the various ASIC manufacturers.  Most designers used factory-specific tools to complete the implementation of their designs.  A solution to this problem, which also yielded a much higher density device, was the implementation of [[standard cell]]s.<ref name="MichaelJohnSebastianSmith">{{cite book|author=Smith, Michael John Sebastian|title=Application-Specific Integrated Circuits|publisher=Addison-Wesley Professional|year=1997|isbn=978-0-201-50022-6}}</ref> Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as [[propagation delay]], capacitance and inductance, that could also be represented in third-party tools.  Standard-cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance.  Standard-cell design is intermediate between {{Section link||Gate-array and semi-custom design|nopage=y}} and {{Section link||Full-custom design|nopage=y}} in terms of its non-recurring engineering and recurring component costs as well as performance and speed of development (including [[time to market]]).

By the late 1990s, [[logic synthesis]] tools became available.  Such tools could compile [[Hardware description language|HDL]] descriptions into a gate-level [[netlist]].  Standard-cell [[integrated circuit]]s (ICs) are designed in the following conceptual stages referred to as [[Design flow (EDA)|electronics design flow]], although these stages overlap significantly in practice:
# '''[[Requirements engineering]]''': A team of design engineers starts with a non-formal understanding of the [[Requirement|required functions]] for a new ASIC, usually derived from [[requirements analysis]].
# '''[[Register-transfer level]] (RTL) design''': The design team constructs a description of an ASIC to achieve these goals using a [[hardware description language]].  This process is similar to writing a computer program in a [[High-level programming language|high-level language]].
# '''[[Functional verification]]''': Suitability for purpose is verified by functional verification. This may include such techniques as [[logic simulation]] through [[test bench]]es, [[formal verification]], [[Hardware emulation|emulation]], or creating and evaluating an equivalent pure [[software]] model, as in [[Simics]].  Each verification technique has advantages and disadvantages, and most often several methods are used together for ASIC verification.  Unlike most [[Field-programmable gate array|FPGAs]], ASICs cannot be [[Reconfigurable computing|reprogrammed]] once [[Semiconductor device fabrication|fabricated]] and therefore ASIC designs that are not completely correct are much more costly, increasing the need for full [[test coverage]].
# '''Logic synthesis''': [[Logic synthesis]] transforms the RTL design into a large collection called of lower-level constructs called standard cells.  These constructs are taken from a [[Library (electronics)|standard-cell library]] consisting of pre-characterized collections of [[logic gate]]s performing specific functions.  The standard cells are typically specific to the planned manufacturer of the ASIC.  The resulting collection of standard cells and the needed electrical connections between them is called a gate-level [[netlist]].
# '''Placement''': The gate-level netlist is next processed by a [[placement (EDA)|placement]] tool which places the standard cells onto a region of an [[Die (integrated circuit)|integrated circuit die]] representing the final ASIC.  The placement tool attempts to find an [[Mathematical optimization|optimized]] placement of the standard cells, subject to a variety of specified constraints.
# '''Routing''': An electronics [[Routing (electronic design automation)|routing]] tool takes the physical placement of the standard cells and uses the netlist to create the [[electrical connection]]s between them.  Since the [[Optimization problem#Search space|search space]] is large, this process will produce a "sufficient" rather than "[[Global optimum|globally optimal]]" solution.  The output is a file which can be used to create a set of [[photomask]]s enabling a [[Semiconductor fabrication plant|semiconductor fabrication facility]], commonly called a "fab" or "foundry" to [[Manufacturing|manufacture]] physical [[integrated circuit]]s. Placement and routing are closely interrelated and are collectively called [[place and route]] in electronics design.
# '''Sign-off''': Given the final layout, [[circuit extraction]] computes the [[Parasitic element (electrical networks)|parasitic resistances and capacitances]].  In the case of a [[digital circuit]], this will then be further mapped into [[Propagation delay|delay information]] from which the circuit performance can be estimated, usually by [[static timing analysis]].  This, and other final tests such as [[design rule checking]] and [[power analysis]] collectively called [[Signoff (electronic design automation)|signoff]] are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature.  When this testing is complete the [[photomask]] information is released for [[chip fabrication]].

These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.<ref>{{Cite book|last=Hurley, Jaden Mclean & Carmen.|title=Logic Design|date=2019|publisher=EDTECH|isbn=978-1-83947-319-7|oclc=1132366891}}</ref>

The design steps also called [[Design flow (EDA)|design flow]], are also common to standard product design. The significant difference is that standard-cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than a full custom design. Standard cells produce a [[Transistor density|design density]] that is cost-effective, and they can also integrate [[Semiconductor intellectual property core|IP cores]] and [[static random-access memory]] (SRAM) effectively, unlike gate arrays.

== Gate-array and semi-custom design ==
{{Unreferenced section|date=February 2025}}

[[File:S-MOS Systems ASIC SLA6140.jpg|thumb|Microscope photograph of a gate-array ASIC showing the predefined logic cells and custom interconnections. This particular design uses less than 20% of available logic gates.]]

[[Gate array]] design is a manufacturing method in which diffused layers,<ref name="bteng198307">{{ cite journal | url=https://archive.org/details/bte-198307/page/n19/mode/2up | title=The Use of Gate Arrays in Telecommunications | journal=British Telecommunications Engineering | last1=Grierson | first1=J. R. | date=July 1983 | access-date=26 February 2021 | volume=2 | issue=2 | pages=78–80 | issn=0262-401X | quote=In the UK, Ferranti, with their bipolar collector diffused isolation (CDI) arrays, pioneered the commercial use of gate arrays and for many years this was by far the most widely used technology. }}</ref> each consisting of [[transistor]]s and other [[Active element|active devices]], are predefined and [[Wafer (electronics)|electronics wafers]] containing such devices are "held in stock" or unconnected prior to the [[metallizing|metallization]] stage of the [[fabrication process]].  The [[Physical design (electronics)|physical design]] process defines the interconnections of these layers for the final device.  For most ASIC manufacturers, this consists of between two and nine metal layers with each layer running perpendicular to the one below it. Non-recurring engineering costs are much lower than full custom designs, as [[Photolithography|photolithographic]] masks are required only for the metal layers.  Production cycles are much shorter, as metallization is a comparatively quick process; thereby accelerating [[time to market]].

Gate-array ASICs are always a compromise between rapid design and [[Computer performance|performance]] as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% [[circuit utilization]].  Often difficulties in [[Routing (electronic design automation)|routing]] the interconnect require migration onto a larger array device with a consequent increase in the piece part price.  These difficulties are often a result of the layout [[Electronic design automation|EDA]] software used to develop the interconnect.

Pure, logic-only gate-array design is rarely implemented by circuit designers today, having been almost entirely replaced by [[Field-programmability|field-programmable]] devices. The most prominent of such devices are [[field-programmable gate array]]s (FPGAs) which can be programmed by the user and thus offer minimal tooling charges, non-recurring engineering, only marginally increased piece part cost, and comparable performance.

Today, gate arrays are evolving into [[Structured ASIC platform|structured ASICs]] that consist of a large [[IP core]] like a [[central processing unit|CPU]], [[digital signal processor]] units, [[peripheral]]s, standard [[computer bus|interfaces]], integrated [[Computer memory|memories]], [[Static random-access memory|SRAM]], and a block of [[Reconfigurable computing|reconfigurable]], uncommitted logic. This shift is largely because ASIC devices are capable of integrating large blocks of [[Systems engineering|system]] functionality, and [[System on a chip|systems on a chip]] (SoCs) require [[glue logic]], [[Communications system|communications subsystems]] (such as [[Network on a chip|networks on chip]]), [[peripheral]]s, and other components rather than only [[functional unit]]s and basic interconnection.

In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous when referring to ASICs. [[Process engineering|Process engineers]] more commonly use the term "semi-custom", while "gate-array" is more commonly used by logic (or gate-level) designers.

== Full-custom design ==
{{Main|Full custom}}
[[File:VLSI VL82C486 Single Chip 486 System Controller HV.jpg|thumb|Microscope photograph of custom ASIC (486 chipset) showing gate-based design on top and custom circuitry on bottom]]

By contrast, full-custom ASIC design defines all the photolithographic layers of the device.<ref name="MichaelJohnSebastianSmith"/> Full-custom design is used for both ASIC design and for standard product design.

The benefits of full-custom design include reduced area (and therefore recurring component cost), [[Computer performance|performance]] improvements, and also the ability to integrate [[Analog signal|analog]] components and other [[Semiconductor intellectual property core|pre-designed]]—and thus fully verified—components, such as [[microprocessor]] cores, that form a [[system on a chip]].

The disadvantages of full-custom design can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the [[computer-aided design]] (CAD) and [[electronic design automation]] systems, and a much higher skill requirement on the part of the design team.

For digital-only designs, however, "standard-cell" cell libraries, together with modern CAD systems, can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimize any performance-limiting aspect of the design.

This is designed by using basic logic gates, circuits or layout specially for a design.

== Structured design ==
{{Main|Structured ASIC platform|Platform-based design}}

''Structured ASIC design'' (also referred to as "''platform ASIC design''") is a relatively new trend in the semiconductor industry, resulting in some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC, by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time).

Definition from Foundations of Embedded Systems states that:<ref>{{Cite book|title=Foundations of Embedded Systems|last1=Barkalov|first1=Alexander|last2=Titarenko|first2=Larysa|last3=Mazurkiewicz|first3=Małgorzata|date=2019|publisher=Springer International Publishing|isbn=9783030119607|series=Studies in Systems, Decision and Control|volume=195|location=Cham|language=en|doi=10.1007/978-3-030-11961-4|s2cid=86596100}}</ref> {{quote|In a "structured ASIC" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than "standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design.|sign=|source=Foundations of Embedded Systems}}

This is effectively the same definition as a gate array. What distinguishes a structured ASIC from a gate array is that in a gate array, the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC, the use of predefined metallization is primarily to reduce cost of the mask sets as well as making the design cycle time significantly shorter.

For example, in a cell-based or gate-array design the user must often design power, clock, and test structures themselves. By contrast, these are predefined in most structured ASICs and therefore can save time and expense for the designer compared to gate-array based designs. Likewise, the design tools used for structured ASIC can be substantially lower cost and easier (faster) to use than cell-based tools, because they do not have to perform all the functions that cell-based tools do. In some cases, the structured ASIC vendor requires customized tools for their device (e.g., custom physical synthesis) be used, also allowing for the design to be brought into manufacturing more quickly.

== Cell libraries, IP-based design, hard and soft macros ==
{{Unreferenced section|date=February 2025}}

[[Library (electronics)|Cell libraries]] of logical primitives are usually provided by the device manufacturer as part of the service. Although they will incur no additional cost, their release will be covered by the terms of a [[non-disclosure agreement]] (NDA) and they will be regarded as intellectual property by the manufacturer. Usually, their physical design will be pre-defined so they could be termed "hard macros".

What most engineers understand as "[[intellectual property]]" are [[Semiconductor intellectual property core|IP cores]], designs purchased from a third-party as sub-components of a larger ASIC. They may be provided in the form of a [[hardware description language]] (often termed a "soft macro"), or as a fully routed design that could be printed directly onto an ASIC's mask (often termed a "hard macro"). Many organizations now sell such pre-designed cores – CPUs, Ethernet, USB or telephone interfaces – and larger organizations may have an entire department or division to produce cores for the rest of the organization. The company [[ARM (company)|ARM]] ''only'' sells IP cores, making it a [[Fabless manufacturing|fabless manufacturer]].

Indeed, the wide range of functions now available in structured ASIC design is a result of the phenomenal improvement in electronics in the late 1990s and early 2000s; as a core takes a lot of time and investment to create, its [[Code reuse|re-use]] and further development cuts product cycle times dramatically and creates better products. Additionally, [[open-source hardware]] organizations such as [[OpenCores]] are collecting free IP cores, paralleling the [[open-source software]] movement in hardware design.

Soft macros are often process-independent (i.e. they can be fabricated on a wide range of manufacturing processes and different manufacturers). Hard macros are process-limited and usually further design effort must be invested to migrate (port) to a different process or manufacturer.

== Multi-project wafers ==
{{Unreferenced section|date=February 2025}}

Some manufacturers  and IC design houses offer [[multi-project wafer service]] (MPW) as a method of obtaining low cost prototypes. Often called shuttles, these MPWs, containing several designs, run at regular, scheduled intervals on a "cut and go" basis, usually with limited liability on the part of the manufacturer. The contract involves delivery of bare dies or the assembly and packaging of a handful of devices. The service usually involves the supply of a physical design database (i.e. masking information or pattern generation (PG) tape). The manufacturer is often referred to as a "silicon foundry" due to the low involvement it has in the process.

== Application-specific standard product ==
[[File:Kyocera FS-C5200DN - interface board - Renesas M66591GP-4189.jpg|thumb|[[Renesas Electronics|Renesas]] M66591GP: USB2.0 Peripheral Controller]]
An '''application-specific standard product''' or '''ASSP''' is an [[integrated circuit]] that implements a specific [[Function (engineering)|function]] that appeals to a wide market. As opposed to ASICs that combine a collection of functions and are designed by or for one [[customer]], ASSPs are available as off-the-shelf components. ASSPs are used in all industries, from automotive to communications.<ref>{{cite web |last1=Maxfield |first1=Max |title=ASIC, ASSP, SoC, FPGA – What's the Difference? |url=https://www.eetimes.com/asic-assp-soc-fpga-whats-the-difference/ |website=[[EE Times]] |access-date=2 February 2025 |date=23 June 2014 }}</ref>

For example, two ICs that might or might not be considered ASICs are a controller chip for a PC and a chip for a [[modem]]. Both of these examples are specific to an application (which is typical of an ASIC) but are sold to many different system vendors (which is typical of standard parts). ASICs such as these are sometimes called application-specific standard products (ASSPs).

Examples of ASSPs are encoding/decoding chip, Ethernet network interface controller chip and flash memory controller chip.<ref>{{Cite web |url=https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/ipcore/eurekacores/ep501nandflashcontroller |title=EP501: NAND Flash Controller |archive-url=http://web.archive.org/web/20240418010628/https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/ipcore/eurekacores/ep501nandflashcontroller |archive-date=April 18, 2024 |access-date=May 8, 2025 |website=[[Lattice Semiconductor]] |url-status=live}}</ref>

== See also ==
{{cols}}
* [[Application-specific instruction set processor]] (ASIP)
* [[Complex programmable logic device]] (CPLD)
* [[Electronic design automation]] (EDA or ECAD)
* [[Field-programmable gate array]] (FPGA)
* [[Multi-project chip]] (MPC)
* [[Very Large Scale Integration]] (VLSI)
* [[System on a chip]] (SoC)
* [[Hardware acceleration]] for an overview of computing based primarily in hardware
{{colend}}

== References ==
{{Reflist}}

== Sources ==
* {{cite news|title=Xilinx looks to ease path to custom FPGAs|author=Anthony Cataldo|work=EE Times|date=26 March 2002|url=http://www.eetimes.com/story/OEG20020325S0060|publisher=CMP Media, LLC|access-date=14 December 2006|archive-date=29 September 2007|archive-url=https://web.archive.org/web/20070929100135/http://www.eetimes.com/story/OEG20020325S0060|url-status=dead}}
* {{cite news|title=Xilinx intros next-gen EasyPath FPGAs priced below structured ASICs|work=EDP Weekly's IT Monitor|date=18 October 2004|url=http://www.thefreelibrary.com/Xilinx+intros+next-gen+EasyPath+FPGAs+priced+below+structured+ASICs.-a0125948398|publisher=Millin Publishing, Inc.}}

== External links ==
* {{Commons category-inline|Application-specific integrated circuits}}

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