Editing CDC STAR-100

{{Short description|1974 supercomputer}}
{{Infobox supercomputer
| name         = CDC STAR-100
| image        = CDC_STAR-100_-_8MB_and_4MB_versions.png
| caption      = Two CDC STAR-100, in 8 MB version (forefront) and 4 MB version (background)
| manufacturer = [[Control Data Corporation]]
| designer     = [[James E. Thornton|Jim Thornton]]
| release date = {{Start date|1974}}<ref name="CERN">[http://www.iaea.org/inis/collection/NCLCollectionStore/_Public/10/462/10462027.pdf LARGE COMPUTER SYSTEMS AND NEW ARCHITECTURES, T. Bloch, CERN, Geneva, Switzerland, November 1978]</ref>
| dimensions   = '''Full computer approx:'''<br />Height: {{convert|212|cm|in|abbr=on}}<br />Length: {{convert|745|cm|in|abbr=on}}<br />'''Internal sections:'''<ref name="Atlas"/><br />
Height: {{convert|76|in|cm|abbr=on}}<br />Width: {{convert|28.5|in|cm|abbr=on}}<br />Depth: {{convert|30|in|cm|abbr=on}}
| weight       = {{convert|2200|lb|kg}}
| power        = 250 [[Kilowatt|kW]]
| voltage      = 208 V 400 Hz<ref name="Atlas"/>
| os           = HELIOS <ref name="Atlas">[http://www.chilton-computing.org.uk/acl/literature/minutes/srcaccmtgs/star100.htm#c2p2 A Proposal to the Atlas Computer Laboratory for a STAR Computer System, Michael Baylis, Control Data, April 1972]</ref>
| cpu          = [[64-bit]] [[Processor (computing)|processor]]
| frequency    = 25 [[Megahertz|MHz]]<ref name="CERN"/>
| memory       = Up to 8 [[megabytes]] (4 * 4 * 64K x 64 bits) <ref name="Star100HW">[http://bitsavers.trailing-edge.com/pdf/cdc/cyber/cyber_200/60256000_STAR-100hw_Dec75.pdf Star-100 Hardware Reference Manual]</ref>
| storage      = -
| mips         = 1 MIPS ([[Scalar_processor|Scalar]])<ref name="whetstone">[http://www.roylongbottom.org.uk/whetstone.htm#anchorMore Whetstone Benchmark History and Results]</ref><ref name="Atlas"/>
| flops        = 100 MFLOPS ([[Vector processor|Vector]])<ref name="CERN"/>
| successor    = [[CDC Cyber 200]]
| predecessor  = -
}}
The '''CDC STAR-100''' is a vector [[supercomputer]] that was designed, manufactured, and marketed by [[Control Data Corporation]] (CDC). It was one of the first machines to use a [[vector processor]] to improve performance on appropriate scientific applications. It was also the first supercomputer to use [[integrated circuit]]s and the first to be equipped with one million [[Word (computer architecture)|words]] of [[computer memory]].<ref name="Mackenzie1998"/>

STAR is a [[Blend word|blend]] of '''''ST'''rings'' (of binary digits) and '''''AR'''rays.''<ref name=ring.ray>{{cite conference |author=C. J. Purcell |date=1974 |title=The Control Data STAR-100 - Performance measurements |book-title=AFIPS 1974 International Workshop on Managing Requirements Knowledge |page=385 |doi=10.1109/AFIPS.1974.113 |s2cid=43509695 }}</ref> The 100 alludes to the nominal peak processing speed of '''100''' million floating point operations per second ([[MFLOPS]]);<ref name="Mackenzie1998"/> the earlier [[CDC 7600]] provided peak performance of 36&nbsp;MFLOPS but more typically ran at around 10&nbsp;MFLOPS.

The design was part of a bid made to [[Lawrence Livermore National Laboratory]] (LLNL) in the mid-1960s.<ref name="Mackenzie1998"/> Livermore was looking for a partner who would build a much faster machine on their own budget and then lease the resulting design to the lab. It was announced publicly in the early 1970s, and on 17 August 1971, CDC announced that [[General Motors]] had placed the first commercial order for it.

A number of basic design features of the machine meant that its real-world performance was much lower than expected when first used commercially in 1974, and was one of the primary reasons CDC was pushed from its former dominance in the supercomputer market when the [[Cray-1]] was announced in 1975. Only three STAR-100 systems were delivered, two to LLNL and another to [[NASA Langley Research Center]].

==Description==
The STAR had a 64-bit [[Computer architecture|architecture]], consisting of 195 [[Instruction (computer science)|instructions]].<ref name="CAAPP"/> Its main innovation was the inclusion of 65 vector instructions for [[vector processing]]. The operations performed by these instructions were strongly influenced by concepts and [[Operator (computer programming)|operators]] from the [[APL (programming language)|APL]] programming language; in particular, the concept of "control vectors" (vector masks in modern terminology), and several instructions for vector permutation with control vectors, were carried over directly from APL.<ref>{{Cite book |last1=Hockney |first1=R.W. |title=Parallel Computers: Architecture, Programming and Algorithms |last2=Jesshope |first2=C.R. |publisher=Adam Hilger |year=1981 |page=15}}</ref><ref>{{Cite book |last1=Ibbett |first1=R.N |title=Architecture of High Performance Computers, Volume I: Uniprocessors and vector processors |last2=Topham |first2=N.P |publisher=[[Springer-Verlag]] |year=1989 |page=159}}</ref>

The vector instructions operated on vectors that were stored in consecutive locations in main memory; memory addressing was [[Virtual memory|virtual]]. The vector instructions fed an arithmetic [[Instruction pipelining|pipeline]]; a single instruction could add two variable-length vectors of up to 65,535 elements with just one instruction fetch. The STAR also fetched vector operands in 512-bit units (superwords), reducing average memory latency.

Since the memory location of the "next" operand is known, the CPU can fetch the next operands while it is operating on the previous ones. As with instruction pipelines in general, the time needed to complete any one instruction was no better than it was before, but since the CPU is working on a number of data points at once, the overall performance dramatically improves.

Many of the STAR's instructions were complex, especially the ''vector macro'' instructions, which performed complex operations that normally would have required long sequences of instructions. These instructions, along with the STAR's generally complex architecture, was implemented with [[microcode]].<ref name="SA"/>

Main memory had a capacity of 65,536 512-bit [[Word (data type)|words]], called superwords (SWORDs).<ref name="TAoPC"/> Main memory was 32-way [[Interleaved memory|interleaved]] to pipeline memory accesses. It was constructed from [[core memory]] with an [[access time]] of 1.28&nbsp;μs. The main memory was accessed via a 512-bit bus, controlled by the ''storage access controller'' (SAC), which handled requests from the ''stream unit''. The stream unit accesses the main memory through the SAC via three 128-bit data buses, two for reads, and one for writes. There is also a 128-bit data bus for instruction fetch, I/O, and control vector access. The stream unit serves as the control unit, fetching and decoding instructions, initiating memory accesses on the behalf of the pipelined functional units, and controlling instruction execution, among other tasks. It also contains two read buffers and one write buffer for streaming data to the execution units.<ref name="TAoPC"/>

The STAR-100 has two arithmetic pipelines. The first has a floating point adder and multiplier, and the second can execute all scalar instructions. It also contains a floating point adder, multiplier, and divider. Both pipelines are 64-bit for floating point operations and are controlled by microcode. The STAR-100 can split its floating point pipelines into four 32-bit pipelines, doubling the peak performance of the system to 100&nbsp;MFLOPS at the expense of half the precision.<ref name="TAoPC"/>

The STAR-100 uses I/O processors to offload I/O from the CPU. Each I/O processor is a 16-bit [[minicomputer]] with its own main memory of 65,536 words of 16 bits each, which is implemented with core memory. The I/O processors all share a 128-bit data bus to the SAC.

==Real-world performance, users and impact==
The STAR-100's real-world performance was a fraction of its theoretical performance for a number of reasons. Firstly, the vector instructions, being "memory-to-memory," had a relatively long startup time, since the pipeline from the memory to the functional units was very long. In contrast to the register-based pipelined functional units in the 7600, the STAR pipelines were much deeper. The problem was compounded by the fact that the STAR had a slower cycle time than the 7600 (40&nbsp;ns vs 27.5&nbsp;ns). So the vector length needed for the STAR to run faster than the 7600 occurred at about 50 elements; if the loops were working on data sets with fewer elements, the time cost of setting up the vector pipeline was higher than the time savings provided by the vector instruction(s).

When the machine was released in 1974, it quickly became apparent that the general performance was disappointing. Very few programs can be effectively vectorized into a series of single instructions; nearly all calculations will rely on the results of some earlier instruction, yet the results had to clear the pipelines before they could be fed back in. This forced most programs to pay the high setup cost of the vector units, and generally the ones that did "work" were extreme examples. Worse, basic scalar performance was sacrificed to improve vector performance. Any time that the program had to run scalar instructions, the overall performance of the machine dropped dramatically. (See [[Amdahl's Law]].)

Two STAR-100 systems were eventually delivered to the [[Lawrence Livermore National Laboratory]] and one to NASA [[Langley Research Center]].<ref name="PC2"/> In preparation for the STAR deliveries, LLNL programmers developed a [[Library (computing)|library]] of [[subroutine]]s, called ''STACKLIB'', on the 7600 to [[emulator|emulate]] the vector operations of the STAR. In the process of developing STACKLIB, they found that programs converted to use it ran faster than they had before, even on the 7600. This placed further pressures on the performance of the STAR.

The STAR-100 was a disappointment to everyone involved. [[James E. Thornton|Jim Thornton]], formerly [[Seymour Cray]]'s close assistant on the [[CDC 1604]] and [[CDC 6600|6600]] projects and the chief designer of STAR, left CDC to form [[Network Systems Corporation]]. An updated version of the basic architecture was later released in 1979 as the [[CDC Cyber#Cyber 200 series|Cyber 203]],<ref name="PC2"/> followed by the [[CDC Cyber#Cyber 200 series|Cyber 205]] in 1980, but by this point systems from [[Cray Research]] with considerably higher performance were on the market. The failure of the STAR led to CDC being pushed from its former dominance in the supercomputer market, something they tried to address with the formation of [[ETA Systems]] in September 1983.<ref name="PC2"/>

==Installations==
Five CDC STAR-100s were built. Deliveries started from 1974:<ref name="CERN"/>
* Control Data Corporation, Arden Hills, MN (2)
* Lawrence Livermore National Laboratory. (2)
* NASA Langley

==References==
{{reflist|refs=
<ref name="PC2">R.W. Hockney and C.R. Jesshope, ''Parallel Computers 2: Architecture, Programming and Algorithms'', Adam Hilger, 1988, p.&nbsp;21.</ref>
<ref name="TAoPC">P.M. Kogge, ''The Architecture of Pipelined Computers'', Taylor & Francis, 1981, pp.&nbsp;162&ndash;164.</ref>
<ref name="Mackenzie1998">{{cite book|url=https://books.google.com/books?id=c5YaHkcP6DEC&pg=PA120|title=Knowing Machines: Essays on Technical Change|first=Donald |last=MacKenzie|publisher=MIT Press |date=1998|isbn=978-0-262-63188-4}}</ref>
<ref name="CAAPP">{{cite book |last1=Hwang |first1=Kai |last2=Briggs |first2=Fayé Alayé |title=Computer Architecture and Parallel Processing |date=1984 |publisher=McGraw-Hill |pages=234&ndash;249}}</ref>
<ref name="SA">{{cite book |last1=Schneck | first1=P.B. |title=Supercomputer Architecture |date=1987 |publisher=Kluwer Academic |pages=99&ndash;118}}</ref>
}}

==Further reading==
* R.G. Hintz and D.P. Tate, "Control Data STAR-100 processor design," ''Proc. Compcon'', 1972, pp.&nbsp;1&ndash;4.

==External links==
* [http://purl.umn.edu/104327 Neil R. Lincoln with 18 Control Data Corporation (CDC) engineers on computer architecture and design], [[Charles Babbage Institute]], University of Minnesota.  Engineers include Robert Moe, Wayne Specker, Dennis Grinna, Tom Rowan, Maurice Hutson, Curt Alexander, Don Pagelkopf, Maris Bergmanis, Dolan Toth, Chuck Hawley, Larry Krueger, Mike Pavlov, Dave Resnick, Howard Krohn, Bill Bhend, Kent Steiner, Raymon Kort, and Neil R. Lincoln.  Discussion topics include [[CDC 1604]], [[CDC 6600]], [[CDC 7600]], [[CDC 8600]], CDC STAR-100 and [[Seymour Cray]].

{{Control Data Corporation}}

{{DEFAULTSORT:CDC STAR-100}}
[[Category:Control Data Corporation hardware|STAR-100]]
[[Category:Vector supercomputers]]
[[Category:Control Data Corporation mainframe computers]]
[[Category:64-bit computers]]