Editing COP8

{{about|COP8 microcontroller|8th Climate Change Conference of the Parties|2002 United Nations Climate Change Conference}}
{{Short description|8-bit microcontroller}}
{{Infobox CPU
|name           = National Semiconductor COP8
|produced-start = {{Start date and age|1988}}
|numinstructions = 69
|produced-end   = 
|data-width     = 8 (RAM), 8 (ROM)
|address-width  = 8 (RAM), 15 (ROM)
|slowest        = 0 | slow-unit = Hz
|fastest        = 2 | fast-unit = MHz
|transistors    = 
|manuf1         = [[National Semiconductor]]
|application    = Embedded
|arch           = COP8
|pack1          = 20, 28, and 40-pin [[Dual in-line package|DIP]]; 16, 20, and 28 pin [[Small outline integrated circuit|SOIC]]; 44-pin [[Chip carrier|PLCC]]
|predecessor    = [[COP400]]
|successor      = none
}}

The [[National Semiconductor]] '''COP8''' is an 8-bit [[Complex instruction set computer|CISC]] core [[microcontroller]]. COP8 is an enhancement to the earlier [[COP400]] 4-bit microcontroller family. COP8 main features are:

* Large amount of [[I/O]] pins
* Up to 32&nbsp;KB of [[Flash memory]]/[[Read-only memory|ROM]] for code and data 
* Very low [[Electromagnetic interference|EMI]]
* Many integrated peripherals (meant as single chip design)
* [[In-System Programming]]
* Free [[Assembly language|assembler]] toolchain. Commercial [[C (programming language)|C]] compilers available
* Free Multitasking OS and [[TCP/IP]] stack
* Peak of 2 million instructions per second

The COP8 has a basic instruction cycle time 1/10 of the clock frequency; a maximum 10&nbsp;MHz clock will result in a maximum 1&nbsp;MHz instruction execution rate.  (The 10&nbsp;MHz clock is used directly by some timer peripherals.)   The maximum instruction execution rate is 1 cycle per byte, and most 1-byte instructions operate in one instruction cycle.  Some, particularly branch instructions, take one or two cycles more.  Some models include a clock doubler, and although they still accept a maximum 10&nbsp;MHz input clock, they internally double it to a 20&nbsp;MHz master clock which then results in a 2&nbsp;MHz instruction execution rate.{{r|cop8s|p=7,32}}

The chip is a [[static logic]] design which can tolerate an arbitrarily slow clock;{{r|cop8s|p=10}} most models include a second {{val|32768|u=Hz}} [[quartz clock]] crystal oscillator which can be used for the CPU clock while the high-speed clock is disabled to save power.

==Registers and memory map==
{| class="infobox" style="font-size:88%;width:26em;"
|-
|+ COP8 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit position)''
|-
|colspan="17" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="7" | 
| style="text-align:center;" colspan="8"| A
| style="width:auto; background:white; color:black;"| '''A'''ccumulator
|- style="background:silver;color:black"
| style="text-align:center;" colspan="7"| PCU
| style="text-align:center;" colspan="8"| PCL
| style="background:white; color:black;"| '''P'''rogram&nbsp;'''C'''ounter
|-
|colspan="20" | Note: All other programmer-visible registers and status bits are allocated in RAM.
|}
|}
The COP8 uses separate instruction and data spaces ([[Harvard architecture]]).{{r|basic|p=2-1|comparison|p2=2-4}}  Instruction address space is 15-bit (32&nbsp;KiB maximum), while data addresses are 8-bit (256 bytes maximum, extended via bank-switching).

To allow software bugs to be caught, all invalid instruction addresses read as zero, which is a trap instruction.  Invalid RAM above the stack reads as all-ones, which is an invalid address.

The CPU has an 8-bit accumulator and 15-bit [[program counter]].  16 additional 8-bit registers (R0–R15) and an 8-bit [[program status word]] are memory mapped.  There are special instructions to access them, but general RAM access instructions may also be used.

The memory map is divided into half RAM and half control registers as follows:
{|class="wikitable"
|+ COP8 data address space
|-
! Addresses || Use
|-
| 0x00–6F || General purpose RAM, used for stack
|-
| 0x70–7F || Unused, reads as all-ones (0xFF) to trap stack underflows
|-
| 0x80–8F || Unused, reads undefined
|-
| 0x90–BF || Additional peripheral control registers
|-
| 0xC0–CF || Peripheral control registers.
|-
| 0xD0–DF || General purpose I/O ports L, G, I, C and D
|-
| 0xE0–E8 || Reserved
|-
| 0xE9 || [[Microwire]] shift register
|-
| 0xEA–ED || Timer 1 registers
|-
| 0xEE || CNTRL register, control bits for Microwire & Timer 1
|-
| 0xEF || PSW, CPU program status word
|-
| 0xF0–FB || R0–R11, on-chip RAM mapped as registers
|-
| 0xFC || R12, a.k.a. X, secondary indirect pointer register
|-
| 0xFD || R13, a.k.a. SP, stack pointer register
|-
| 0xFE || R14, a.k.a. B, primary indirect pointer register
|-
| 0xFF || R15, a.k.a. S, data segment extension register
|}
If RAM is not banked, then R15 (S) is just another general-purpose register.  If RAM is banked, then the low half of the data address space (addresses 0x00–7F) is directed to a RAM bank selected by S.  The special purpose registers in the high half of the data address space are always visible.  The data registers at 0xF''x'' can be used to copy data between banks.

RAM banks other than bank 0 have all 128 bytes available.  The stack (addressed via the stack pointer) is always on bank 0, no matter how the S register is set.

==Control transfers==
In addition to 3-byte {{code|JMPL}} and {{code|JSRL}} instructions which can address the entire address space, 2-byte versions of these instructions, {{code|JMP}} and {{code|JSR}}, can jump within a 4K page.  The instruction specifies the low 12 bits, and the high 3 bits of the PC are preserved.  (These are intended primarily for models with up to 4K of ROM.) For short-distance branches, there are 63 1-byte instructions, {{code|JP}}, which perform PC-relative branches from PC−32 to PC+31.  This is a 15-bit addition, and no page boundary requirements apply.

There are also jump indirect and load accumulator indirect instructions which use the accumulator contents as the low 8 bits of an address; the high 7 bits of the current PC are preserved.

Conditional branches ''per se'' do not exist, nor does the processor provide the [[Status register#Common flags|traditional ZCVN status flags]], although the program status word contains [[Carry flag|carry]] and [[half-carry flag]]s for multi-byte arithmetic.  Rather, there are a number of compare-and-skip instructions.  For example, {{code|IFEQ}} compares its two operands, and skips the following instruction if they are unequal.  Any instruction may be skipped; it is not limited to branches.

An interesting extension of this mechanism is the {{code|RETSK}} return-and-skip instruction, which lets any subroutine conditionally skip the instruction following the call.  This provides a very compact way to return a [[Boolean data type|boolean value]] from a subroutine.

Another feature unique to the COP8 architecture is the {{code|IFBNE}} instruction.  This one-byte instruction compares the low 4 bits of the B (memory pointer) register with a 4-bit immediate constant, and can be used to loop until B has reached the end of a small (up to 16 byte) buffer.  There is also a one-byte {{code|LD B,#imm4}} instruction.

== Instruction set ==
COP8 operands are listed in destination, source order.  Most instructions have the accumulator A as one of the operands.  The other operand is generally chosen from an 8-bit immediate value, an 8-bit RAM address, or {{code|[B]}}, the RAM address selected by the B register.  The {{code|LD}} and {{code|X}} (exchange with accumulator) instructions also support RAM addressing by the X register ({{code|[X]}}) and post-inc/decrement variants ({{code|[B+]}}, {{code|[B−]}}, {{code|[X+]}}, {{code|[X−]}}).

Indirect addressing via B is particularly fast, and can be done in the same cycle that the instruction is executed; even {{code|X A,[B]}} is a one-cycle instruction.

On the other hand, absolute RAM addressing is only directly encoded for five instructions: <code>LD A,''addr8''</code>, <code>X A,''addr8''</code>, <code>IFEQ ''addr8'',#''imm8''</code>, <code>LD ''addr8'',#''imm8''</code>, and [[#DIR|<code>DIR ''addr8''</code>]].<!--JSRB takes a ROM address-->  The latter is a "direct addressing" prefix opcode which may be prepended to any instruction with a {{code|[B]}} operand, and changes the operand to the specified memory location.  (Conditional-skip instructions skip the prefix and following instruction as a pair.)  Using {{code|DIR}} with the {{code|LD A,[B]}}, {{code|X A,[B]}} and <code>LD [B],#''imm8''</code> instructions is not documented, as the dedicated instructions are more efficient.

All "move" instructions are called {{code|LD}} (load) even if the destination is a memory address (<code>LD ''addr8'',#''imm8''</code>).  Unusually, there are no {{code|LD}} instructions with the accumulator as a source; stores must be done with the {{code|X}} instruction which ''exchanges'' the accumulator with the memory operand, storing A and loading the previous memory contents.  

There are instructions to fetch from tables in ROM.  These combine the high 7 bits of the program counter (PCU) with the accumulator, fetch a byte from that address, and place it in the accumulator ({{code|LAID}} instruction) or the low 8 bits of the program counter PCL ({{code|JID}} instruction).  Because the next instruction executed must be in the same 256-byte page of ROM as the table itself, a 256-entry table is not possible.

{|class="wikitable" style="text-align:center"
|+ COP8 family instruction set<ref name=basic>{{cite book |title=COP8 Basic Family User's Manual |version=Revision 002 |date=June 1996 |id=Literature Number 620895-002 |publisher=[[National Semiconductor]] |url=http://bitsavers.org/components/national/_dataBooks/1996_National_COP8_Basic_Family_Users_Manual.pdf |access-date=2021-01-02}}</ref><ref name=feature>{{cite book |title=COP8 Feature Family User's Manual |version=Revision 005 |date=March 1999 |id=Literature Number 620897-005 |publisher=[[National Semiconductor]]}}  Extracted from [[ZIP (file format)|zipped]] [[ISO image]] [http://bitsavers.informatik.uni-stuttgart.de/components/national/cop8/cdrom/530094-003_COP8_Tools_Docs_Aug1999.zip 530094-003_COP8_Tools_Docs_Aug1999.zip], retrieved 2020-01-07.</ref><ref name=comparison>{{cite web |title=Comparison of COP878x to the Enhanced COP8SAx7 Family - Hardware/Software Considerations |first=Abdul |last=Aleaf |publisher=[[National Semiconductor]] |date=July 1996 |id=Application Note 1043 |url=https://www.ti.com/lit/an/snoa378/snoa378.pdf}}</ref><ref>{{cite web |title=COP8SAx Designer's Guide |id=Literature Number 620894-001 |date=January 1997 |publisher=[[National Semiconductor]] |url=http://datasheet.elcodis.com/pdf/12/40/124000/dm-cop820d.pdf}}</ref>
!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Cycles ||rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| INTR || 7 ||align=left| Software interrupt (push PC, PC ← 0x00ff)
|-
| 0 || 0 || 0 ||colspan=5| ''offset'' || &mdash; || &mdash; ||align=left| JP +''disp5'' || 3 ||align=left| PC ← PC + ''offset''; jump 1&ndash;31 bytes forward (offset≠0)
|-
| 0 || 0 || 1 || 0 ||colspan=4| ''high'' || ''low'' || &mdash; ||align=left| JMP ''addr12'' || 3 ||align=left| PC[11:0] ← ''addr''.  Top 3 bits of PC preserved.
|-
| 0 || 0 || 1 || 1 ||colspan=4| ''high'' || ''low'' || &mdash; ||align=left| JSR ''addr12'' || 5 ||align=left| Jump to subroutine: push PC, proceed as JMP.
|-
| 0 || 1 || 0 || 0 ||colspan=4| ''k'' || &mdash; || &mdash; ||align=left| IFBNE #''imm4'' || 1 ||align=left| Skip next instruction if (B & 15) = ''k''.
|-
| 0 || 1 || 0 || 1 ||colspan=4| ''k'' || &mdash; || &mdash; ||align=left| LD B,#''imm4'' || 1 ||align=left| B ← 15 − ''k'' (zero-extended)
|-
|colspan=13|
|-
! 0 || 1 || 1 || 0 || 0 ||colspan=3| ''opcode'' ||  || &mdash; ||colspan=3| Miscellaneous instructions
|-
| 0 || 1 || 1 || 0 || 0 || 0 || 0 || 0 || ''k'' || &mdash; ||align=left| ANDSZ A,#''imm8''{{efn|name=feature}} || 2 ||align=left| Skip if A & ''k'' = 0 (=IFBIT #''bit'',A)
|-
| 0 || 1 || 1 || 0 || 0 || 0 || 0 || 1 || ''addr'' || &mdash; ||align=left| JSRB ''addr8''{{efn|name=flash}} || 5 ||align=left| Push PC, jump to boot ROM subroutine at address<ref name=cop8s>{{cite web |title=COP8SBR9/COP8SCR9/COP8SDR98-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |type=data sheet |date=April 2002 |publisher=[[National Semiconductor]] |url=http://radio-hobby.org/uploads/datasheet/39/cop8/cop8sdr9.pdf |accessdate=2021-01-06}}</ref><!--See also cop8cdr9.pdf-->

|- style="background:lightgrey;"
| 0 || 1 || 1 || 0 || 0 || 0 || 1 || &ndash; || &mdash;  || &mdash; ||colspan=3 align=left| ''(reserved for boot ROM)''{{efn|name=flash}}{{r|cop8s}}<!--One instruction is RETF to return from boot ROM to flash.  Not sure what the other is.  JSRBL?-->
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| CLR A || 1 ||align=left| A ← 0
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| SWAP A || 1 ||align=left| A ← A<<4 {{pipe}} A>>4; swap nibbles
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| DCOR A || 1 ||align=left| Decimal correct after [[Binary-coded decimal|BCD]] addition
|-
| 0 || 1 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| PUSH A{{efn|name=feature}} || 3 ||align=left| [SP] ← A, SP ← SP−1
|-
|colspan=12|
|-
! 0 || 1 || 1 ||colspan=2| ''opc'' ||colspan=3| ''bit'' || &mdash; || &mdash; ||colspan=3| Bit operations on [B]{{efn|name=dir}}
|-
| 0 || 1 || 1 || 0 || 1 ||colspan=3| ''bit'' || &mdash; || &mdash; ||align=left| RBIT #''bit'',[B]{{efn|name=dir}}  || 1 ||align=left| Reset (clear to 0) given bit of RAM
|-
| 0 || 1 || 1 || 1 || 0 ||colspan=3| ''bit'' || &mdash; || &mdash; ||align=left| IFBIT #''bit'',[B]{{efn|name=dir}} || 1 ||align=left| Test given bit of RAM, skip if zero
|-
| 0 || 1 || 1 || 1 || 1 ||colspan=3| ''bit'' || &mdash; || &mdash; ||align=left| SBIT #''bit'',[B]{{efn|name=dir}} || 1 ||align=left| Set (to 1) given bit of RAM
|-
|colspan=12|
|-
! 1 || 0 || 0 || ''m'' || 0 ||colspan=3| ''opcode'' || ''k?'' || &mdash; ||colspan=3| Binary operations, A ← A op ''operand''
|-
| 1 || 0 || 0 || 0 || 0 ||colspan=3| ''opcode'' || &mdash; || &mdash; ||align=left| ''OP'' A,[B]{{efn|name=dir}} || 1 ||align=left| A ← A op [B]
|-
| 1 || 0 || 0 || 1 || 0 ||colspan=3| ''opcode'' || ''k'' || &mdash; ||align=left| ''OP'' A,#''imm8'' || 2 ||align=left| A ← A op  ''k''
|-
| 1 || 0 || 0 || ''m'' || 0 || 0 || 0 || 0 || ''k?'' || &mdash; ||align=left| ADC A,''operand'' || ||align=left| C,A ← A + ''operand'' + C; add with carry
|-
| 1 || 0 || 0 || ''m'' || 0 || 0 || 0 || 1 || ''k?'' || &mdash; ||align=left| SUBC A,''operand'' || ||align=left| C,A ← A + ~''operand'' + C (A − ''operand'' − ~C)
|-
| 1 || 0 || 0 || ''m'' || 0 || 0 || 1 || 0 || ''k?'' || &mdash; ||align=left| IFEQ A,''operand'' || ||align=left| Skip if A ≠ ''operand''
|-
| 1 || 0 || 0 || ''m'' || 0 || 0 || 1 || 1 || ''k?'' || &mdash; ||align=left| IFGT A,''operand'' || ||align=left| Skip if A ≤ ''operand''
|-
| 1 || 0 || 0 || ''m'' || 0 || 1 || 0 || 0 || ''k?'' || &mdash; ||align=left| ADD A,''operand'' || ||align=left| A ← A + ''operand'' (carry unchanged!)
|-
| 1 || 0 || 0 || ''m'' || 0 || 1 || 0 || 1 || ''k?'' || &mdash; ||align=left| AND A,''operand'' || ||align=left| A ← A & ''operand''
|-
| 1 || 0 || 0 || ''m'' || 0 || 1 || 1 || 0 || ''k?'' || &mdash; ||align=left| XOR A,''operand'' || ||align=left| A ← A ^ ''operand''
|-
| 1 || 0 || 0 || ''m'' || 0 || 1 || 1 || 1 || ''k?'' || &mdash; ||align=left| OR A,''operand'' || ||align=left| A ← A {{pipe}} ''operand''
|-
|colspan=13|
|-
! 1 || 0 || 0 || 0 || 1 ||colspan=3| ''opcode'' || &mdash; || &mdash; ||colspan=3| Zero-operand instructions
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| IFC || 1 ||align=left| Skip if carry clear
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| IFNC || 1 ||align=left| Skip if carry set
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| INC A || 1 ||align=left| A ← A + 1 (carry unchanged)
|-
| 1 || 0 || 0 || 0 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| DEC A || 1 ||align=left| A ← A − 1 (carry unchanged)
|-
| 1 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| POP A{{efn|name=feature}} || 3 ||align=left| SP ← SP+1, A ← [SP]
|-
| 1 || 0 || 0 || 0 || 1 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| RETSK || 5 ||align=left| Pop PC, skip one instruction
|-
| 1 || 0 || 0 || 0 || 1 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| RET || 5 ||align=left| Pop PC high, pop PC low
|-
| 1 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RETI || 5 ||align=left| Return and enable interrupts
|-
|colspan=13|
|-
! 1 || 0 || 0 || 1 || 1 ||colspan=3| ''opcode'' || ''k'' || &mdash; ||colspan=3| Instructions with immediate operand
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 0 || 0 || ''k'' || &mdash; ||align=left| LD A,#''imm8'' || 2 ||align=left| A ← ''k''
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 0 || 1 || ''k'' || &mdash; ||align=left| IFNE A,#''imm8''{{efn|name=feature}} || 2 ||align=left| Skip if A = ''k''
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || ''k'' || &mdash; ||align=left| LD [B+],#''imm8'' || 3 ||align=left| [B] ← ''k'', B ← B + 1
|-
| 1 || 0 || 0 || 1 || 1 || 0 || 1 || 1 || ''k'' || &mdash; ||align=left| LD [B−],#''imm8'' || 3 ||align=left| [B] ← ''k'', B ← B − 1
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 0 || 0 || ''addr'' || &mdash; ||align=left| X A,''addr8'' || 3 ||align=left| A ↔ [''addr''], exchange
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 0 || 1 || ''addr'' || &mdash; ||align=left| LD A,''addr8'' || 3 ||align=left| A ← [''addr'']
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 1 || 0 || ''k'' || &mdash; ||align=left| LD [B],#''imm8'' || 2 ||align=left| [B] ← ''k''
|-
| 1 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || ''k'' || &mdash; ||align=left| LD B,#''imm8''{{efn|name=feature}} || 2 ||align=left| B ← ''k'' (=LD R14,#''k'', one cycle faster)
|-
|colspan=13|
|-
! 1 || 0 || 1 ||colspan=3| ''opcode'' || 0 || ''c'' ||  ||  ||colspan=3| Miscellaneous instructions
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| RC || 1 ||align=left| C ← 0; reset carry to 0
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| SC || 1 ||align=left| C ← 1; set carry to 1
|-
| 1 || 0 || 1 || 0 || 0 || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| LAID || 3 ||align=left| A ← ROM[PCU:A]; load from ROM
|-
| 1 || 0 || 1 || 0 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| JID || 3 ||align=left| PCL ← ROM[PCU:A]; jump via ROM table
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| RLC A{{efn|name=feature}} || 1 ||align=left| C,A ← A,C; rotate left through carry (=ADC A,A) 
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 0 || 1 || ''addr'' || ''k'' ||align=left| IFEQ ''addr8'',#''imm8''{{efn|name=feature}} || 3 ||align=left| Skip if [''addr''] ≠ ''k''
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || ''high'' || ''low'' ||align=left| JMPL ''addr15'' || 4 ||align=left| PC ← ''address''
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 0 || 1 || ''high'' || ''low'' ||align=left| JSRL ''addr15'' || 5 ||align=left| Push PC, PC ← ''address''
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| RRC A || 1 ||align=left| A,C ← C,A; rotate right through carry
|- style="background:lightgrey;"
| 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || &mdash; || &mdash; ||colspan=3 align=left| ''(reserved)''
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| VIS{{efn|name=feature}} || 5 ||align=left| PC ← ROM[''vector table'']; Vector Interrupt Select
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| RPND{{efn|name=feature}} || 1 ||align=left| Reset pending interrupt flag
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| NOP || 1 ||align=left| No operation
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| IFNE A,[B]{{efn|name=feature}}{{efn|name=dir}} || 1 ||align=left| Skip if A = [B]
|-
| 1 || 0 || 1 || 1 || 1 || 1 || 0 || 0 || ''addr'' || ''k'' ||align=left| LD ''addr8'',#''imm8'' || 3 ||align=left| [''addr''] ← ''k''
|-
| 1 || 0 || 1 || 1 || 1 || 1 || 0 || 1 || ''addr'' || &mdash; ||align=left| {{Anchor|DIR}}DIR ''addr8'' || 3 ||align=left| Change next instruction's operand from [B] to [''addr'']
|-
|colspan=13|
|-
! 1 || 0 || 1 || ''R'' || ''L'' || ''='' || 1 || ''±'' || &mdash; || &mdash; ||colspan=3| Load/exchange operations
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| X A,[B+] || 2 ||align=left| A ↔ [B], B ← B+1
|-
| 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| X A,[B−] || 2 ||align=left| A ↔ [B], B ← B−1
|-
| 1 || 0 || 1 || 0 || 0 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| X A,[B] || 1 ||align=left| A ↔ [B]
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| LD A,[B+] || 2 ||align=left| A ← [B], B ← B+1
|-
| 1 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| LD A,[B−] || 2 ||align=left| A ← [B], B ← B−1
|-
| 1 || 0 || 1 || 0 || 1 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| LD A,[B] || 1 ||align=left| A ← [B]
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| X A,[X+] || 3 ||align=left| A ↔ [X], X ← X+1
|-
| 1 || 0 || 1 || 1 || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| X A,[X−] || 3 ||align=left| A ↔ [X], X ← X−1
|-
| 1 || 0 || 1 || 1 || 0 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| X A,[X] || 3 ||align=left| A ↔ [X]
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| LD A,[X+] || 3 ||align=left| A ← [X], X ← X+1
|-
| 1 || 0 || 1 || 1 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| LD A,[X−] || 3 ||align=left| A ← [X], X ← X−1
|-
| 1 || 0 || 1 || 1 || 1 || 1 || 1 || 0 || &mdash; || &mdash; ||align=left| LD A,[X] || 3 ||align=left| A ← [X]
|- style="background:lightgrey;"
| 1 || 0 || 1 ||colspan=2| &mdash; || 1 || 1 || 1 || &mdash; || &mdash; ||colspan=3 align=left| ''(reserved)''
|-
|colspan=13|
|-
| 1 || 1 || 0 || 0 ||colspan=4| ''register'' || &mdash; || &mdash; ||align=left| DRSZ ''register'' || 3 ||align=left| ''register'' ← ''register'' − 1, skip if result is zero
|-
| 1 || 1 || 0 || 1 ||colspan=4| ''register'' || ''k'' || &mdash; ||align=left| LD ''register'',#''imm8'' || 3 ||align=left| ''register'' ← ''k'' (=LD 0xf0+''register'',#''k'', one byte shorter)
|-
| 1 || 1 || 1 ||colspan=5| ''offset'' || &mdash; || &mdash; ||align=left| JP −''disp5'' || 3 ||align=left|  PC ← PC − 32 + ''offset''; jump 1&ndash;32 bytes backward
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Cycles  || Description
|}
{{notelist|refs=
{{efn|name=feature|Only on "feature family" (COP888/COP8SA) cores; not present on "basic family" (COP800) cores.}}
{{efn|name=flash|Only on "flash family" (COP8TA/COP8C) models with boot ROM for [[in-system programming]].}}
{{efn|name=dir|Operand may be changed from {{code|[B]}} to 8-bit absolute address with a [[#DIR|{{code|DIR}} prefix]] (+2 bytes, +3 cycles).}}
}}

==Notable uses==
* The COP8 family is employed in the FMU-139 [[aerial bomb]] fuze <ref>{{cite conference |url=https://ndiastorage.blob.core.usgovcloudapi.net/ndia/2006/fuze/liberatore.pdf |first=David |last=Liberatore |title=FMU-139C/B Electronic Bomb Fuze Design Update |conference=50th Annual NDIA Fuze Conference |date=11 May 2006 |access-date=7 Nov 2024}} </ref>
*The COP822 is employed in the M732A2 [[artillery]] fuze <ref>{{cite book|first1=Marc |last1=Dennis |first2=Bob |last2=Hanrahan |first3=Chris |last3=Brackmann |title=Application Note 761 - Electronic Fuzing |url=https://www.ti.com/lit/an/snoa217/snoa217.pdf |publisher=Texas Instruments |date=November 1991 |access-date=7 Nov 2024}}</ref>

== References ==
{{reflist}}

==External links==
* [https://microcontroller.com/National_Semiconductor_Embedded_Microcontrollers.htm National Semiconductor Embedded Microcontrollers] ([[CR16]] and COP8)
* [http://www.faqs.org/faqs/microcontroller-faq/COP8/ microcontroller-faq/COP8], 1995
* {{cite journal |title=National Semiconductor COP8 |department=EDN's 25th Annual Microprocessor/Microcontroller Directory |journal=[[EDN (magazine)|EDN]] |date=24 September 1998 |access-date=|url=https://www.edn.com/09-24-98-national-semiconductor-cop8-edns-25th-annual-microprocessor-microcontroller-director/}}

{{8bitMCUs}}

{{DEFAULTSORT:Cop8}}
[[Category:Microcontrollers]]