Editing DDR2 SDRAM

{{short description|Second generation of double-data-rate synchronous dynamic random-access memory}}
{{Infobox memory
| abbr       = DDR2 SDRAM
| name       = Double Data Rate 2 Synchronous Dynamic Random-Access Memory
| image      = Swissbit 2GB PC2-5300U-555.jpg
| caption    = Front and back of a 2GB PC2-5300 DDR2 RAM module for desktop PCs (DIMM)
| developer  = [[Samsung]]<ref name="phys"/> <br /> [[JEDEC]]
| type       = [[Synchronous dynamic random-access memory]]
| generation = 2nd generation
| release    = {{Start date and age|2003|09}}
| standards  = {{Unbulleted list|DDR2-400 (PC2-3200)|DDR2-533 (PC2-4200)|DDR2-667 (PC2-5300)|DDR2-800 (PC2-6400)|DDR2-1066 (PC2-8500)}}
| clock_rate = {{Nowrap|100–266 MHz}}
| cycle_time = {{Nowrap|10–3.75 ns}}
| prefetch   = 4n
| bus_clock_rate = {{Nowrap|200–533 MHz}}
| transfer_rate  = {{Nowrap|400–1066 MT/s}}
| bandwidth = {{Nowrap|3,200–8,533 MB/s}}
| voltage   = {{Nowrap|1.8 V}}
| predecessor = [[DDR SDRAM]]
| successor = [[DDR3 SDRAM]]
}}
'''Double Data Rate 2 Synchronous Dynamic Random-Access Memory''' ('''DDR2 SDRAM''') is a [[double data rate]] (DDR) [[synchronous dynamic random-access memory]] (SDRAM) [[External memory interface|interface]]. It is a [[JEDEC]] standard (JESD79-2); first published in September 2003.<ref>{{Cite web |date=2003-09-12 |title=JEDEC Publishes DDR2 Standard |url=http://www.jedec.org/Home/press/press_release/jedec_publishes_DD2Std.pdf |url-status=dead |archive-url=https://web.archive.org/web/20031204212300/http://www.jedec.org/home/press/press_release/jedec_publishes_DD2Std.pdf |archive-date=2003-12-04}}</ref> DDR2 succeeded the original [[DDR SDRAM]] specification, and was itself succeeded by [[DDR3 SDRAM]] in 2007. DDR2 [[DIMM]]s are neither [[Forward compatibility|forward compatible]] with DDR3 nor [[Backward compatibility|backward compatible]] with DDR.

In addition to double pumping the data [[Bus (computing)|bus]] as in DDR SDRAM (transferring data on the rising and falling edges of the bus [[clock signal]]), DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to produce a total of four data transfers per internal clock cycle.

Since the DDR2 internal clock runs at half the DDR external clock rate, DDR2 memory operating at the same external data bus clock rate as DDR results in DDR2 being able to provide the same [[Bandwidth (computing)|bandwidth]] but with better [[Memory timings|latency]]. Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. The best-rated DDR2 memory modules are at least twice as fast as the best-rated DDR memory modules.
The maximum capacity on commercially available DDR2 DIMMs is 8GB, but chipset support and availability for those DIMMs is sparse and more common 2GB per DIMM are used.{{Citation needed|date=June 2019}}<ref>https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/modules/parity_rdimm/htf36c256_512_1gx72pz.pdf?rev=e8e3928f09794d61809f92abf36bfb24 {{Bare URL PDF|date=March 2022}}</ref>

== History ==
DDR2 SDRAM was first produced by [[Samsung]] in 2001. In 2003, the [[JEDEC]] standards organization presented Samsung with its Technical Recognition Award for the company's efforts in developing and standardizing DDR2.<ref name="phys">{{cite news |title=Samsung Demonstrates World's First DDR 3 Memory Prototype |url=https://phys.org/news/2005-02-samsung-world-ddr-memory-prototype.html |access-date=23 June 2019 |work=[[Phys.org]] |date=17 February 2005 |language=en-us}}</ref>

DDR2 was officially introduced in the second quarter of 2003 at two initial clock rates: 200&nbsp;MHz (referred to as PC2-3200) and 266&nbsp;MHz (PC2-4200). Both performed worse than the original DDR specification due to higher latency, which made total access times longer. However, the original DDR technology tops out at a clock rate around 200&nbsp;MHz (400 MT/s). Higher performance DDR chips exist, but JEDEC has stated that they will not be standardized. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance, unless bandwidth dependent tasks such as integrated graphics rendering are used. DDR2 started to become competitive against the older DDR standard by the end of 2004, as modules with lower latencies became available.<ref>{{cite web |url=http://www.xbitlabs.com/articles/memory/display/ddr2-ddr.html |title=DDR2 vs. DDR: Revenge gained |author=Ilya Gavrichenkov |publisher=X-bit Laboratories |url-status=dead |archive-url=https://web.archive.org/web/20061121045622/http://www.xbitlabs.com/articles/memory/display/ddr2-ddr.html |archive-date=2006-11-21 }}</ref>

== Specification ==

=== Overview ===
[[File:Samsung-1GB-DDR2-Laptop-RAM.jpg|thumb|PC2-5300 DDR2 SO-DIMM (for notebooks)]]
[[Image:Desktop_DDR_Memory_Comparison.svg|thumb|right|Comparison of memory modules for desktop PCs (DIMM)]]
[[Image:Laptop_SODIMM_DDR_Memory_Comparison_V2.svg|thumb|right|Comparison of memory modules for portable/mobile PCs (SO-DIMM)]]

The key difference between DDR2 and DDR SDRAM is the increase in prefetch length. In DDR SDRAM, the prefetch length is two bits for every bit in a word; whereas it is four bits in DDR2 SDRAM. During an access, four bits are read or written to or from a four-bit-deep prefetch queue. This queue receives or transmitts its data over the data bus in two data bus clock cycles (each clock cycle transferrs two bits of data). Increasing the prefetch length allowed DDR2 SDRAM to double the rate at which data can be transferred over the data bus without a corresponding doubling in the rate at which the DRAM array can be accessed. DDR2 SDRAM is designed with such a scheme to avoid an excessive increase in power consumption.

DDR2's bus frequency is boosted by electrical interface improvements, [[on-die termination]], [[prefetch buffer]]s and off-chip drivers. However, [[memory latency|latency]] is greatly increased as a trade-off. The DDR2 prefetch buffer is four&nbsp;bits deep, whereas it is two&nbsp;bits deep for DDR. While DDR SDRAM has typical read latencies of between two and three bus cycles, DDR2 may have read latencies between three and nine cycles, although the typical range is between four and six. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency.

Another cost of the increased bandwidth is the requirement that the chips are packaged in a more expensive and difficult to assemble [[Ball grid array|BGA]] package as compared to the [[TSSOP]] package of the previous memory generations such as [[DDR SDRAM]] and [[SDR SDRAM]].  This packaging change was necessary to maintain signal integrity at higher bus speeds.

Power savings are achieved primarily due to an improved manufacturing process through die shrinkage, resulting in a drop in operating voltage (1.8&nbsp;V compared to DDR's 2.5&nbsp;V). The lower memory clock frequency may also enable power reductions in applications that do not require the highest available data rates.

According to JEDEC<ref>[http://www.jedec.org/download/search/JESD208.pdf JEDEC JESD 208] (section 5, tables 15 and 16)</ref> the maximum recommended voltage is 1.9 volts and should be considered the absolute maximum when memory stability is an issue (such as in servers or other mission critical devices). In addition, JEDEC states that memory modules must withstand up to 2.3 volts before incurring permanent damage (although they may not actually function correctly at that level).

=== Chips and modules ===
For use in computers, DDR2 SDRAM is supplied in [[DIMM]]s with 240 pins and a single locating notch. Laptop DDR2 [[SO-DIMM]]s have 200 pins and often come identified by an additional '''S''' in their designation. DIMMs are identified by their peak transfer capacity (often called bandwidth).

{| class="wikitable sortable"
|+ Comparison of DDR2 SDRAM standards

! colspan="3" scope="col" | Name
! colspan="2" scope="col" | [[Chip (computing)|Chip]]
! colspan="3" scope="col" | [[Bus (computing)|Bus]]
! colspan="2" scope="col" | [[Memory timings|Timings]]

|-
! scope="col" | Standard
! scope="col" | Type
! scope="col" | Module
! scope="col" |[[Clock rate]] {{Small|([[MHz]])}}
! scope="col" | Cycle time {{Small|([[Nanosecond|ns]])}}<ref>Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100&nbsp;MHz) = 10&nbsp;ns per clock cycle.</ref>
! scope="col" | Clock rate {{Small|(MHz)}}
! scope="col" | [[Transfer (computing)|Transfer rate]] {{Small|(MT/s)}}
! scope="col" | [[Bandwidth (computing)|Bandwidth]] <small>([[MB/s]])</small>
! scope="col" | CL-T{{Sub|RCD}}-T{{Sub|RP}}<ref>{{cite journal |date=April 2008 |title=DDR2 SDRAM SPECIFICATION |version=JESD79-2E |publisher=[[JEDEC]] |pages=78 |url=http://www.jedec.org/download/search/JESD79-2E.pdf |access-date=2009-03-14 }}</ref><ref>{{cite journal |date=November 2007 |title=SPECIALITY DDR2-1066 SDRAM |publisher=[[JEDEC]] |pages=70 |url=http://www.jedec.org/download/search/JESD208.pdf |access-date=2009-03-14 }}</ref>
! scope="col" | [[CAS latency]] {{Small|(ns)}}

|-
! rowspan="2" scope="row" | DDR2-400
| scope="row" | B
| rowspan="2" | PC2-3200
| rowspan="2" | 100
| rowspan="2" | 10
| rowspan="2" | 200
| rowspan="2" | 400
| rowspan="2" | 3200
| 3-3-3
| 15

|-
| scope="row" | C
| 4-4-4
| 20

|-
! rowspan="2" scope="row" | DDR2-533
| scope="row" | B
| rowspan="2" | PC2-4200*
| rowspan="2" | 133
| rowspan="2" | 7.5
| rowspan="2" | 266
| rowspan="2" | 533
| rowspan="2" | 4266
| 3-3-3
| 11.25

|-
| scope="row" | C
| 4-4-4
| 12

|-
! rowspan="2" scope="row" | DDR2-667
| scope="row" | C
| rowspan="2" | PC2-5300*
| rowspan="2" | 166
| rowspan="2" | 6 
| rowspan="2" | 333
| rowspan="2" | 667
| rowspan="2" | 5333
| 4-4-4
| 12

|-
| scope="row" | D
| 5-5-5
| 12 or 15

|-
! rowspan="3" scope="row" | DDR2-800
| scope="row" | C
| rowspan="3" | PC2-6400
| rowspan="3" | 200
| rowspan="3" | 5
| rowspan="3" | 400
| rowspan="3" | 800
| rowspan="3" | 6400
| 4-4-4 
| 10

|-
| scope="row" | D
| 5-5-5
| 12.5

|-
| scope="row" | E
| 6-6-6
| 12 or 15

|-
! rowspan="3" scope="row" | DDR2-1066
| scope="row" | D
| rowspan="3" | PC2-8500*
| rowspan="3" | 266
| rowspan="3" | 3.75
| rowspan="3" | 533
| rowspan="3" | 1066
| rowspan="3" | 8533
| 5-5-5
| 9.375

|-
| scope="row" | E
| 6-6-6
| 11.25

|-
| scope="row" | F
| 7-7-7
| 13.125
|}

{|class="wikitable floatright" style="text-align:center;"
|+ Relative speed comparison between similar modules
! rowspan="2" |
! colspan="2" | PC-5300
! colspan="3" | PC-6400
|-
! 5-5-5
! 4-4-4
! 6-6-6
! 5-5-5
! 4-4-4
|-
|| PC2-3200 4-4-4 || % || % || +33% || +60% || % 
|-
|| PC2-3200 3-3-3 || % || % || = || +20% || % 
|-
|| PC2-4200 4-4-4 || % || % || = || +21% || % 
|-
|| PC2-4200 3-3-3 || % || % || −24% || −9% || % 
|-
|| PC2-5300 5-5-5 || % || % || = || +21% || %
|-
|| PC2-5300 4-4-4 || % || % || −19% || −3% || % 
|-
|| PC2-6400 6-6-6 || % || % || = || +20% || % 
|-
|| PC2-6400 5-5-5 || % || % || −16% || = || % 
|-
|| PC2-6400 4-4-4 || % || % || −33% || −20% || % 
|-
|| PC2-8500 7-7-7 || % || % || −12% || +6% || % 
|-
|| PC2-8500 6-6-6 || % || % || −25% || −9% || % 
|-
|| PC2-8500 5-5-5 || % || % || −37% || −24% || % 
|}
<nowiki>*</nowiki> ''Some manufacturers label their DDR2 modules as PC2-4300, PC2-5400 or PC2-8600 instead of the respective names suggested by JEDEC. At least one manufacturer has reported this reflects successful testing at a higher-than-standard data rate<ref>[http://www.metku.net/index.html?path=reviews/ddr2_1/index_eng Mushkin PC2-5300 vs. Corsair PC2-5400]</ref> whilst others simply round up for the name.''

'''Note:''' DDR2-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC2-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

[[File:DDR2 F 'Fully Buffer' vs 'Parity' notch position.jpg|alt=DDR2 P vs F Server DIMM's Notch Positions compared|thumb|left|DDR2 '''P''' vs '''F''' ''Server'' DIMM's Notch Positions compared]]
In addition to bandwidth and capacity variants, modules can:

# Optionally implement [[ECC memory|ECC]], which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC in their designation. PC2-4200&nbsp;ECC is a PC2-4200 module with ECC. An additional ''P'' can be added at the end of the designation, P standing for parity (ex : PC2-5300P).
# [[File:Intel ® 6402 Advanced Memory Buffer..jpg|alt=Intel ® 6402 Advanced Memory Buffer|thumb|Intel ® 6402 Advanced Memory Buffer]]Be "registered" ("buffered"), which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals at a cost of an extra clock of increased latency. Those modules are identified by an additional '''R''' in their designation, whereas non-registered (a.k.a. "[[Unbuffered memory|unbuffered]]") RAM ''may be'' identified by an additional '''U''' in the designation.  PC2-4200R is a registered PC2-4200 module, PC2-4200R&nbsp;ECC is the same module but with additional ECC. 
# Be aware [[Fully Buffered DIMM|fully buffered]] modules, which are designated by '''F''' or '''FB''' do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.

'''Note:''' 
* Registered and un-buffered SDRAM generally cannot be mixed on the same channel.
* The highest-rated DDR2 modules in 2009 operate at 533&nbsp;MHz (1066&nbsp;MT/s), compared to the highest-rated DDR modules operating at 200&nbsp;MHz (400&nbsp;MT/s). At the same time, the CAS latency of 11.2&nbsp;ns = 6&nbsp;/&nbsp;(bus&nbsp;clock&nbsp;rate) for the best PC2-8500 modules is comparable to that of 10&nbsp;ns = 4&nbsp;/&nbsp;(bus&nbsp;clock&nbsp;rate) for the best PC-3200 modules.

=== Backward compatibility ===
DDR2 DIMMs are not backward compatible with DDR DIMMs. The notch on DDR2 DIMMs is in a different position from DDR DIMMs, and the pin density is higher than DDR DIMMs in desktops. DDR2 is a 240-pin module, DDR is a 184-pin module. Notebooks have 200-pin SO-DIMMs for DDR and DDR2; however, the notch on DDR2 modules is in a slightly different position than on DDR modules.

Higher-speed DDR2 DIMMs can be mixed with lower-speed DDR2 DIMMs, although the memory controller will operate all DIMMs at same speed as the lowest-speed DIMM present.

== Relation to GDDR memory ==
GDDR2, a form of [[GDDR SDRAM]], was developed by [[Samsung]] and introduced in July 2002.<ref>{{cite news |title=Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-announces-jedec-compliant-256mb-gddr2-for-3d-graphics/ |access-date=26 June 2019 |work=[[Samsung Electronics]] |publisher=[[Samsung]] |date=23 August 2003}}</ref> The first commercial product to claim using the "DDR2" technology was the [[Nvidia]] [[GeForce FX|GeForce FX 5800]] graphics card. However, this GDDR2 memory used on graphics cards is not DDR2 per se, but rather an early midpoint between DDR and DDR2 technologies. Using "DDR2" to refer to GDDR2 is a [[colloquialism|colloquial]] [[misnomer]]. In particular, the performance-enhancing doubling of the I/O clock rate is missing. It had severe overheating issues due to the nominal DDR voltages. [[ATI Technologies|ATI]] has since designed the GDDR technology further into [[GDDR3]], which is based on DDR2 SDRAM, though with several additions suited for graphics cards.

[[GDDR3]] was commonly used in graphics cards and some tablet PCs. However, further confusion has been added to the mix with the appearance of budget and mid-range graphics cards which claim to use "GDDR2". These cards actually use standard DDR2 chips designed for use as main system memory although operating with higher latencies to achieve higher clock rates. These chips cannot achieve the clock rates of GDDR3 but are inexpensive and fast enough to be used as memory on mid-range cards.
<!--From DDR2 SDRAM on 2009-09-02 07:12 -->

== See also ==
* [[DDR SDRAM]]
* [[CAS latency]] (definition of "CAS 5-5-5-15", for example)
* [[Dual-channel architecture]]
* [[Fully Buffered DIMM]]
* [[SO-DIMM]]
* [[Registered memory]]
* [[List of interface bit rates]]
* [[DDR3 SDRAM]]

== References ==
{{Reflist}}

== Further reading ==
* [http://www.jedec.org/standards-documents JEDEC standard: DDR2 SDRAM Specification: JESD79-2F, November 2009] ** http://www.jedec.org/standards-documents/docs/jesd-79-2e
* [http://www.jedec.org/standards-documents JEDEC standard: DDR2-1066] **
* [http://www.jedec.org/standards-documents "JEDEC Standard No. 21C: 4.20.13 240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification"] **
* [[JEDEC]] Solid State Technology Association
* {{cite magazine
|url=http://www.eetasia.com/ARTICLES/2006OCT/PDF/EEOL_2006OCT16_INTD_STOR_TA.pdf
|title=DDR2 SDRAM interfaces for next-gen systems
|author=Razak Mohammed Ali
|magazine=Electronic Engineering Times
|url-status=dead
|archive-url=https://web.archive.org/web/20070926215646/http://www.eetasia.com/ARTICLES/2006OCT/PDF/EEOL_2006OCT16_INTD_STOR_TA.pdf
|archive-date=2007-09-26
}}

Note**: JEDEC website requires registration ($2,500 membership) for viewing or downloading of these documents: http://www.jedec.org/standards-documents

== External links ==
* [http://www.jedec.org JEDEC website]
* [https://web.archive.org/web/20090106043029/http://www.lostcircuits.com/mambo/index.php?option=com_content&task=view&id=35&Itemid=60 Overview of DDR-II technology] 
* [https://web.archive.org/web/20070216022756/http://www.xbitlabs.com/articles/memory/display/core2duo-memory-guide.html DDR2 low latency vs high bandwidth, Core 2 Duo (Conroe) performance]

{{DRAM}}

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