Editing DDR SDRAM

{{short description|Type of computer memory}}
{{about|DDR SDRAM|graphics DDR|GDDR SDRAM{{!}}GDDR}}
{{Memory types}}
{{Infobox
| title            = DDR SDRAM<br />{{Small|Double Data Rate Synchronous Dynamic Random-Access Memory}}
| image            = [[Image:Desktop DDR Memory Comparison.svg|frameless]]
| caption          = Comparison of DDR modules for desktop PCs (DIMM)
| image2           = [[Image:1GB DDR1 400Mhz (8).jpg|frameless]]
| caption2         = Front and back of a 1GB DDR-400 RAM module for desktop PCs (DIMM)
| label1           = Developer
| data1            = {{ubl|[[Samsung]]<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref><ref name="samsung98">{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |publisher=[[Samsung]] |date=17 September 1998}}</ref><ref name="phys"/>|[[JEDEC]]}}
| label2           = Type
| data2            = [[Synchronous dynamic random-access memory]]
| label3           = Generations
| data3            = {{Unbulleted list|[[DDR2 SDRAM|DDR2]]|[[DDR3]]|[[DDR4]]|[[DDR5]]}}
| label4           = Release date
| data4            = {{Unbulleted list|'''DDR:''' {{start date and age|1998}}|'''DDR2:''' {{start date and age|2003}}|'''DDR3:''' {{start date and age|2007}}|'''DDR4:''' {{start date and age|2014}}|'''DDR5:''' {{start date and age|2020}}}}
| header5          = Specifications
| label6           = [[Voltage]]
| data6            = {{Unbulleted list|'''DDR:''' 2.5/2.6|'''DDR2:''' 1.8|'''DDR3:''' 1.5/1.35|'''DDR4:''' 1.2/1.05|'''DDR5:''' 1.1}}
}}

'''Double Data Rate Synchronous Dynamic Random-Access Memory''' ('''DDR SDRAM''') is a [[double data rate]] (DDR) [[synchronous dynamic random-access memory]] (SDRAM) class of memory [[integrated circuit]]s used in [[computer]]s. DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by [[DDR2 SDRAM]], [[DDR3 SDRAM]], [[DDR4 SDRAM]] and [[DDR5 SDRAM]]. None of its successors are [[Forward compatibility|forward]] or [[Backward compatibility|backward compatible]] with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 [[memory module]]s will not work on DDR1-equipped [[motherboard]]s, and vice versa.

Compared to single data rate ([[Synchronous dynamic random-access memory#SDR|SDR]]) SDRAM, the DDR SDRAM [[External memory interface|interface]] makes higher transfer rates possible through more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as [[phase-locked loop]]s and self-calibration to reach the required timing accuracy.<ref>[http://www.nwlogic.com/docs/ASIC_DDR_PHY.pdf Northwest Logic DDR Phy datasheet] {{webarchive|url=https://web.archive.org/web/20080821101233/http://www.nwlogic.com/docs/ASIC_DDR_PHY.pdf |date=2008-08-21 }}</ref><ref>{{cite web|url=http://www.xilinx.com/support/documentation/application_notes/xapp701.pdf|title=Memory Interfaces Data Capture Using Direct Clocking Technique (Xilinx application note)|website=xilinx.com}}</ref> The interface uses [[double data rate|double pumping]] (transferring data on both the rising and falling edges of the [[clock signal]]) to double [[data bus]] bandwidth without a corresponding increase in clock frequency. One advantage of keeping the clock frequency low is that it reduces the [[signal integrity]] requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the [[bandwidth (computing)|bandwidth]] of a SDR SDRAM running at the same clock frequency, due to this double pumping.

With data being transferred 64 [[bit]]s at a time, DDR SDRAM gives a transfer rate (in bytes/s) of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100&nbsp;MHz, DDR SDRAM gives a maximum transfer rate of 1600&nbsp;[[MB/s]].

== History ==
[[File:SAMSUNG@DDR-SDRAM@64MBit@K4D62323HA-QC60 Stack-DSC03491-DSC03518 - ZS-DMap.jpg|left|thumb|A Samsung DDR SDRAM 64&nbsp;Mbit chip]]

In the late 1980s [[IBM]] had built DRAMs using a [[double data rate|dual-edge clocking]] feature and presented their results at the International Solid-State Circuits Convention in 1990. However, it was standard [[DRAM]], not [[SDRAM]].<ref>{{cite book |first1=B. |last1=Jacob |first2=S. W. |last2=Ng |first3=D. T. |last3=Wang | title=Memory Systems: Cache, DRAM, Disk | year=2008 | publisher=Morgan Kaufmann | page=333 | isbn=9780080553849 | url=https://books.google.com/books?id=SrP3aWed-esC}}</ref><ref>{{cite journal |first1=H. L. |last1=Kalter |first2=C. H. |last2=Stapper |first3=J. E. |last3=Barth |first4=J. |last4=Dilorenzo |first5=C. E. |last5=Drake |first6=J. A. |last6=Fifield |first7=G. A. |last7=Kelley |first8=S. C. |last8=Lewis |first9=W. B. |last9=van der Hoeven |first10=J. A. |last10=Jankosky | title=A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC | year=1990 | journal=IEEE Journal of Solid-State Circuits | volume=25 | issue=5| page=1118 | doi=10.1109/4.62132 | bibcode=1990IJSSC..25.1118K }}</ref>

[[Samsung]] demonstrated the first DDR SDRAM memory prototype in 1997,<ref name="techpowerup">{{cite web |title=Samsung 30 nm Green PC3-12800 Low Profile 1.35 V DDR3 Review |url=https://www.techpowerup.com/review/samsung-mv-3v4g3/ |website=TechPowerUp |access-date=25 June 2019 |date= March 8, 2012}}</ref> and released the first commercial DDR SDRAM chip (64{{nbsp}}[[Megabit|Mbit]]) in June 1998,<ref name="samsung99">{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019  |publisher=[[Samsung]] |date=10 February 1999}}</ref><ref name="samsung98">{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |publisher=[[Samsung]] |date=17 September 1998}}</ref><ref name="phys">{{cite news |title=Samsung Demonstrates World's First DDR 3 Memory Prototype |url=https://phys.org/news/2005-02-samsung-world-ddr-memory-prototype.html |access-date=23 June 2019 |work=[[Phys.org]] |date=17 February 2005 |language=en-us}}</ref> followed soon after by [[Hyundai Electronics]] (now [[SK Hynix]]) the same year.<ref name="hynix90s">{{cite web |title=History: 1990s |url=https://www.skhynix.com/eng/about/history1990.jsp |website=[[SK Hynix]] |access-date=6 July 2019 |archive-date=5 February 2021 |archive-url=https://web.archive.org/web/20210205032928/https://www.skhynix.com/eng/about/history1990.jsp |url-status=dead }}</ref> The development of DDR began in 1996, before its specification was finalized by [[JEDEC]] in June 2000 (JESD79).<ref>{{cite web | url = http://www.design-reuse.com/articles/13805/the-love-hate-relationship-with-ddr-sdram-controllers.html | title = The Love/Hate Relationship with DDR SDRAM Controllers}}</ref> JEDEC has set standards for the data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. The first retail PC motherboard using DDR SDRAM was released in August 2000.<ref name="iwill">{{Cite web|url=http://www.pcstats.com/releaseview.cfm?releaseID=317|title=Iwill Reveals First DDR Motherboard |website=PCStats.com|access-date=2019-09-09|archive-date=2016-11-07|archive-url=https://web.archive.org/web/20161107084737/http://www.pcstats.com/releaseview.cfm?releaseID=317|url-status=dead}}</ref>

== Specification ==
[[File:Generic DDR Memory (Xytram).jpg|thumb|Single generic DDR memory module]]
[[File:4 slots DDR.JPG|thumb|Four DDR RAM slots]]
[[File:Corsair CMX512-3200C2PT 20080602.jpg|thumb|[[Corsair Gaming|Corsair]] DDR-400 memory with [[heat spreader]]s]]
[[File:DDR layout sketch.png|thumb|Physical DDR layout]]
[[File:Laptop SODIMM DDR Memory Comparison V2.svg|thumb|Comparison of memory modules for portable/mobile PCs ([[SO-DIMM]])]]

=== Modules ===
To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with common address lines are called a [[memory rank]]. The term was introduced to avoid confusion with chip internal '''rows''' and '''banks'''. A memory module may bear more than one rank. The term '''sides''' would also be confusing because it incorrectly suggests the physical placement of chips on the module. All ranks are connected to the same memory bus (address + data). The [[chip select]] signal is used to issue commands to specific rank.

Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the [[Von Neumann architecture#Von Neumann bottleneck|memory bottleneck]], new [[chipsets]] employ the [[dual-channel|multi-channel]] architecture.

{|class="wikitable" style="text-align:center;"
|+ Comparison of DDR SDRAM standards

! colspan="3" scope="col" | Name
! colspan="2" scope="col" | [[Chip (computing)|Chip]]
! colspan="3" scope="col" | [[Bus (computing)|Bus]]
! colspan="2" scope="col" | [[Memory timings|Timings]]
! rowspan="2" scope="col" | [[Voltage]]<br>{{Small|([[Volt|V]])}}

|- style="line-height:133%"
! scope="col" | Standard
! scope="col" | Type
! scope="col" | Module
! scope="col" |[[Clock rate]]<br>{{Small|([[MHz]])}}
! scope="col" | Cycle time<br>{{Small|([[Nanosecond|ns]])}}<ref>Cycle time is the inverse of the I/O bus clock frequency; e.g., 1/(100&nbsp;MHz) = 10&nbsp;ns per clock cycle.</ref>
! scope="col" | Clock rate<br>{{Small|(MHz)}}
! scope="col" | [[Transfer (computing)|Transfer rate]]<br>{{Small|(MT/s)}}
! scope="col" | [[Bandwidth (computing)|Bandwidth]]<br><small>([[MB/s]])</small>
! scope="col" | CL-T{{Sub|RCD}}-<br>T{{Sub|RP}}
! scope="col" | [[CAS latency]]<br>{{Small|(ns)}}

|-
! colspan="2" scope="row" | DDR-200
| PC-1600
| 100
| 10
| 100 
| 200
| 1600
| 2-2-2
| 20
| rowspan="3" | 2.5±0.2

|-
! colspan="2" scope="row" | DDR-266
| PC-2100
| {{frac|133|1|3}}
| 7.5
| {{frac|133|1|3}}
| {{Fraction|266|2|3}}
| {{frac|2133|1|3}}
| 2.5-3-3
| 18.75
|-
! colspan="2" scope="row" | DDR-333
| PC-2700
| {{frac|166|2|3}}
| 6
| {{frac|166|2|3}}
| {{frac|333|1|3}}
| {{frac|2666|2|3}}
| 2.5-3-3
| 15

|-
! rowspan="3" scope="row" | DDR-400
! A
| rowspan="3" | PC-3200
| rowspan="3" | 200
| rowspan="3" | 5
| rowspan="3" | 200
| rowspan="3" | 400
| rowspan="3" | 3200
| 2.5-3-3
| 12.5
| rowspan="3" | 2.6±0.1

|-
! B
| 3-3-3
| 15
|-
! C
| 3-4-4
| 15
|}

'''Note:''' All items listed above are specified by [[JEDEC]] as JESD79F.<ref>{{cite web|url=http://www.jedec.org/standards-documents/docs/jesd-79f|title=DOUBLE DATA RATE (DDR) SDRAM STANDARD - JEDEC|website=www.jedec.org}}</ref> All RAM data rates in-between or above these listed specifications are not standardized by JEDEC – often they are simply manufacturer optimizations using tighter tolerances or overvolted chips. The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM modules. Modules are instead designed to run at different clock frequencies: for example, a PC-1600 module is designed to run at {{nowrap|100 MHz}}, and a PC-2100 is designed to run at {{nowrap|133 MHz}}. A module's clock speed designates the data rate at which it is guaranteed to perform, hence it is guaranteed to run at lower (''[[underclocking]]'') and can possibly run at higher (''[[overclocking]]'') clock rates than those for which it was made.<ref>{{Cite web|url=http://www.crucial.com/support/memory_speeds.aspx|title=What is the difference between PC-2100 (DDR-266), PC-2700 (DDR-333), and PC-3200 (DDR-400)?|publisher=Micron Technology|access-date=2009-06-01|archive-url=https://web.archive.org/web/20131203004412/http://www.crucial.com/support/memory_speeds.aspx|archive-date=2013-12-03|url-status=dead}}</ref>

DDR SDRAM modules for desktop computers, [[DIMM|dual in-line memory modules (DIMMs)]], have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, [[SO-DIMM]]s, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of a correct match. Most DDR SDRAM operates at a voltage of 2.5&nbsp;V, compared to 3.3&nbsp;V for SDRAM. This can significantly reduce power consumption. Chips and modules with the DDR-400/PC-3200 standard have a nominal voltage of 2.6&nbsp;V.

JEDEC Standard No. 21–C defines three possible operating voltages for 184 pin DDR, as identified by the key notch position relative to its centreline. Page 4.5.10-7 defines 2.5V (left), 1.8V (centre), TBD (right), while page 4.20.5–40 nominates 3.3V for the right notch position. The orientation of the module for determining the key notch position is with 52 contact positions to the left and 40 contact positions to the right.

Increasing the operating voltage slightly can increase maximum speed but at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage.

;Capacity
;Number of DRAM devices: The number of chips is a multiple of 8 for non-[[Error-correcting code|ECC]] modules and a multiple of 9 for ECC modules. Chips can occupy one side (''single sided'') or both sides (''dual sided'') of the module. The maximal number of chips per DDR module is 36 (9×4) for ECC and 32 (8x4) for non-ECC.
;ECC vs non-ECC: Modules that have [[Error detection and correction#Error-correcting memory|error-correcting code]] are labeled as [[dynamic random-access memory#Error detection and correction|ECC]].  Modules without error correcting code are labeled '''non-ECC'''.
;Timings: [[CAS latency]] (CL), clock cycle time (t<sub>CK</sub>), row cycle time (t<sub>RC</sub>), refresh row cycle time (t<sub>RFC</sub>), row active time (t<sub>RAS</sub>).
;Buffering: [[Registered memory|Registered]] (or buffered) vs [[Unbuffered memory|unbuffered]].
;Packaging: Typically [[DIMM]] or [[SO-DIMM]].
;Power consumption: A test with DDR and DDR2 RAM in 2005 found that average power consumption appeared to be of the [[Order of magnitude|order]] of 1–3&nbsp;W per 512&nbsp;MB module; this increases with clock rate and when in use rather than idling.<ref>[http://www.silentpcreview.com/article265-page4.html Mike Chin: Power Distribution within Six PCs].</ref><!--Out of order and from 2003, but very useful <ref>http://www.overclockers.com/articles696/ {{Dead link|date=February 2022}}</ref>--> A manufacturer has produced calculators to estimate the power used by various types of RAM.<ref>[https://www.micron.com/support/power-calc Micron: System Power Calculators] {{webarchive|url=https://web.archive.org/web/20160126211816/https://www.micron.com/support/power-calc |date=2016-01-26 }}</ref>

Module and chip characteristics are inherently linked.

Total module capacity is a product of one chip's capacity and the number of chips. ECC modules multiply it by {{frac|8|9}} because they use 1&nbsp;bit per byte (8&nbsp;bits) for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip and number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently, a module with a greater number of chips or using ×8 chips instead of ×4 will have more ranks.

{| class="wikitable floatright"
|+ Example: Variations of 1&nbsp;GB PC2100 registered DDR SDRAM module with ECC
! Module<br>size
! Number<br>of chips
! Chip<br>size
! Chip<br>organization
! Number<br>of ranks
|-
| 1 GB
| 36
| 256
| {{0}}64M×4 MBit
| 2
|-
| 1 GB
| 18
| 512
| {{0}}64M×8 MBit
| 2
|-
| 1 GB
| 18
| 512
| 128M×4 MBit
| 1
|}

This example compares different real-world server memory modules with a common size of 1&nbsp;GB. One should definitely be careful buying 1&nbsp;GB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single- or dual-ranked.

There is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can also find 2-side/1-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it is unlikely such a module was ever produced.

=== Chip characteristics ===
[[File:SAMSUNG@DDR-SDRAM@64MBit@K4D62323HA-QC60 Stack-DSC03539-DSC03556 - ZS-DMap.jpg|thumb|The [[die (integrated circuit)|die]] of a Samsung DDR-SDRAM 64MBit package]]
;DRAM density: Size of the chip is measured in [[megabits]]. Most motherboards recognize only 1&nbsp;GB modules if they contain ''64M×8'' chips (''low density''). If ''128M×4'' (''high density'') 1&nbsp;GB modules are used, they most likely will not work. The [[JEDEC]] standard allows ''128M×4'' only for registered modules designed specifically for servers, but some generic manufacturers do not comply.<ref>{{cite web|url=http://reviews.ebay.com/Myth-Low-Density-vs-High-Density-memory-modules_W0QQugidZ10000000001236178|title=Low Density vs High Density memory modules|website=eBay|access-date=2009-01-21|archive-date=2012-03-03|archive-url=https://web.archive.org/web/20120303072655/http://reviews.ebay.com/Myth-Low-Density-vs-High-Density-memory-modules_W0QQugidZ10000000001236178|url-status=dead}}</ref><ref>{{cite web |title=Vostro 230, 4GB max incorrect, explanation |url=https://www.dell.com/community/en/conversations/vostro-desktops/vostro-230-4gb-max-incorrect-explanation/647f8052f4ccf8a8deefdb84 |website=DELL Technologies |language=en |date=10 April 2019}}</ref>
;Organization: The notation like ''64M×4'' means that the memory matrix has 64 million (the product of ''banks'' x ''rows'' x ''columns'') 4-bit storage locations. There are ''×4, ×8,'' and ''×16'' DDR chips. The ''×4'' chips allow the use of advanced error correction features like [[Chipkill]], [[memory scrubbing]] and Intel SDDC in server environments, while the ''×8'' and ''×16'' chips are somewhat less expensive. ''x8'' chips are mainly used in desktops/notebooks but are making an entry into the server market. There are normally 4 banks and only one row can be active in each bank.

==== Double data rate (DDR) SDRAM specification ====
From Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics.

Standard No. 79 Revision Log:
*Release 1, June 2000
*Release 2, May 2002
*Release C, March 2003 – JEDEC Standard No. 79C.<ref>http://www.jedec.org/download/search/JESD79F.pdf DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION (Release F)</ref>

"This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well."

=== Organization ===
PC3200 is DDR SDRAM designed to operate at 200&nbsp;MHz using DDR-400 chips with a bandwidth of 3,200&nbsp;MB/s. Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400&nbsp;MHz.

1&nbsp;GB PC3200 non-ECC modules are usually made with 16 512&nbsp;Mbit chips, 8 on each side (512&nbsp;Mbits × 16&nbsp;chips) / (8 bits (per byte)) = 1,024&nbsp;MB. The individual chips making up a 1&nbsp;GB memory module are usually organized as 2<sup>26</sup> 8-bit words, commonly expressed as 64M×8. Memory manufactured in this way is low-density RAM and is usually compatible with any motherboard specifying PC3200 DDR-400 memory.<ref>{{Cite web|url=https://superuser.com/questions/138800/per-bytes-ram-memory-acess|title=Per bytes RAM memory access|website=Super User|access-date=2018-10-21}}</ref>{{Citation needed|date=October 2010}}

== Generations ==
DDR (DDR1) was superseded by [[DDR2 SDRAM]], which had modifications for a higher clock frequency and again doubled throughput, but operates on the same principle as DDR. Competing with DDR2 was [[Rambus]] [[XDR DRAM]]. DDR2 dominated due to cost and support factors. DDR2 was in turn superseded by [[DDR3 SDRAM]], which offered higher performance for increased bus speeds and new features. DDR3 has been superseded by [[DDR4 SDRAM]], which was first produced in 2011 and whose standards were still in flux (2012) with significant architectural changes.

DDR's prefetch buffer depth is 2 (bits), while DDR2 uses 4. Although the effective clock rates of DDR2 are higher than DDR, the overall performance was not greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.<ref>[http://www.xbitlabs.com/articles/memory/display/ddr2-ddr.html DDR2 vs. DDR: Revenge Gained] {{webarchive|url=https://web.archive.org/web/20061121045622/http://www.xbitlabs.com/articles/memory/display/ddr2-ddr.html |date=2006-11-21 }}</ref>

Memory manufacturers stated that it was impractical to mass produce DDR1 memory with effective transfer rates in excess of 400&nbsp;MHz (i.e. 400&nbsp;MT/s and 200&nbsp;MHz external clock) due to internal speed limitations. DDR2 picks up where DDR1 leaves off, utilizing internal clock rates similar to DDR1, but is available at effective transfer rates of 400&nbsp;MHz and higher. DDR3 advances extended the ability to preserve internal clock rates while providing higher effective transfer rates by again doubling the prefetch depth.

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as 16 banks, 4 bank groups with 4 banks for each bank group for ×4/×8 and 8 banks, 2 bank groups with 4 banks for each bank group for ×16 DRAM.
The DDR4 SDRAM uses an 8''n'' prefetch architecture to achieve high-speed operation. The 8''n'' prefetch architecture is combined with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8''n''-bit-wide 4-clock data transfer at the internal DRAM core and 8 corresponding ''n''-bit-wide half-clock-cycle data transfers at the I/O pins.<ref>{{cite web|title=DDR4 SDRAM Standard JESD79-4B|url=https://www.jedec.org}}</ref>

[[RDRAM]] was a particularly expensive alternative to DDR SDRAM, and most manufacturers dropped its support from their chipsets. DDR1 memory's prices substantially increased from Q2 2008, while DDR2 prices declined. In January 2009, 1&nbsp;GB DDR1 was 2–3 times more expensive than 1&nbsp;GB DDR2. {{citation needed|date=December 2017}}

{| class="wikitable sortable" style="text-align: center;"
|+ {{anchor|Comparison}} Comparison of DDR SDRAM generations
! colspan="2" scope="col" | Name
! rowspan="2" scope="col" | Release<br />year
! colspan="3" scope="col" | [[Chip (computing)|Chip]]
! colspan="3" scope="col" | [[Bus (computing)|Bus]]
! rowspan="2" scope="col" | [[Voltage]]<br />(V)
! colspan="3" scope="col" | Pins
|-
! scope="col" | Gen
! scope="col" | Standard
! scope="col" | [[Clock rate]]<br />(MHz)
! scope="col" | Cycle time<br />(ns)
! scope="col" | [[Prefetch buffer|Pre-<br />fetch]]
! scope="col" | Clock rate<br />(MHz)
! scope="col" | [[Transfer (computing)|Transfer rate]]<br />([[MT/s]])
! scope="col" | [[Bandwidth (computing)|Bandwidth]]<br />(MB/s)
! scope="col" | [[DIMM]]
! scope="col" | [[SO-DIMM|SO-<br />DIMM]]
! scope="col" | [[MicroDIMM|Micro-<br />DIMM]]
|-
! rowspan="4" scope="row" | DDR
!DDR-200
| rowspan="4" | 1998
| 100
|10
| rowspan="4" | 2n
| 100
| 200
|1600
| rowspan="3" | 2.5
| rowspan="4" | 184
| rowspan="4" | 200
| rowspan="4" | 172
|-
!DDR-266
|133
|7.5
|133
|266
|{{frac|2133|1|3}}
|-
!DDR-333
|{{frac|166|2|3}}
|6
|{{frac|166|2|3}}
|333
|{{frac|2666|2|3}}
|-
!DDR-400
|200
|5
|200
|400
|3200
|2.6
|-
! rowspan="5" scope="row" |[[DDR2 SDRAM|DDR2]]
!DDR2-400
| rowspan="5" | 2003
| 100
|10
| rowspan="5" | 4n
| 200
| 400
|3200
| rowspan="5" | 1.8
| rowspan="5" | 240
| rowspan="5" | 200
| rowspan="5" | 214
|-
!DDR2-533
|{{frac|133|1|3}}
|7.5
|{{frac|266|2|3}}
|{{frac|533|1|3}}
|{{frac|4266|2|3}}
|-
!DDR2-667
|{{frac|166|2|3}}
|6
|{{frac|333|1|3}}
|{{frac|666|2|3}}
|{{frac|5333|1|3}}
|-
!DDR2-800
|200
|5
|400
|800
|6400
|-
!DDR2-1066
|{{frac|266|2|3}}
|3.75
|{{frac|533|1|3}}
|{{frac|1066|2|3}}
|{{frac|8533|1|3}}
|-
! rowspan="6" scope="row" |[[DDR3 SDRAM|DDR3]]
!DDR3-800
| rowspan="6" | 2007
| 100
|10
| rowspan="6" | 8n
| 400
| 800
|6400
| rowspan="6" | 1.5/1.35
| rowspan="6" | 240
| rowspan="6" | 204
| rowspan="6" | 214
|-
!DDR3-1066
|{{frac|133|1|3}}
|7.5
|{{frac|533|1|3}}
|{{frac|1066|2|3}}
|{{frac|8533|1|3}}
|-
!DDR3-1333
|{{frac|166|2|3}}
|6
|{{frac|666|2|3}}
|{{frac|1333|1|3}}
|{{frac|10600|2|3}}
|-
!DDR3-1600
|200
|5
|800
|1600
|12800
|-
!DDR3-1866
|{{frac|233|1|3}}
|4.29
|{{frac|933|1|3}}
|{{frac|1866|2|3}}
|{{frac|14933|1|3}}
|-
!DDR3-2133
|{{frac|266|2|3}}
|3.75
|{{frac|1066|2|3}}
|{{frac|2133|1|3}}
|{{frac|17066|2|3}}
|-
! rowspan="7" scope="row" |[[DDR4 SDRAM|DDR4]]
!DDR4-1600
| rowspan="7" | 2014
| 200
|5
| rowspan="7" | 8n
| 800
| 1600
|12800
| rowspan="7" | 1.2/1.05
| rowspan="7" | 288
| rowspan="7" | 260
| rowspan="7" |-
|-
!DDR4-1866
|{{frac|233|1|3}}
|4.29
|{{frac|933|1|3}}
|{{frac|1866|2|3}}
|{{frac|14933|1|3}}
|-
!DDR4-2133
|{{frac|266|2|3}}
|3.75
|{{frac|1066|2|3}}
|{{frac|2133|1|3}}
|{{frac|17066|2|3}}
|-
!DDR4-2400
|300
|{{frac|3|1|3}}
|1200
|2400
|19200
|-
!DDR4-2666
|{{frac|333|1|3}}
|3
|{{frac|1333|1|3}}
|{{frac|2666|2|3}}
|{{frac|21333|1|3}}
|-
!DDR4-2933
|{{frac|366|2|3}}
|2.73
|{{frac|1466|2|3}}
|{{frac|2933|1|3}}
|{{frac|23466|2|3}}
|-
!DDR4-3200
|400
|2.5
|1600
|3200
|25600
|-
! rowspan="10" |[[DDR5 SDRAM|DDR5]]
!DDR5-3200
| rowspan="10" |2020
|200
|5
| rowspan="10" |16n
|1600
|3200
|25600
| rowspan="10" |1.1
| rowspan="10" |288
| rowspan="10" |262
| rowspan="10" |
|-
!DDR5-3600
|225
|4.44
|1800
|3600
|28800
|-
!DDR5-4000
|250
|4
|2000
|4000
|32000
|-
!DDR5-4800
|300
|{{frac|3|1|3}}
|2400
|4800
|38400
|-
!DDR5-5000
|{{frac|312|1|2}}
|3.2
|2500
|5000
|40000
|-
!DDR5-5120
|320
|{{frac|3|1|8}}
|2560
|5120
|40960
|-
!DDR5-5333
|{{frac|333|1|3}}
|3
|{{frac|2666|2|3}}
|{{frac|5333|1|3}}
|{{frac|42666|2|3}}
|-
!DDR5-5600
|350
|2.86
|2800
|5600
|44800
|-
!DDR5-6400
|400
|2.5
|3200
|6400
|51200
|-
!DDR5-7200
|450
|2.22
|3600
|7200
|57600
|}

=== LPDDR ===
{{Main|LPDDR}}
LPDDR is an acronym that some enterprises use for [[LPDDR]] SDRAM, a type of memory used in some portable electronic devices, like [[mobile phone]]s, [[handheld]]s, and [[digital audio player]]s. Through techniques including reduced voltage supply and advanced refresh options, [[LPDDR]] can achieve greater power efficiency.

== See also ==
* [[Fully Buffered DIMM]]
* [[ECC memory]], a type of computer data storage 
* [[List of interface bit rates]]
* [[Serial presence detect]]

== References ==
{{Reflist}}

== External links ==

{{DRAM}}

{{DEFAULTSORT:Ddr Sdram}}
[[Category:SDRAM]]
[[Category:JEDEC standards]]
[[Category:South Korean inventions]]

[[el:Μνήμη τυχαίας προσπέλασης#Τύποι μνήμης RAM]]
[[fi:DRAM#DDR SDRAM]]