Editing DLX

{{Short description|RISC processor architecture}}
{{About|the CPU architecture}}
{{Infobox CPU architecture
| name       = DLX
| designer   = [[John L. Hennessy]] and [[David A. Patterson (scientist)|David A. Patterson]]
| bits       = 32-bit
| introduced = 1994
| version    = 1.0
| design     = RISC
| type       = [[Load–store architecture|Load–store]]
| encoding   = Fixed
| branching  = Condition register
| endianness = [[Bi-endian]]
| extensions = None, but [[MDMX]] & [[MIPS-3D]] could be used
| open       = Yes
| registers  = 
| gpr        = 32 (R0=0)
| fpr        = 32 (paired DP for 32-bit)
}}
The '''DLX''' (pronounced "Deluxe") is a [[Reduced instruction set computer|RISC]] [[Central processing unit|processor]] [[Computer architecture|architecture]] designed by [[John L. Hennessy]] and [[David Patterson (computer scientist)|David A. Patterson]], the principal designers of the [[Stanford MIPS]] and the [[Berkeley RISC]] designs (respectively), the two benchmark examples of RISC design (named after the Berkeley design).

The DLX is essentially a cleaned up (and modernized) simplified Stanford MIPS CPU. The DLX has a simple [[32-bit computing|32-bit]] load/store architecture, somewhat unlike the modern [[MIPS architecture]] CPU. As the DLX was intended primarily for teaching purposes, the DLX design is widely used in [[university]]-level computer architecture courses.

There are two known "[[Soft microprocessor|softcore]]" hardware implementations: ASPIDA and VAMP. The ASPIDA project resulted in a core with many nice features: it is open source, supports [[Wishbone (computer bus)|Wishbone]], has an asynchronous design, supports multiple [[Instruction set architecture|ISA]]s, and is [[ASIC]] proven. VAMP is a DLX-variant that was mathematically verified as part of Verisoft project. It was specified with [[Prototype Verification System|PVS]], implemented in [[Verilog]], and runs on a [[Xilinx]] [[FPGA]]. A full stack from compiler to kernel to [[TCP/IP]] was built on it.

==History==
In the Stanford MIPS architecture, one of the methods used to gain performance was to force all instructions to complete in one clock cycle. This forced compilers to insert "[[NOP (code)|no-ops]]" in cases where the instruction would definitely take longer than one clock cycle. Thus input and output activities (like memory accesses) specifically forced this behaviour, leading to artificial program bloat. In general, MIPS programs were forced to have a lot of wasteful NOP instructions, a behaviour that was an unintended consequence. The DLX architecture does not force single clock cycle execution, and is therefore immune to this problem.

In the DLX design, a more modern approach to handling long instructions was used: data-forwarding and instruction reordering. In this case, the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they can complete. Externally, this design behaviour makes it appear as if execution had occurred linearly.

==Instruction decoding==
DLX instructions can be broken down into three types, ''R-type'', ''I-type'' and ''J-type''. R-type instructions are pure ''register'' instructions, with three register references contained in the 32-bit word. I-type instructions specify two registers, and use 16 bits to hold an ''immediate'' value. Finally J-type instructions are ''jumps'', containing a 26-bit address.

[[Opcode]]s are 6 bits long, for a total of 64 possible basic instructions. To select one of 32 registers 5 bits are needed.
* In the case of R-type instructions this means that only 21 bits of the 32-bit word are used, which allows the lower 6 bits to be used as "extended instructions".
* The DLX can support more than 64 instructions, as long as those instructions work purely on registers. This quirk is useful for things like [[floating point unit|FPU]] support.

==Pipeline==
The DLX, like the MIPS design, bases its performance on the use of an [[instruction pipeline]]. In the DLX design this is a fairly simple one, [[Classic RISC pipeline|"classic" RISC]] in concept. The pipeline contains five stages:

;IF – Instruction Fetch unit/cycle
: IR<-Mem(PC)
: NPC<-PC+4
: Operation: Send out the PC and fetch the instruction from memory into the [[instruction register|Instruction Register (IR)]]; increment the PC by 4 to address the next sequential instruction. The IR is used to hold the next instruction that will be needed on subsequent clock cycles; likewise the register NPC is used to hold the next sequential PC.
;ID – Instruction Decode unit
: Operation: Decode the instruction and access the register file to read the registers. This unit gets instruction from IF, and extracts opcode and operand from that instruction. It also retrieves register values if requested by the operation.
;EX – Execution unit/effective address cycle 
: Operation: The [[Arithmetic logic unit|ALU]] operates on the operands prepared in prior cycle, performing one of the four functions depending on the DLX instruction type. 
: Memory Reference: Register–Register ALU instruction, Register–Immediate ALU instruction
: Branch
;MEM – Memory access unit
: The DLX instructions active in this unit are loads, stores and branches.
: Memory reference: access memory if needed. If instruction is load, data returns from memory and is placed in the LMD (load memory data) register
: Branch
;WB – WriteBack unit
: Typically referred to as "the store unit" in modern terminology. Write the result into the register file, whether it comes from the memory system or from the ALU.

==See also==
* [[Educational programming language]]
* [[Little Computer 3|LC-3]]
* [[MIX (abstract machine)|MIX]], [[MMIX]]
* [[MicroBlaze]]
* [[MikroSim]]
* [[OpenRISC]]

==References==
* {{cite book |last=Sailer |first=Philip M. |author2=Kaeli, David R. |authorlink2=David R. Kaeli |title=The DLX Instruction Set Architecture Handbook |year=1996 |publisher=Morgan Kaufmann|isbn=1-55860-371-9}}
* {{cite book|last1=Patterson|first1=David|authorlink1=David Patterson (scientist)|last2=Hennessy|first2=John|authorlink2=John L. Hennessy|title=Computer Architecture: A Quantitative Approach|year=1996|edition=1st|publisher=[[Morgan Kaufmann]]|isbn=978-1-55-860329-5|url=https://archive.org/details/computerarchitec00patt}}
* {{cite book|last1=Patterson|first1=David|authorlink1=David Patterson (scientist)|last2=Hennessy|first2=John|authorlink2=John L. Hennessy|title=Computer Organization and Design|year=1994|edition=1st|publisher=[[Morgan Kaufmann]]|isbn=978-1-55-860281-6|url=https://archive.org/details/computerorganiza00henn}}

==External links==
* [http://www.csee.umbc.edu/courses/undergraduate/411/spring96/dlx.html The DLX Processor]
* [http://www.eng.tau.ac.il/~guy/Computer_Structure03/slides/instructions.pdf DLX instructions]
* [https://web.archive.org/web/20080117091139/http://cs.uns.edu.ar/~jechaiz/arquitectura/windlx/windlx.html WinDLX]
* [http://www.davidviner.com/dlx.html DLX Simulator (GNU GPL)]
* [http://users.elis.ugent.be/escape/ ESCAPE DLX Simulator] {{Webarchive|url=https://web.archive.org/web/20150623110040/http://users.elis.ugent.be/escape/ |date=2015-06-23 }}
* [http://sourceforge.net/projects/opendlx/ openDLX - opensource DLX-Simulator in Java (GNU GPLv3)]
* [http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=F3092E4572A237F069257DFF168CB07A?doi=10.1.1.217.2251&rep=rep1&type=pdf Formal verification of VAMP processor]
* [http://opencores.org/project,aspida ASPIDA asynchronous DLX processor]
* [https://www.haverford.edu/computer-science/resources/hera HERA: The Haverford Educational RISC Architecture]

{{RISC-based processor architectures}}
{{Soft microprocessors}}

{{DEFAULTSORT:Dlx}}
[[Category:Instruction set architectures]]
[[Category:Soft microprocessors]]