Editing Differential TTL

'''Differential TTL''' is a type of binary [[electrical signal]]ing based on the [[transistor-transistor logic]] (TTL) concept. It enables electronic systems to be relatively immune to noise.<ref>{{cite journal
|title=A High-Speed Mixed Digital-to-Analog Circuit Board for Accurate Control of Wavelength Tunable Lasers for Fiber-Optic Communications
|author1=Paul D. Biernacki |author2=Michael Y. Frankel |author3=Michael E. Gingerich |author4=Paul J. Matthews
|journal=Journal of Lightwave Technology
|volume=17
|issue= 7
|year=1999
|page=1222
|doi=10.1109/50.774260
|bibcode=1999JLwT...17.1222B
|url=https://www.osapublishing.org/jlt/abstract.cfm?uri=jlt-17-7-1222
|url-access=subscription
}} 
</ref> [[RS-422]] and [[RS-485]] outputs can be implemented as differential TTL.<ref>{{cite web |title=B&B Electronics - Polarities for Differential Pair Signals (RS-422 and RS-485) |url=https://www.bb-elec.com/Learning-Center/All-White-Papers/Serial/%E2%80%A2-Polarities-for-Differential-Pair-Signals-%28RS-422.aspx |website=www.bb-elec.com}}</ref>

Normal TTL signals are [[single-ended signaling|single-ended]], which means that each signal consists of a voltage on one wire, referenced to a system [[Ground (electricity)|ground]].<ref>{{cite book
|title=Signal and Power Integrity in Digital Systems: TTL, CMOS, and BiCMOS
|year=1996
|isbn=0070087342
|url=https://books.google.com/books?id=6yRTAAAAMAAJ&q=single-ended+TTL-+or+CMOS-level+communication
|page=200|last1=Buchanan
|first1=James Edgar
|publisher=McGraw-Hill
}}</ref>  The "low" voltage level is zero to 0.8 volts, and the "high" voltage level is 2 volts to 5 volts.  A differential TTL signal consists of two such wires, also referenced to a system ground.  The [[logic level]] on one wire is always the complement of the other.  The principle is similar to that of [[low-voltage differential signaling]] (LVDS), but with different voltage levels.

Differential TTL is used in preference to single-ended TTL for long-distance signaling.<ref>{{cite book
|title=Exploring the World of SCSI
|year=2000
|author= Louis Columbus
|isbn=0790612100
|url=https://books.google.com/books?id=8HCQLfbnrwEC&pg=PA20
|page=20|publisher=LWC Research
}}</ref>  In a long cable, stray [[electromagnetic field]]s in the environment, or stray [[electric current|currents]] in the system ground, can induce unwanted voltages that cause errors at the receiver.  With a [[Differential signaling|differential pair]] of wires, roughly the same unwanted voltage is induced in each wire.  The receiver subtracts the voltages on the two wires, so that the unwanted voltage disappears, and only the voltage created by the driver remains.

A second advantage of differential TTL is that the differential pair of wires can form a current loop.<ref>{{cite book
|title=Interfacing PIC Microcontrollers: Embedded Design by Interactive Simulation
|year=2013
|author= Martin P. Bates
|isbn=978-0080993720
|url=https://books.google.com/books?id=cjyJ-hjat9QC&pg=PA200
|page=200|publisher=Newnes
}}</ref>  The driver sources a current from the power supply into one wire.  This current passes along the wire to the receiver, through the termination resistor and back up the other wire, then back through the driver and down to ground.  No net current is exchanged between the driver and receiver, which means that none of the signal current has to return through the ground connection (if there is one) between the two ends.  This arrangement prevents the signal from injecting currents into the ground connection, which might upset other circuits attached to it.

Differential TTL is the most common type of [[high-voltage differential signaling]] ([[HVDS]]).{{citation needed|date=December 2017}}

== Applications ==
Differential TTL signaling was used in the [[Serial Storage Architecture]] (SSA) standard devised by IBM,{{citation needed|date=December 2017}} but this is mostly obsolete.  More efficient signaling techniques such as [[LVDS]] are now used instead.

==See also==
*[[Differential signalling]]

==References==
{{reflist}}


[[Category:Logic families]]