Editing Direct digital synthesis

{{Short description|Method for creating waveforms}}
[[File:DDS function generator.jpg|thumb|250px|A DDS [[function generator]].]]
'''Direct digital synthesis''' ('''DDS''') is a method employed by [[frequency synthesizer]]s used for creating arbitrary [[waveform]]s from a single, fixed-frequency reference clock. DDS is used in applications such as [[signal generator|signal generation]], [[local oscillator]]s in communication systems, [[function generator]]s, mixers, [[modulator]]s,<ref name="AD_app"/> [[synthesizer|sound synthesizers]] and as part of a digital [[phase-locked loop]].<ref name="RFDesign July 2007"/>

==Overview==
[[File:Direct digital synthesizer block diagram.png|frame|Figure 1 - Direct Digital Synthesizer block diagram]]

A basic Direct Digital Synthesizer consists of a frequency reference (often a [[crystal oscillator|crystal]] or [[surface acoustic wave|SAW]] oscillator), a [[numerically controlled oscillator]] (NCO) and a [[digital-to-analog converter]] (DAC) {{#tag:ref|While some authors use the terms DDS and NCO interchangeably,<ref name="latticeSC" /> by convention an NCO refers to the digital (i.e. the discrete-time, discrete amplitude) portion of a DDS<ref>Jane Radatz, The IEEE Standard Dictionary of Electrical and Electronics Terms, IEEE Standards Office, New York, NY, 1997</ref>}} as shown in Figure 1.

The reference oscillator provides a stable time base for the system and determines the frequency accuracy of the DDS. It provides the clock to the ''NCO'', which produces at its output a discrete-time, [[Quantization (signal processing)|quantized]] version of the desired output waveform (often a [[Sine wave|sinusoid]]) whose period is controlled by the digital word contained in the ''Frequency Control Register''. The sampled, digital waveform is converted to an analog waveform by the ''DAC''. The output reconstruction filter rejects the spectral replicas produced by the [[zero-order hold]] inherent in the analog conversion process.

== Performance ==
A DDS has many advantages over its analog counterpart, the [[phase-locked loop]] (PLL), including much better frequency agility, improved [[phase noise]], and precise control of the output phase across frequency switching transitions. Disadvantages include spurious responses mainly due to truncation effects in the [[Numerically controlled oscillator|NCO]], crossing spurs resulting from high order (>1) Nyquist images, and a higher noise floor at large frequency offsets due mainly to the [[digital-to-analog converter]].<ref name="AD DDSvPLL"/>

Because a DDS is a [[Nyquist–Shannon sampling theorem|sampled system]], in addition to the desired waveform at output frequency F<sub>out</sub>, [[Nyquist frequency|Nyquist images]] are also generated (the primary image is at F<sub>clk</sub>-F<sub>out</sub>, where F<sub>clk</sub> is the reference clock frequency). In order to reject these undesired images, a DDS is generally used in conjunction with an analog [[reconstruction filter|reconstruction lowpass filter]] as shown in Figure 1.<ref>Kroupa, Venceslav F.,''Direct Digital Frequency Synthesizers'', IEEE Press, 1999, {{ISBN|0-7803-3438-8}}</ref>

=== Frequency agility ===
The output frequency of a DDS is determined by the value stored in the frequency control register (FCR) (see Fig.1), which in turn controls the [[Numerically controlled oscillator|NCO]]'s phase accumulator step size. Because the NCO operates in the discrete-time domain, it changes frequency instantaneously at the clock edge coincident with a change in the value stored in the FCR. The DDS output frequency settling time is determined mainly by the phase response of the reconstruction filter. An ideal reconstruction filter with a linear phase response (meaning the output is simply a delayed version of the input signal) would allow instantaneous frequency response at its output because a linear system can not create frequencies not present at its input.<ref name="Chen"/>

=== Phase noise and jitter ===

The superior close-in [[phase noise]] performance of a DDS stems from the fact that it is a feed-forward system. In a traditional [[phase locked loop]] (PLL), the [[frequency divider]] in the feedback path acts to multiply the phase noise of the reference oscillator and, within the PLL loop bandwidth, impresses this excess noise onto the VCO output. A DDS, on the other hand, reduces the reference clock phase noise by the ratio <math>f_{clk}/f_o</math> because the fractional division of the clock derives its output. Reference clock [[jitter]] translates directly to the output, but this jitter is a smaller percentage of the output period (by the ratio above). Since the maximum output frequency is limited to <math>f_{clk}/2</math>, the output phase noise at close-in offsets is always at least 6&nbsp;dB below the reference clock phase noise.<ref name="AD DDSvPLL"/>

At offsets far removed from the carrier, the phase-noise floor of a DDS is determined by the power sum of the DAC [[Quantization (signal processing)|quantization]] noise floor and the reference clock phase noise floor.

==See also==
*[[Crystal oscillator]]
*[[Digital synthesizer]]
*[[Digital-to-analog converter]]
*[[Numerically controlled oscillator]]
*[[Reconstruction filter]]
*[[Table-lookup synthesis]]
** Multiple [[wavetable synthesis]]

==References==
<references>
<ref name="latticeSC">{{cite web|title=Numerically Controlled Oscillator
  |url=http://www.latticesemi.com/products/intellectualproperty/ipcores/numericallycontrolledosci/index.cfm
  |publisher=Lattice Semiconductor Corporation|year=2009}}</ref>
<ref name="AD_app">{{cite web|title=DDS Controls Waveforms in Test, Measurement, and Communications|url=http://www.analog.com/library/analogdialogue/archives/39-08/dds_apps.html|publisher=[[Analog Devices]] Corporation}}</ref>
<ref name="RFDesign July 2007">{{cite web
   |title=Direct digital synthesis enables digital PLLs
   |url=http://rfdesign.com/mag/707RFDF2.pdf
   |author=Paul Kern
   |publisher=RFDesign
   |date=July 2007
   |access-date=2010-01-15
   |archive-date=2012-04-05
   |archive-url=https://web.archive.org/web/20120405200808/http://rfdesign.com/mag/707RFDF2.pdf
   |url-status=dead
   }}</ref>  
<ref name="AD DDSvPLL">{{cite web|title=Single-Chip Direct Digital Synthesis vs. the Analog PLL
    |url=http://www.analog.com/library/analogDialogue/archives/30-3/single_chip.html
    |publisher=[[Analog Devices]] Corporation}}</ref>
<ref name="Chen">{{cite book|title=Introduction to Linear System Theory|author=Chen, C.T.|publisher=Holt, Rinehart and Winston, Inc.|year=1970|isbn=978-0-03-077155-2|url-access=registration|url=https://archive.org/details/introductiontoli00chen}}</ref>
</references>

==External links and further reading==
*[http://www.ieee.li/pdf/essay/dds.pdf Tutorial on Digital Signal Synthesis] (From [[Analog Devices]])
*L. Cordesses, [http://lionel.cordesses.free.fr/gpages/DDS1.pdf "Direct Digital Synthesis: A Tool for Periodic Wave Generation (Part 1)"] ''IEEE Signal Processing Magazine, DSP Tips & Tricks column'', pp.&nbsp;50–54, Vol. 21, No. 4 July 2004.
*L. Cordesses, [http://lionel.cordesses.free.fr/gpages/DDS2.pdf Direct Digital Synthesis: A Tool for Periodic Wave Generation (Part 2)] ''IEEE Signal Processing Magazine, DSP Tips & Tricks column'', pp.&nbsp;110–117, Vol. 21, No. 5, Sep. 2004.
* {{cite book |title=Direct Digital Synthesizers: Theory, Design and Applications|series=The Kluwer international series in Engineering and Computer Science|author=Jouko Vankka & Kari A.I. Halonen|isbn=978-1-4419-4895-3|year=2010|publisher=Kluwer Academic Publishers|location=Boston, MA }}

{{DEFAULTSORT:Direct Digital Synthesizer}}
[[Category:Digital signal processing]]
[[Category:Electronic oscillators]]