Editing Double data rate

{{Short description|Method of computer bus operation}}
{{Use American English|date=September 2024}}

[[File:SDR DDR QDR.svg|thumb|A comparison between [[single data rate]], double data rate, and [[quad data rate]]. The dots are where data transfers take place, measured in millions of transfers per second (MT/s).]]

In [[computing]], '''double data rate''' ('''DDR''') describes a [[computer bus]] that transfers data on both the rising and falling edges of the [[clock signal]] and hence doubles the [[memory bandwidth]] by transferring data twice per clock cycle.<ref>{{cite book | url = https://books.google.com/books?id=pqYl3SWkA64C&pg=PA314 | isbn = 978-0-12-370490-0 | first1 = John L. | last1 = Hennessy | first2 = David A. | last2 = Patterson | year = 2007 | publisher = Morgan Kaufmann | location = Amsterdam | title = Computer architecture: a quantitative approach | page = 314}}</ref><ref name="Intel z434">{{cite web | title=double data rate (DDR) Definition | website=Intel | url=https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_ddr.htm | access-date=2024-04-07}}</ref>  This is also known as '''double pumped''', '''dual-pumped''', and '''double transition'''.  The term '''toggle mode'''<!--boldface per WP:R#PLA--> is used in the context of [[NAND flash memory]].

==Overview==
The simplest way to design a clocked [[electronic circuit]] is to make it perform one transfer per full cycle (rise and fall) of a [[clock signal]].  This, however, requires that the clock signal changes twice per transfer, while the data lines change at most once per transfer.  When operating at a high bandwidth, [[signal integrity]] limitations constrain the clock [[frequency]].{{citation needed|date=May 2021}}  By using both edges of the clock, the data signals operate with the same limiting frequency, thereby doubling the data transmission rate.

This technique has been used for microprocessor [[front-side bus]]ses, [[Parallel SCSI#Ultra-3|Ultra-3 SCSI]], expansion buses ([[Accelerated Graphics Port|AGP]], [[PCI-X]]<ref>{{cite web |last1=Schmid |first1=Patrick |title=PCI Express Battles PCI-X |url=https://www.tomshardware.com/reviews/pci-express-battles-pci,1176-2.html |website=Tom's Hardware Guide|date=23 November 2005 }}</ref>), graphics memory ([[GDDR]]), [[SDRAM|main memory]] (both [[RDRAM]] and [[DDR SDRAM|DDR1]] through [[DDR5]]), and the [[HyperTransport]] bus on [[AMD]]'s [[Athlon 64]] processors. It is more recently being used for other systems with high data transfer speed requirements{{spaced ndash}} as an example, for the output of [[analog-to-digital converter]]s (ADCs).<ref>{{cite web |title= AD9467 ADC | type = data sheet |url= http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf |publisher= Analog Devices}}</ref>

DDR should not be confused with [[Dual-channel architecture|dual channel]], in which each memory channel accesses two RAM modules simultaneously. The two technologies are independent of each other and many motherboards use both, by using DDR memory in a dual channel configuration.

An alternative to double or [[Quad data rate|quad pumping]] is to make the link [[self-clocking]]. This tactic was chosen by [[InfiniBand]] and [[PCI Express]].

== Relation of bandwidth and frequency ==
Describing the bandwidth of a double-pumped bus can be confusing.  Each clock edge is referred to as a ''[[beat (music)|beat]]'', with two beats (one [[Beat (music)#Downbeat and upbeat|upbeat]] and one [[Beat (music)#Downbeat|downbeat]]) per cycle.  Technically, the [[hertz]] is a unit of ''cycles'' per second, but many people refer to the number of ''transfers'' per second.  Careful usage generally talks about "500&nbsp;MHz, double data rate" or "1000&nbsp;[[MT/s]]", but many refer casually to a "1000&nbsp;MHz bus," even though no signal cycles faster than 500&nbsp;MHz.

[[DDR SDRAM]] popularized the technique of referring to the bus bandwidth in [[megabytes per second]], the product of the transfer rate and the bus width in bytes.  DDR SDRAM operating with a 100&nbsp;MHz clock is called DDR-200 (after its 200&nbsp;MT/s data transfer rate), and a 64-bit (8-byte) wide [[DIMM]] operated at that data rate is called PC-1600, after its 1600&nbsp;MB/s peak (theoretical) bandwidth.  Likewise, 12.8&nbsp;GB/s transfer rate DDR3-1600 is called PC3-12800.

Some examples of popular designations of DDR modules:
{| class="wikitable"
|-
! Names !! Memory clock !! I/O bus clock !! [[Transfer (computing)|Transfer rate]] !! Theoretical bandwidth
|-
| DDR-200, PC-1600
| 100&nbsp;MHz <!--Divide by 2 for DDR1-->
| 100&nbsp;MHz
| 200 MT/s
| 1.6 GB/s
|-
| DDR-400, PC-3200
| 200&nbsp;MHz <!--Divide by 2 for DDR1-->
| 200&nbsp;MHz
| 400 MT/s
| 3.2 GB/s
|-bgcolor=white
| DDR2-800, PC2-6400
| 200&nbsp;MHz <!--Divide by 4 for DDR2-->
| 400&nbsp;MHz
| 800 MT/s
| 6.4 GB/s
|-
| DDR3-1600, PC3-12800
| 200&nbsp;MHz <!--Divide by 8 for DDR3-->
| 800&nbsp;MHz
| 1600 MT/s
| 12.8 GB/s
|-bgcolor=white
|DDR4-2400, PC4-19200
| 300&nbsp;MHz <!--DDR4 remains 8n prefetch, so divide by 8 for DDR4-->
| 1200&nbsp;MHz
| 2400 MT/s
| 19.2 GB/s
|-bgcolor=white
| DDR4-3200, PC4-25600
| 400&nbsp;MHz <!--DDR4 remains 8n prefetch, so divide by 8 for DDR4-->
| 1600&nbsp;MHz
| 3200 MT/s
| 25.6 GB/s
|-
|DDR5-4800, PC5-38400
| 300&nbsp;MHz <!--Divide by 16 for DDR5-->
| 2400&nbsp;MHz
| 4800 MT/s
| 38.4 GB/s <!--Using both buses; DDR5 provides two independent buses per DIMM-->
|-
| DDR5-6400, PC5-51200
| 400&nbsp;MHz
| 3200&nbsp;MHz
| 6400 MT/s
| 51.2 GB/s
|}

DDR SDRAM uses double-data-rate signalling only on the data lines. Address and control signals are still sent to the DRAM once per clock ''cycle'' (to be precise, on the rising edge of the clock), and timing parameters such as [[CAS latency]] are specified in clock cycles. Some less common DRAM interfaces, notably [[LPDDR2]], [[GDDR5]] and [[XDR DRAM]], send commands and addresses using double data rate.  [[DDR5]] uses two 7-bit double data rate command/address buses to each DIMM, where a [[Registered memory|registered]] clock driver chip converts to a 14-bit SDR bus to each memory chip.

== See also ==
* [[DDR SDRAM]], [[DDR2 SDRAM]], [[DDR3 SDRAM]], [[DDR4 SDRAM]] and [[DDR5 SDRAM]]
* [[GDDR SDRAM]], [[GDDR3 SDRAM]], [[GDDR4 SDRAM]], [[GDDR5 SDRAM]] and [[GDDR6 SDRAM]]
* [[List of interface bit rates]]
* [[Pumping (computer systems)]]
* [[Quad data rate]]

== References ==
{{Reflist}}

[[Category:Digital electronics]]
[[Category:Clock signal]]