Editing Emitter-coupled logic

{{Short description|Integrated circuit logic family}}
{{Use mdy dates|date=September 2023}}
{{Use American English|date=September 2023}}
[[Image:ECL.svg|350px|thumb|right|Motorola ECL 10,000 basic [[OR gate|OR/NOR gate]] circuit diagram from 1972.<ref>Original drawing based on {{cite book |first=William R. |last=Blood Jr. |date=1972 |title=MECL System Design Handbook |edition=2nd  |publisher=Motorola Semiconductor Products |page=1 |url=http://www.bitsavers.org/components/motorola/_dataBooks/1972_Motorola_MECL_System_Design_Handbook_2ed.pdf |via=Bitsavers}}</ref>{{r|p=5|TND309}} Note the Q5 and Q6 emitters coupled to the output and the [[Emitter-coupled logic#power supply|negative-power supply]].{{efn|Motorolla ECL devices run off of a negative power supply. This "reversed" arrangement used to avoid noise that might be induced to the collector and emitter lines. It also had very unusual logic levels (see [[#logic_levels_comparison|comparison]]): -1.75 V for LOW (0) and -0.9 V for HIGH (1).{{r|p=5|TND309}} It was possible to design circuits by using ECL with positive sources (see PECL - Positive ECL).{{r|p=18|TND309}} }}<ref>{{Cite book |url=https://www.onsemi.com/download/application-notes/pdf/an1406-d.pdf |title=Designing with PECL (ECL at +5.0V), The High Speed Solution for the CMOS/TTL Designer |date=September 1999 |publisher=Onsemi |edition=2 }}</ref> ]]

In electronics, '''emitter-coupled logic''' ('''ECL''') is a high-speed [[integrated circuit]] bipolar transistor [[logic family]]. ECL uses a [[bipolar junction transistor]] (BJT) [[differential amplifier]] with single-ended input and limited emitter current to avoid the [[Bipolar junction transistor#Regions of operation|saturated]] (fully on) region of operation and the resulting slow turn-off behavior.<ref name = "unitd04">
{{cite web
 | url = http://www.physics.dcu.ie/~bl/digi/unitd04.pdf
 | work = Fundamental Digital Electronics
 | first = Brian |last=Lawless
 | title = Unit4: ECL Emitter Coupled Logic
 }}</ref>
As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called ''current-steering logic'' (CSL),<ref>
{{cite book
 | title = Pulse and Digital Circuits
 | first = Anand |last=Kumar
 | publisher = PHI Learning
 | year = 2008
 | isbn = 978-81-203-3356-7
 | page = 472
 | url = https://books.google.com/books?id=ECeObhzCiLIC&pg=RA2-PA472
}}</ref>
''current-mode logic'' (CML)<ref>
{{cite book
 | title = Digital Logic Techniques: Principles and Practice
 | first = T. J. |last=Stonham
 | publisher = Taylor & Francis
 | year = 1996
 | isbn = 978-0-412-54970-0
 | page = 173
 | url = https://books.google.com/books?id=UE6vFEnGP2kC&pg=PA173
}}</ref>
or ''current-switch emitter-follower'' (CSEF) logic.<ref>
{{cite book
 | title = Fundamentals of Microsystems Packaging
 | first = Rao R. |last=Tummala
 | publisher = McGraw-Hill
 | year = 2001
 | pages = 930
 | url = https://books.google.com/books?id=P93ZrOWHlO0C&pg=PA930
 | isbn = 978-0-07-137169-8
 }}</ref>

In ECL, the transistors are never in saturation, the input and output voltages have a small swing (0.8 V), the input impedance is high and the output impedance is low. As a result, the transistors change states quickly, [[gate delay]]s are low, and the [[fanout]] capability is high.<ref>
{{cite book
 | title = The Forrest Mims Circuit Scrapbook
 | volume = 2
 | first = Forrest M. |last=Mims
 | author-link = Forrest Mims
 | publisher = Newnes
 | year = 2000
 | isbn = 978-1-878707-48-2
 | page = 115
 | url = https://books.google.com/books?id=STzitya5iwgC&pg=PA115
 }}</ref> In addition, the essentially constant current draw of the differential amplifiers minimizes delays and [[Glitch#Electronics_glitch|glitches]] due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count.

ECL's major disadvantage is that each gate continuously draws current, which means that it requires (and dissipates) significantly more power than those of other logic families, especially when quiescent.

The equivalent of emitter-coupled logic made from [[field-effect transistor|FETs]] is called [[source-coupled logic]] (SCFL).<ref>
{{cite book
 | title = Gallium Arsenide IC Applications Handbook
 | first1 = Dennis |last1=Fisher |first2=I.J. |last2=Bahl
 | publisher = Elsevier
 | year = 1995
 | isbn = 978-0-12-257735-2
 | page = 61
 | url = https://books.google.com/books?id=KSKJ56kvcSYC&pg=PA61
 | volume = 1
 }}</ref>

A variation of ECL in which all signal paths and gate inputs are differential is known as differential current switch (DCS) logic.<ref>
{{cite journal
 | first1 = E.B. |last1=Eichelberger |first2=S.E. |last2=Bello
 | date = May 1991
 | title = Differential Current Switch – High performance at low power
 | journal = IBM Journal of Research and Development
 | volume = 35
 | issue = 3
 | pages = 313–320
 | url = http://domino.watson.ibm.com/tchjr/journalindex.nsf/0/af4fa2f7f17243c485256bfa0067fab9?OpenDocument
 | doi = 10.1147/rd.353.0313
 | url-access = subscription
 }}</ref>

== History ==
[[Image:CurrentSwitchLogic.svg|350px|thumb|right|Yourke's current switch (around 1955)<ref name="Rymaszewski"/>]]

ECL was invented in August 1956 at [[IBM]] by Hannon S. Yourke.<ref>[http://semiconductormuseum.com/Transistors/IBM/OralHistories/Yourke/Yourke_Index.htm Early Transistor History at IBM].</ref><ref>{{Citation |url=http://archive.computerhistory.org/resources/text/IBM/Stretch/pdfs/06-11/102634289.pdf |title=Millimicrosecond non-saturating transistor switching circuits |first=Hannon S. |last=Yourke |id=Stretch Circuit Memo # 3 |date=October 1956 }}. Yourke's circuits used commercial transistors and had an average gate delay of 12&nbsp;ns.</ref> Originally called ''current-steering logic'', it was used in the [[IBM 7030 Stretch|Stretch]], [[IBM 7090]], and [[IBM 7090#IBM 7094 and IBM 7040/7044|IBM 7094]] computers.<ref name="Rymaszewski">{{cite journal |author=E. J. Rymaszewski |year=1981 |title=Semiconductor Logic Technology in IBM |journal=IBM Journal of Research and Development |volume=25 |issue=5 |pages=607–608 |issn=0018-8646 |url=http://researchweb.watson.ibm.com/journal/rd/255/ibmrd2505W.pdf |access-date=August 27, 2007 |doi=10.1147/rd.255.0603 |display-authors=etal |url-status=dead |archive-url=https://web.archive.org/web/20080705164759/http://researchweb.watson.ibm.com/journal/rd/255/ibmrd2505W.pdf |archive-date=July 5, 2008 }}</ref>  The logic was also called a current-mode circuit.<ref>{{cite book |title=High-Speed Switching Transistor Handbook |editor-first=William D. |editor-last=Roehr |editor2-first=Darrell |editor2-last=Thorpe |year=1963 |publisher=Motorola |url=https://archive.org/details/High-speedSwitchingHandbook }}, p. 37.</ref>  It was also used to make the IBM Advanced [[Solid Logic Technology]] (ASLT) circuits in the IBM 360/91.<ref>{{cite book |title=IBM's 360 and Early 370 Systems |page=108 |date=2003 |isbn=0262517205|last1=Pugh |first1=Emerson W. |last2=Johnson |first2=Lyle R. |last3=Palmer |first3=John H. |publisher=MIT Press }}</ref><ref name="ASLT">{{cite journal |year=1967 |title=Design of a High-Speed Transistor for the ASLT Current Switch |journal=IBM Journal of Research and Development |first1=J.L. |last1=Langdon |first2=E.J. |last2=VanDerveer |volume=11 |pages=69–73 |url=http://www.research.ibm.com/journal/rd/111/ibmrd1101G.pdf |doi=10.1147/rd.111.0069 }}</ref><ref name=Blocks>{{cite web|title=Logic Blocks Automated Logic Diagrams SLT, SLD, ASLT, MST |url=http://bitsavers.trailing-edge.com/pdf/ibm/logic/SY22-2798-2_LogicBlocks_AutomatedLogicDiagrams_SLT,SLD,ASLT,MST_TO_Oct71.pdf|publisher=IBM|access-date=September 11, 2015|pages=1–10 |via=Bitsavers}}</ref>

Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level."<ref>{{Harvnb|Roehr|Thorpe|1963|p=39}}</ref> In Yourke's design, the two logic reference levels differed by 3&nbsp;volts.<!-- This would keep the collector to base capacitance small and improve switching speed. Roehr page 40 advises keeping a minimum Vcb of at least 2V -- that's a typical design goal to minimize effect of Ccb, but Roehr does not actually state it is for Ccb. --> Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."<ref name="Rymaszewski"/>

Instead of alternating NPN and PNP stages, another coupling method employed [[Zener diode]]s and resistors to shift the output logic levels to be the same as the input logic levels.<ref>{{Harvnb|Roehr|Thorpe|1963|pp=40, 261}}</ref>

Beginning in the early 1960s, ECL circuits were implemented on [[monolithic integrated circuit]]s. They consisted of a differential-amplifier input stage to perform logic followed by an emitter-follower stage to drive outputs and shift the output voltages so they will be compatible with the inputs. The emitter-follower output stages could also be used to perform [[Wired logic connection|wired-or logic]].

{{anchor|MECL}}[[Motorola]] introduced their first digital monolithic integrated circuit line, MECL I, in 1962.<ref>{{cite book |first=William R. |last=Blood Jr. |date=1988 |orig-year=1980 |url=http://www.onsemi.com/pub/Collateral/HB205-D.PDF |title=MECL System Design Handbook |edition=4th |publisher=Motorola Semiconductor Products, republished by On Semiconductor|page=vi |archive-url=https://web.archive.org/web/20041010110305/http://www.onsemi.com/pub/Collateral/HB205-D.PDF |archive-date=October 10, 2004}}</ref> Motorola developed several improved series, with MECL II in 1966, MECL III in 1968 with 1-nanosecond gate propagation time and 300&nbsp;MHz flip-flop toggle rates, and the 10,000 series (with lower power consumption and controlled edge speeds) in 1971.<ref>{{cite book |first=William R. |last=Blood Jr. |title=MECL System Design Handbook |edition=1st |date=October 1971 |publisher=Motorola  |pages=vi–vii |url=http://www.bitsavers.org/components/motorola/_dataBooks/1971_Motorola_MECL_System_Design_Handbook_1ed_Oct71.pdf |via=Bitsavers}}</ref>
The MECL 10H family was introduced in 1981.<ref name="TND309">{{cite book
|url=http://www.onsemi.com/pub_link/Collateral/TND309-D.PDF |title=TND309: General Information for MECL 10H and MECL 10K
|date=2002 |publisher=ON Semiconductor: Semiconductor Components Industries |id=TND309/D
|page=2
|archive-url=https://web.archive.org/web/20150708060625/http://www.onsemi.com/pub_link/Collateral/TND309-D.PDF |archive-date=July 8, 2015
}}</ref>
Fairchild introduced the F100K family in 1975.<ref>{{cite journal |last1=Hively |first1=J. W. |last2=Muller |first2=H. H. |last3=Owens |first3=W. K. |title=F100K, A Standard Family of Subnanosecond ECL |journal=Fairchild Journal of Semiconductor Progress |volume=3 |issue=3 |pages=16-21 |url=https://www.computerhistory.org/collections/catalog/102798005 |access-date=30 October 2024}}</ref><ref>{{cite web |title=Thomas A. Longo: Department of Physics and Astronomy: Purdue University |url=https://www.physics.purdue.edu/alumni/distalum/longo.html |website=www.physics.purdue.edu}}</ref>

The ECLinPS ("ECL in picoseconds") family was introduced in 1987.<ref>{{cite book |first=Anil K. |last=Maini |url=https://books.google.com/books?id=Ljsr7UA83ScC |title=Digital Electronics: Principles, Devices and Applications
|date=2007 |page=148|publisher=John Wiley & Sons |isbn=9780470510513 }}</ref> ECLinPS has 500 ps single-gate delay and 1.1&nbsp;GHz flip-flop toggle frequency.<ref>{{Cite FTP |url=ftp://ece.buap.mx/pub/manuales/High%20Performace%20ECL%20Data.pdf |title=High Performance ECL Data: ECLinPS and ECLinPS Lite |date=1996 |server=FTP server |url-status=dead |page=iii }}</ref> The ECLinPS family parts are available from multiple sources, including Arizona Microtek, Micrel (subsequently acquired by Microchip Technology Inc.), National Semiconductor, and ON Semiconductor.<ref>
[http://www.interfacebus.com/ECL_Logic_Manufacturers.html ECL Logic Manufacturers – "Emitter Coupled Logic"].
</ref>

The high power consumption of ECL meant that it has been used mainly when high speed is a vital requirement. Older high-end mainframe computers, such as the [[IBM ES/9000 family|Enterprise System/9000]] members of IBM's [[ESA/390]] computer family, used ECL,<ref name=barish/> as did the [[Cray-1]],<ref name="Russell">{{cite journal |first=R.M. |last=Russell |year=1978 |title=The CRAY1 computer system|journal=Communications of the ACM |volume=21 |issue=1 |pages=63–72 |url=http://www.eecg.toronto.edu/~moshovos/ACA05/read/cray1.pdf
|access-date=April 27, 2010 |doi=10.1145/359327.359336 |s2cid=28752186 }}</ref> and first-generation [[Amdahl Corporation|Amdahl]] mainframes. (Current IBM mainframes use [[CMOS]].<ref>{{cite web|url=http://www.redbooks.ibm.com/redpieces/pdfs/sg248050.pdf |title=IBM zEnterprise System Technical Introduction |date=August 1, 2013 |url-status=dead |archive-url=https://web.archive.org/web/20131103060023/http://www.redbooks.ibm.com/redpieces/pdfs/sg248050.pdf |archive-date=November 3, 2013 }}</ref>) Beginning in 1975, [[Digital Equipment Corporation]]'s highest performance processors were all based on multi-chip ECL CPUs—from the ECL [[PDP-10|KL10]] through the ECL [[VAX 8000]] and finally the [[VAX 9000]]. By 1991, the CMOS [[NVAX]] was launched, which offered comparable performance to the VAX 9000 despite costing 1/25 as much and consuming considerably less power.<ref>
{{cite web |first=Bob |last=Supnik 
|url=http://simh.trailing-edge.com/semi/raven.html |title=Raven: Introduction: The ECL Conundrum |quote=Raven was started in 1988... Raven was a simplified VAX design with a single chip CPU and a single chip FPU. Implemented in Fujitsu's ECL standard cells, it was intended to run at 250Mhz and deliver 50 "VUPS" ... Power dissipation would have been a startling (for the day) 150W. }}
</ref> The [[R6000|MIPS R6000]] computers also used ECL. Some of these computer designs used ECL [[gate array]]s.

==Implementation==
[[Image:ECL structure 1000.jpg|right|thumb|350px|The picture represents a typical ECL circuit diagram based on Motorola's MECL. In this schematic, transistor T5′ represents the output transistor of a previous ECL gate that provides a logic signal to input transistor T1 of an OR/NOR gate whose other input is at T2 and has outputs Y and {{overline|Y}}. Additional pictures illustrate the circuit operation by visualizing the voltage relief and current topology at [[:Image:ECL logical0 1000.jpg|low input voltage]] (logical "0"), [[:Image:ECL transition 1000.jpg|during the transition]] and at [[:Image:ECL logical1 1000.jpg|high input voltage]] (logical "1").]]

ECL is based on an emitter-coupled ([[Differential amplifier#Long-tailed pair|long-tailed]]) pair, shaded red in the figure on the right. The left half of the pair (shaded yellow) consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic. The base voltage of the right transistor T3 is held fixed by a reference voltage source, shaded light green: the voltage divider with a diode thermal compensation (R1, R2, D1 and D2) and sometimes a buffering emitter follower (not shown on the picture); thus the emitter voltages are kept relatively steady. As a result, the common emitter resistor R<sub>E</sub> acts nearly as a [[current source]]. The output voltages at the collector load resistors R<sub>C1</sub> and R<sub>C3</sub> are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5 (shaded blue). The output emitter resistors R<sub>E4</sub> and R<sub>E5</sub> do not exist in all versions of ECL. In some cases 50&nbsp;Ω line termination resistors connected between the bases of the input transistors and −2&nbsp;V of a driven gate act as emitter resistors of the driving gate.<ref>{{harvnb|Blood Jr.|1972|p=3}}</ref>

== Operation ==

The ECL circuit operation is considered below with assumption that the input voltage is applied to T1 base, while T2 input is unused or a logical "0" is applied.

[[:Image:ECL transition 1000.jpg|During the transition]], the core of the circuit – the emitter-coupled pair (T1 and T3) – acts as a differential amplifier with single-ended input. The long-tail current source (R<sub>E</sub>) sets the total current flowing through the two legs of the pair. The input voltage controls the current flowing through the transistors by sharing it between the two legs, steering it all to one side when not near the switching point. The gain is higher than at the end states (see below) and the circuit switches quickly.

[[:Image:ECL logical0 1000.jpg|At low input voltage]] (logical "0") or [[:Image:ECL logical1 1000.jpg|at high input voltage]] (logical "1") the differential amplifier is overdriven. The transistor (T1 or T3) is cutoff and the other (T3 or T1) is in active linear region acting as a [[Common emitter#Emitter degeneration|common-emitter stage with emitter degeneration]] that takes all the current, starving the other cutoff transistor.<br>The active transistor is loaded with the relatively high emitter resistance ''R''<sub>E</sub> that introduces a significant negative feedback (emitter degeneration). To prevent saturation of the active transistor so that the diffusion time that slows the recovery from saturation will not be involved in the logic delay,<ref name = "unitd04" /> the emitter and collector resistances are chosen such that at maximum input voltage some voltage is left across the transistor. The residual gain is low (''K''&nbsp;=&nbsp;''R''<sub>C</sub>/''R''<sub>E</sub>&nbsp;&lt;&nbsp;1). The circuit is insensitive to the input voltage variations and the transistor stays firmly in active linear region. The input resistance is high because of the series negative feedback.<br> The cutoff transistor breaks the connection between its input and output. As a result, its input voltage does not affect the output voltage. The input resistance is high again since the base-emitter junction is cutoff.

== Characteristics ==

Other noteworthy characteristics of the ECL family include the fact that the large current requirement is approximately constant, and does not depend significantly on the state of the circuit.  This means that ECL circuits generate relatively little power noise, unlike other logic types which draw more current when switching than quiescent. In cryptographic applications, ECL circuits are also less susceptible to [[side channel attack]]s such as [[differential power analysis]].{{citation needed|date=December 2018}}

The [[propagation delay|propagation time]] for this arrangement can be less than a nanosecond, including the signal delay getting on and off the IC package. Some type of ECL has always been the fastest logic family.<ref>John F. Wakerly. Supplement to Digital Design Principles and Practices. Section [http://www.ddpp.com/DDPP4student/Supplementary_sections/ECL.pdf "ECL: Emitter-Coupled Logic"].
</ref><ref>{{cite book |last1=Sedra |last2=Smith |title=Microelectronic Circuits |date=2015 |chapter-url=http://global.oup.com/us/companion.websites/fdscontent/uscompanion/us/static/companion.websites/9780199339136/pdf/Additional_Material.pdf |chapter=Emitter-Coupled Logic (ECL) |page=47 |publisher=Oxford University Press |isbn=978-0-19-933913-6}}</ref>

[[Radiation hardening]]:  While normal commercial-grade chips can withstand 100 [[Gray (unit)|gray]] (10 krad),  many ECL devices are operational after 100,000 gray (10 Mrad).<ref name="verkasalo">{{cite web| title = Protection of Instrument Control Computers against Soft and Hard Errors and Cosmic Ray Effects | url=https://www.researchgate.net/publication/27782054 | first1 = Kari | last1 = Leppälä | first2 = Raimo | last2 = Verkasalo | date = 1989 }}</ref>

== {{anchor|power_supply}}Power supplies and logic levels ==
{{anchor|logic_levels}}
ECL circuits usually operate with negative power supplies (positive end of the supply is connected to ground).{{r|p=5|TND309}} (Other logic families ground the negative end of the power supply.) This is done mainly to minimize the influence of the power supply variations on the logic levels. ECL is more sensitive to noise on the V<sub>CC</sub> and is relatively immune to noise on V<sub>EE</sub>.<ref>{{cite book |url=https://books.google.com/books?id=c2YxCCaM9RIC&pg=PA163 |title=Electronic Materials Handbook: Packaging |page=163 |first=Merrill L. |last=Minges |author2=ASM International. Handbook Committee|date=1989 |publisher=ASM International |isbn=9780871702852 }}</ref> Because ground should be the most stable voltage in a system, ECL is specified with a positive ground. In this connection, when the supply voltage varies, the voltage drops across the collector resistors change slightly (in the case of emitter constant current source, they do not change at all). As the collector resistors are firmly "tied up" to ground, the output voltages "move" slightly (or not at all). If the negative end of the power supply was grounded, the collector resistors would be attached to the positive rail.{{r|p=5|TND309}} As the constant voltage drops across the collector resistors change slightly (or not at all), the output voltages follow the supply voltage variations and the two circuit parts act as constant current level shifters. In this case, the voltage divider R1-R2 compensates the voltage variations to some extent. The positive power supply has another disadvantage — the output voltages will vary slightly (±0.4 V) against the background of high constant voltage (+3.9 V). Another reason for using a negative power supply is protection of the output transistors from an accidental short circuit developing between output and ground<ref>{{cite book |url=https://books.google.com/books?id=dnq3HmDN1ZAC&pg=RA1-PA110 |title=Modern digital electronics  |first=R.P. |last=Jain |date=2003 |page=111|publisher=McGraw-Hill Education (India) Pvt Limited |isbn=9780070494923 }}</ref> (but the outputs are not protected from a short circuit with the negative rail).

The value of the supply voltage is chosen so that sufficient current flows through the compensating diodes D1 and D2 and the voltage drop across the common emitter resistor R<sub>E</sub> is adequate.

ECL circuits available on the open market usually operated with logic levels incompatible with other families. This meant that interoperation between ECL and other logic families, such as the popular [[Transistor-transistor logic|TTL]] family, required additional interface circuits.  The fact that the high and low logic levels are relatively close meant that ECL suffers from small noise margins, which can be troublesome.

At least one manufacturer, [[IBM]], made ECL circuits for use in the manufacturer's own products. The power supplies were substantially different from those used in the open market.<ref name=barish>{{cite journal | author=A. E. Barish | title=Improved performance of IBM Enterprise System/9000 bipolar logic chips | journal=IBM Journal of Research and Development | year=1992 | volume=36 | issue=5 | url=http://domino.watson.ibm.com/tchjr/journalindex.nsf/0/3f9af3392b4530f985256bfa0067fa2e?OpenDocument | pages= 829&ndash;834 | doi=10.1147/rd.365.0829|display-authors=etal| url-access=subscription }}
</ref>

===PECL===
{| class="wikitable" style="float:right; margin-left: 1em;
|+Logic levels for Motorolla ECL/PEC comparison<ref>{{cite web |last=Holland |first=Nick |date=December 2002 |title=Interfacing Between LVPECL, VML, CML and LVDS Levels |url=http://focus.ti.com/lit/an/slla120/slla120.pdf |work=Application Report |publisher=Texas Instruments |id=SLLA120}}</ref>{{r|TND309|p=5}}{{anchor|logic_levels_comparison}}
! Type
! V<sub>ee</sub>
! {{Abbr|V<sub>low</sub>|Logic level LOW (0)}}
! {{Abbr|V<sub>high</sub>|Logic level HIGH (1)}}
!{{Abbr|V<sub>swing</sub>|Logic level swing - difference between V_high and V_low}}
! V<sub>cc</sub>
!{{Abbr|V<sub>cm</sub>|cm - common mode voltage range.}}
|-
!ECL
|–5.2 V
|–1.75 V
|–0.9 V
|–0.85 V
|GND
|
|-
! PECL
| GND
| 3.4 V
| 4.2 V
|0.8 V
| 5.0 V
|
|-
! LVPECL
| GND
| 1.6 V
| 2.4 V
|0.8 V
| 3.3 V
| 2.0 V
|}

'''Positive emitter-coupled logic''', also called '''pseudo-ECL''', (PECL) is a further development of ECL using a positive 5&nbsp;V supply instead of a negative 5.2&nbsp;V supply.<ref>{{cite web |work=EE Times |first=John |last=Goldie |url=http://www.eetimes.com/document.asp?doc_id=1225744 |title=LVDS, CML, ECL – differential interfaces with odd voltages |date=January 21, 2003}}</ref>  Low-voltage positive emitter-coupled logic (LVPECL) is a power-optimized version of PECL, using a positive 3.3&nbsp;V instead of 5&nbsp;V supply. PECL and LVPECL are differential-signaling systems and are mainly used in high-speed and clock-distribution circuits.

A common misconception is that PECL devices are slightly different from ECL devices.
In fact, every ECL device is also a PECL device.<ref>
{{cite web |first1=Cleon |last1=Petty |first2=Todd |last2=Pearson
|url=https://www.onsemi.com/pub/Collateral/AN1406-D.PDF |title=Designing with PECL (ECL at +5.0 V) |id=AN1406-D
|page=3}}
</ref>

== Notes ==
{{Notelist}}

==References==
{{Reflist}}

==Further reading==
* {{cite web |title=What Computers Are Made From |first=John J. G. |last=Savard |date=2018 |orig-year=2005 |work=quadibloc |url=http://www.quadibloc.com/comp/cp01.htm |access-date=July 16, 2018 |url-status=live |archive-url=https://web.archive.org/web/20180702235616/http://www.quadibloc.com/comp/cp01.htm |archive-date=July 2, 2018}}
* {{Cite patent |inventor-last=Yourke |inventor-first=Hannon S. |title=Transistor Switching Circuits |country-code=US |patent-number=2964652 |publication-date=November 15, 1956 |issue-date=December 13, 1960 |doi= }}
* {{Cite journal |first=Hannon S. |last=Yourke |title=Millimicrosecond Transistor Current Switching Circuits |journal=IRE Transactions on Circuit Theory |volume=4 |issue=3 |pages=236–240 |date=September 1957 |doi=10.1109/TCT.1957.1086377 }}
* {{cite web |title=DECL test run — Differential emitter-coupled logic |first=Dieter |last=Mueller |date=2008 |orig-year=2006 |url=http://www.6502.org/users/dieter/decl/decl1.htm |access-date=July 18, 2018 |url-status=live |archive-url=https://web.archive.org/web/20180718215508/http://www.6502.org/users/dieter/decl/decl1.htm |archive-date=July 18, 2018}}

==External links==
*[http://www.worldpowersystems.com/archives/solid-state-datasheets/Motorola/MECL/index.html Motorola MECL logic family datasheets, 1963]

{{Logic Families}}
{{Digital electronics}}

{{DEFAULTSORT:Emitter-Coupled Logic}}
[[Category:Logic families]]