Editing Endianness

{{Short description|Order of bytes in a computer word}}
{{Redirect2|Big-endian|Little-endian|the conflicting ideologies in ''Gulliver's Travels''|Lilliput and Blefuscu#History and politics}}
{{For|the specific use of endianness in date formats|Calendar date}}
{{refimprove|date=July 2020}}
[[file:Gullivers_travels.jpg|thumb|''[[Gulliver's Travels]]'' by [[Jonathan Swift]], the novel from which the term was coined]]

In [[computing]], '''endianness''' is the order in which [[byte]]s within a [[word (data type)|word]] of digital data are transmitted over a [[data communication]] medium or [[Memory_address|addressed]] (by rising addresses) in [[computer memory]], counting only byte [[Bit_numbering#Bit significance and indexing|significance]] compared to earliness. Endianness is primarily expressed as '''big-endian''' ('''BE''') or '''little-endian''' ('''LE'''), terms introduced by [[Danny Cohen (computer scientist)|Danny Cohen]] into computer science for data ordering in an [[Internet Experiment Note]] published in 1980.<ref name="HOLY">{{cite IETF | title = On Holy Wars and a Plea for Peace | ien = 137 | last = Cohen | first = Danny | author-link = Danny Cohen (computer scientist) | date = 1980-04-01 | publisher = [[IETF]] }} Also published at {{cite journal |journal=IEEE Computer |volume=14 |issue=10 |url=https://ieeexplore.ieee.org/document/1667115 |title=On Holy Wars and a Plea for Peace |last=Cohen |first=Danny |pages=48–54 |doi=10.1109/C-M.1981.220208 |date=October 1981}}</ref> The adjective ''endian'' has its origin in the writings of 18th century Anglo-Irish writer [[Jonathan Swift]]. In the 1726 novel ''[[Gulliver's Travels]]'', he portrays the conflict between sects of Lilliputians divided into those breaking the shell of a [[boiled egg]] from the big end or from the little end.<ref>{{cite book | first = Jonathan | last = Swift | title = Gulliver's Travels | chapter = A Voyage to Lilliput, Chapter IV | year = 1726 | chapter-url = https://en.wikisource.org/wiki/The_Works_of_the_Rev._Jonathan_Swift/Volume_6/A_Voyage_to_Lilliput/Chapter_4 | access-date = 2022-09-20 | archive-date = 2022-09-20 | archive-url = https://web.archive.org/web/20220920173204/https://en.wikisource.org/wiki/The_Works_of_the_Rev._Jonathan_Swift/Volume_6/A_Voyage_to_Lilliput/Chapter_4 | url-status = live }}</ref><ref>{{Citation | last1 = Bryant | first1 = Randal E. | author-link = Randal Bryant | last2 = David | first2 = O'Hallaron | title = Computer Systems: A Programmer's Perspective | publisher = Pearson Education | year = 2016 | edition = 3 | isbn = 978-1-488-67207-1 | page = 79 }}</ref> By analogy, a CPU may read a digital word big end first or little end first.

Computers store information in various-sized groups of binary bits. Each group is assigned a number, called its ''address'', that the computer uses to access that data. On most modern computers, the smallest data group with an address is eight bits long and is called a byte. Larger groups comprise two or more bytes, for example, a [[32-bit]] word contains four bytes. There are two principal ways a computer could number the individual bytes in a larger group, starting at either end. Both types of endianness are in widespread use in digital electronic engineering. The initial choice of endianness of a new design is often arbitrary, but later technology revisions and updates perpetuate the existing endianness to maintain [[backward compatibility]].

A big-endian system stores the [[most significant byte]] of a word at the smallest [[memory address]] and the [[least significant byte]] at the largest. A little-endian system, in contrast, stores the least-significant byte at the smallest address.<ref>{{Cite web |url=https://betterexplained.com/articles/understanding-big-and-little-endian-byte-order/ |title=Understanding big and little endian byte order |website=betterexplained.com |access-date=2019-05-20 |archive-date=2019-05-24 |archive-url=https://web.archive.org/web/20190524124000/https://betterexplained.com/articles/understanding-big-and-little-endian-byte-order/ |url-status=live }}</ref><ref>{{Cite web |url=https://developer.apple.com/library/archive/documentation/CoreFoundation/Conceptual/CFMemoryMgmt/Concepts/ByteOrdering.html#//apple_ref/doc/uid/20001150-CJBEJBHH |title=Byte Ordering PPC |access-date=2019-05-20 |archive-date=2019-05-09 |archive-url=https://web.archive.org/web/20190509013855/https://developer.apple.com/library/archive/documentation/CoreFoundation/Conceptual/CFMemoryMgmt/Concepts/ByteOrdering.html#//apple_ref/doc/uid/20001150-CJBEJBHH |url-status=live }}</ref><ref>{{Cite web |url=https://developer.ibm.com/articles/au-endianc/ |title=Writing endian-independent code in C |access-date=2019-05-20 |archive-date=2019-06-10 |archive-url=https://web.archive.org/web/20190610085733/https://developer.ibm.com/articles/au-endianc/ |url-status=live }}</ref> Of the two, big-endian is thus closer to the way the digits of numbers are written left-to-right in English, comparing digits to bytes. ''Bi-endianness'' is a feature supported by numerous computer architectures that feature switchable endianness in data fetches and stores or for instruction fetches. Other orderings are generically called ''middle-endian'' or ''mixed-endian''.<ref>{{cite web |title = Internet Hall of Fame Pioneer |url = http://internethalloffame.org/inductees/danny-cohen |website = [[Internet Hall of Fame]] |publisher = [[The Internet Society]] |access-date = 2015-10-07 |archive-date = 2021-07-21 |archive-url = https://web.archive.org/web/20210721114730/https://www.internethalloffame.org/inductees/danny-cohen |url-status = live }}</ref><ref>{{cite web | first = David | last = Cary | title = Endian FAQ | url = http://david.carybros.com/html/endian_faq.html | access-date = 2010-10-11 | archive-date = 2017-11-09 | archive-url = https://web.archive.org/web/20171109112101/http://david.carybros.com/html/endian_faq.html | url-status = dead }}</ref><ref>{{cite journal | last = James |first = David V. | title = Multiplexed buses: the endian wars continue | journal = [[IEEE Micro]] | date = June 1990 | volume = 10 | issue = 3 | pages = 9–21 | doi = 10.1109/40.56322 | s2cid = 24291134 | issn = 0272-1732 }}</ref><ref>{{cite web | last1 = Blanc | first1 = Bertrand | last2 = Maaraoui | first2 = Bob | title = Endianness or Where is Byte 0? | date = December 2005 | url = http://3bc.bertrand-blanc.com/endianness05.pdf | access-date = 2008-12-21 | archive-date = 2007-12-03 | archive-url = https://web.archive.org/web/20071203190220/http://3bc.bertrand-blanc.com/endianness05.pdf | url-status = live }}</ref>

Big-endianness is the dominant ordering in networking protocols, such as in the [[Internet protocol suite]], where it is referred to as ''network order'', transmitting the most significant byte first. Conversely, little-endianness is the dominant ordering for processor architectures ([[x86]], most [[ARM architecture|ARM]] implementations, base [[RISC-V]] implementations) and their associated memory. [[File format]]s can use either ordering; some formats use a mixture of both or contain an indicator of which ordering is used throughout the file.<ref>{{Cite IETF|date=April 1992|rfc=1314|title=A File Format for the Exchange of Images in the Internet|page=7|access-date=2021-08-16 }}</ref>

== Characteristics ==
[[file:32bit-Endianess.svg|thumb|upright=2|Diagram demonstrating big- versus little-endianness]]

[[Computer memory]] consists of a sequence of storage cells (smallest [[address space|addressable]] units); in machines that support [[byte addressing]], those units are called ''[[byte]]s''. Each byte is identified and accessed in hardware and software by its [[memory address]]. If the total number of bytes in memory is ''n'', then addresses are enumerated from 0 to ''n''&nbsp;−&nbsp;1.

Computer programs often use data structures or [[Field (computer science)|fields]] that may consist of more data than can be stored in one byte. In the context of this article where its type cannot be arbitrarily complicated, a "field" consists of a consecutive sequence of bytes and represents a "simple data value" which – at least potentially – can be manipulated by ''one'' single [[Instruction set architecture|hardware instruction]]. On most systems, the address of a multi-byte simple data value is the address of its first byte (the byte with the lowest address). There are exceptions to this rule – for example, the Add instruction of the [[IBM 1401]] addresses variable-length fields at their low-order (highest-addressed) position with their lengths being defined by a [[Word mark (computer hardware)|word mark]] set at their high-order (lowest-addressed) position. When an operation such as addition is performed, the processor begins at the low-order positions at the high addresses of the two fields and works its way down to the high-order.{{cn|date=November 2023}}

Another important attribute of a byte being part of a "field" is its "significance".
These attributes of the parts of a field play an important role in the sequence the bytes are accessed by the computer hardware, more precisely: by the low-level algorithms contributing to the results of a computer instruction.

=== Numbers ===
[[Positional notation|Positional number systems]] (mostly base 2, or less often base 10) are the predominant way of representing and particularly of manipulating [[Integer (computer science)|integer data]] by computers. In pure form this is valid for moderate sized non-negative integers, e.g. of C data type <code>[[Signedness|unsigned]]</code>. In such a number system, the ''value'' of a digit that contributes to the whole number is determined not only by its value as a single digit, but also by the position it holds in the complete number, called its significance. These positions can be mapped to memory mainly in two ways:<ref name="TanenbaumAustin2012">{{cite book |first1=Andrew S. |last1=Tanenbaum |first2=Todd M. |last2=Austin |title=Structured Computer Organization |url=https://books.google.com/books?id=m0HHygAACAAJ |access-date=18 May 2013 |date=4 August 2012 |publisher=Prentice Hall PTR |isbn=978-0-13-291652-3}} </ref>
* Decreasing numeric significance with increasing memory addresses, known as ''big-endian'' and
* Increasing numeric significance with increasing memory addresses, known as ''little-endian''.

In ''big-endian'' and ''little-endian'', the ''end'' is the extremity where the ''big'' or ''little'' significance is written in the location indexed by the lowest memory address.

The integer data that are directly supported by the [[Arithmetic logic unit|computer hardware]] have a fixed width of a low power of 2, e.g. 8 bits ≙ 1 byte, 16 bits ≙ 2 bytes, 32 bits ≙ 4 bytes, 64 bits ≙ 8 bytes, 128 bits ≙ 16 bytes. The low-level access sequence to the bytes of such a field depends on the operation to be performed. The least-significant byte is accessed first for [[addition]], [[subtraction]] and [[multiplication]]. The most-significant byte is accessed first for [[Division (mathematics)|division]] and [[Natural number# Order|comparison]]. See {{section link||Calculation order}}.

=== Text ===

When character (text) strings are to be compared with one another, e.g. in order to support some mechanism like [[Sorting algorithm|sorting]], this is very frequently done [[lexicographically]] where a single positional element (character) also has a positional value. Lexicographical comparison means almost everywhere: first character ranks highest – as in the telephone book. Almost all machines which can do this using a single instruction are big-endian or at least mixed-endian.{{cn|date=November 2023}}

Integer numbers written as text are always represented most significant digit first in memory, which is similar to big-endian, independently of [[text direction]].

=== Byte addressing ===
{{See also|Byte addressing}}

When memory bytes are printed sequentially from left to right (e.g. in a [[hex dump]]), little-endian representation of integers has the significance increasing from right to left. In other words, it appears backwards when visualized, which can be counter-intuitive.

This behavior arises, for example, in [[FourCC]] or similar techniques that involve packing characters into an integer, so that it becomes a sequence of specific characters in memory. For example, take the string "JOHN", stored in hexadecimal [[ASCII]]. On big-endian machines, the value appears left-to-right, coinciding with the correct string order for reading the result ("J O H N"). But on a little-endian machine, one would see "N H O J". Middle-endian machines complicate this even further; for example, on the [[PDP-11]], the 32-bit value is stored as two 16-bit words "JO" "HN" in big-endian, with the characters in the 16-bit words being stored in little-endian, resulting in "O J N H".<ref name=":0" />

=== Byte swapping ===

Byte-swapping consists of rearranging bytes to change endianness. Many compilers provide [[Intrinsic function|built-ins]] that are likely to be compiled into native processor instructions ({{code|bswap}}/{{code|movbe}}), such as {{code|__builtin_bswap32}}. Software interfaces for swapping include:

* Standard [[#Networking|network endianness]] functions (from/to BE, up to 32-bit).<ref>{{man|3|byteorder|Linux}}</ref> Windows has a 64-bit extension in {{code|winsock2.h}}.
* BSD and Glibc {{code|endian.h}} functions (from/to BE and LE, up to 64-bit).<ref>{{man|3|endian|Linux}}</ref>
* [[macOS]] {{code|OSByteOrder.h}} macros (from/to BE and LE, up to 64-bit).
* The {{code|std::byteswap}} function in [[C++23]].<ref>{{cite web |title=std::byteswap |url=https://en.cppreference.com/w/cpp/numeric/byteswap |website=en.cppreference.com |access-date=3 October 2023 |archive-date=20 November 2023 |archive-url=https://web.archive.org/web/20231120095109/https://en.cppreference.com/w/cpp/numeric/byteswap |url-status=live }}</ref>

Some [[CPU]] instruction sets provide native support for endian byte swapping, such as {{code|bswap}}<ref>{{cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf |archive-date=2022-10-09 |url-status=live|title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z|at=p. 3–112|publisher=Intel|date=September 2016|access-date=2017-02-05}}</ref> ([[x86]] — [[Intel 80486|486]] and later, [[i960]] — i960Jx and later<ref>{{cite web|url=https://datasheets.chipdb.org/Intel/80960/manuals/27317301.PDF|title=i960® VH Processor Developer's Manual|publisher=Intel|date=October 1998|access-date=2024-04-02|archive-date=2024-04-02|archive-url=https://web.archive.org/web/20240402165236/https://datasheets.chipdb.org/Intel/80960/manuals/27317301.PDF|url-status=live}}</ref>), and {{code|rev}}<ref>{{cite web|url=http://infocenter.arm.com/help/topic/com.arm.doc.ddi0487a.k_10775/index.html|title=ARMv8-A Reference Manual|publisher=[[ARM Holdings]]|access-date=2017-02-05|archive-date=2019-01-19|archive-url=https://web.archive.org/web/20190119214452/http://infocenter.arm.com/help/topic/com.arm.doc.ddi0487a.k_10775/index.html|url-status=live}}</ref> ([[ARM architecture|ARMv6]] and later).

Some [[compiler]]s have built-in facilities for byte swapping. For example, the [[Intel]] [[Fortran]] compiler supports the non-standard {{code|CONVERT}} specifier when opening a file, e.g.: {{code|1=OPEN(unit, CONVERT='BIG_ENDIAN',...)|2=fortran|class=nowrap}}. Other compilers have options for generating code that globally enables the conversion for all file IO operations. This permits the reuse of code on a system with the opposite endianness without code modification.

== Considerations ==

=== Simplified access to part of a field ===

On most systems, the address of a multi-byte value is the address of its first byte (the byte with the lowest address); little-endian systems of that type have the property that, for sufficiently low data values, the same value can be read from memory at different lengths without using different addresses (even when [[byte alignment|alignment]] restrictions are imposed). For example, a 32-bit memory location with content {{code|4A 00 00 00|class=nowrap}} can be read at the same address as either [[8-bit]] (value = 4A), [[16-bit]] (004A), [[24-bit]] (00004A), or [[32-bit]] (0000004A), all of which retain the same numeric value. Although this little-endian property is rarely used directly by high-level programmers, it is occasionally employed by code optimizers as well as by [[assembly language]] programmers. While not allowed by C++, such [[type punning]] code is allowed as "implementation-defined" by the C11 standard<ref>{{cite web |title = C11 standard |url = https://www.iso.org/standard/57853.html |publisher = ISO |access-date = 15 August 2018 |at = Section 6.5.2.3 "Structure and Union members", §3 and footnote 95 |archive-date = 28 March 2020 |archive-url = https://web.archive.org/web/20200328063511/https://www.iso.org/standard/57853.html |url-status = live }}</ref> and commonly used<ref>{{cite web |title=3.10 Options That Control Optimization: -fstrict-aliasing |url=https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#Type-punning |website=GNU Compiler Collection (GCC) |publisher=Free Software Foundation |access-date=15 August 2018 |archive-date=1 July 2023 |archive-url=https://web.archive.org/web/20230701053330/https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#Type-punning |url-status=live }}</ref> in code interacting with hardware.<ref>{{cite mailing list |first=Linus |last=Torvalds |title=[GIT PULL] Device properties framework update for v4.18-rc1 |url=https://lkml.org/lkml/2018/6/5/769 |mailing-list=Linux Kernel |access-date=15 August 2018 |date=5 Jun 2018 |archive-date=15 August 2018 |archive-url=https://web.archive.org/web/20180815090956/https://lkml.org/lkml/2018/6/5/769 |url-status=live }}</ref>

=== Calculation order ===

Some operations in [[positional number system]]s have a natural or preferred order in which the elementary steps are to be executed. This order may affect their performance on small-scale byte-addressable processors and [[microcontroller]]s. However, high-performance processors usually fetch multi-byte operands from memory in the same amount of time they would have fetched a single byte, so the complexity of the hardware is not affected by the byte ordering.

Addition, subtraction, and multiplication start at the least significant digit position and [[Adder (electronics)|propagate the carry]] to the subsequent more significant position. On most systems, the address of a multi-byte value is the address of its first byte (the byte with the lowest address). The implementation of these operations is marginally simpler using little-endian machines where this first byte contains the least significant digit.

Comparison and division start at the most significant digit and propagate a possible carry to the subsequent less significant digits. For fixed-length numerical values (typically of length 1,2,4,8,16), the implementation of these operations is marginally simpler on big-endian machines.

Some big-endian processors (e.g. the IBM System/360 and its successors) contain hardware instructions for lexicographically comparing varying length [[character string]]s.

The normal data transport by an [[Assignment (computer science)|assignment]] statement is in principle independent of the endianness of the processor.

== Hardware ==

Many historical and extant processors use a big-endian memory representation, either exclusively or as a design option. The [[IBM System/360]] uses big-endian byte order, as do its successors [[System/370]], [[ESA/390]], and [[z/Architecture]]. The [[PDP-10]] uses big-endian addressing for byte-oriented instructions. The [[IBM Series/1]] minicomputer uses big-endian byte order. The Motorola [[Motorola 6800|6800]] / 6801, the [[6809]] and the [[68000 series]] of processors use the big-endian format. Solely big-endian architectures include the IBM z/Architecture and [[OpenRISC]]. The [[PDP-11]] minicomputer, however, uses little-endian byte order, as does its [[VAX]] successor.

The [[Datapoint 2200]] used simple bit-serial logic with little-endian to facilitate [[carry propagation]]. When Intel developed the [[8008]] microprocessor for Datapoint, they used little-endian for compatibility. However, as Intel was unable to deliver the 8008 in time, Datapoint used a [[medium-scale integration]] equivalent, but the little-endianness was retained in most Intel designs, including the [[MCS-48]] and the [[8086]] and its [[x86]] successors, including [[IA-32]] and [[x86-64]] processors.<ref>{{cite web |last=House |first=David |title=Oral History Panel on the Development and Promotion of the Intel 8008 Microprocessor |url=http://archive.computerhistory.org/resources/text/Oral_History/Intel_8008/Intel_8008_1.oral_history.2006.102657982.pdf#page=5 |publisher=[[Computer History Museum]] |access-date=23 April 2014 |author2=Faggin, Federico |author3=Feeney, Hal |author4=Gelbach, Ed |author5=Hoff, Ted |author6=Mazor, Stan |author7=Smith, Hank |page=b5 |date=2006-09-21 |archive-date=2014-06-29 |archive-url=https://web.archive.org/web/20140629084907/http://archive.computerhistory.org/resources/text/Oral_History/Intel_8008/Intel_8008_1.oral_history.2006.102657982.pdf#page=5 |url-status=live }}</ref><ref name="Lunde2009">{{cite book |first = Ken |last = Lunde |title = CJKV Information Processing |url = https://books.google.com/books?id=SA92uQqTB-AC&pg=PA29 |access-date=21 May 2013 |date = 13 January 2009 |publisher = O'Reilly Media, Inc. |isbn = 978-0-596-51447-1 |page = 29 }}</ref> The [[MOS Technology 6502]] family (including [[Western Design Center]] [[65802]] and [[65C816]]), the Zilog [[Z80]] (including [[Z180]] and [[eZ80]]), the [[Altera]] [[Nios II]], the [[Atmel AVR]], the [[Andes Technology]] NDS32, the [[Qualcomm Hexagon]], and many other processors and processor families are also little-endian.

The Intel [[8051]], unlike other Intel processors, expects 16-bit addresses for LJMP and LCALL in big-endian format; however, xCALL instructions store the return address onto the stack in little-endian format.<ref>{{cite web|url=http://www.keil.com/support/man/docs/c51/c51_xe.htm|title=Cx51 User's Guide: E. Byte Ordering|website=keil.com|access-date=2015-03-28|archive-date=2015-04-02|archive-url=https://web.archive.org/web/20150402094251/http://www.keil.com/support/man/docs/c51/c51_xe.htm|url-status=live}}</ref>

=== Bi-endianness ===

Some instruction set architectures feature a setting which allows for switchable endianness in data fetches and stores, instruction fetches, or both; those instruction set architectures are referred to as ''bi-endian''. Architectures that support switchable endianness include [[PowerPC]]/[[Power ISA]], [[SPARC]] V9, [[ARM architecture|ARM]] versions 3 and above, [[DEC Alpha]], [[MIPS architecture|MIPS]], [[Intel i860]], [[PA-RISC]], [[SuperH|SuperH SH-4]], [[IA-64]], [[C-Sky]], and [[RISC-V]]. This feature can improve performance or simplify the logic of networking devices and software. The word ''bi-endian'', when said of hardware, denotes the capability of the machine to compute or pass data in either endian format.

Many of these architectures can be switched via software to default to a specific endian format (usually done when the computer starts up); however, on some systems, the default endianness is selected by hardware on the motherboard and cannot be changed via software (e.g. Alpha, which runs only in big-endian mode on the [[Cray T3E]]).

[[IBM AIX]] and [[IBM i]] run in big-endian mode on bi-endian Power ISA; [[Linux]] originally ran in big-endian mode, but by 2019, IBM had transitioned to little-endian mode for Linux to ease the porting of Linux software from x86 to Power.<ref>{{cite web |title=Little endian and Linux on IBM Power Systems |url=https://developer.ibm.com/articles/l-power-little-endian-faq-trs/ |date=2016-06-16 |website=IBM |author=Jeff Scheel |access-date=2022-03-27 |archive-date=2022-03-27 |archive-url=https://web.archive.org/web/20220327025540/https://developer.ibm.com/articles/l-power-little-endian-faq-trs/ |url-status=live }}</ref><ref>{{cite web |last1=Timothy Prickett Morgan |title=The Transition To RHEL 8 Begins On Power Systems |url=https://www.itjungle.com/2019/06/10/the-transition-to-rhel-8-begins-on-power-systems/ |website=ITJungle |date=10 June 2019 |access-date=26 March 2022 |archive-date=24 January 2022 |archive-url=https://web.archive.org/web/20220124063316/https://www.itjungle.com/2019/06/10/the-transition-to-rhel-8-begins-on-power-systems/ |url-status=live }}</ref> SPARC has no relevant little-endian deployment, as both [[Oracle Solaris]] and Linux run in big-endian mode on bi-endian SPARC systems, and can be considered big-endian in practice. ARM, C-Sky, and RISC-V have no relevant big-endian deployments, and can be considered little-endian in practice.

The term ''bi-endian'' refers primarily to how a processor treats data accesses. Instruction accesses (fetches of instruction words) on a given processor may still assume a fixed endianness, even if data accesses are fully bi-endian, though this is not always the case, such as on Intel's [[IA-64]]-based Itanium CPU, which allows both.

Some nominally bi-endian CPUs require motherboard help to fully switch endianness. For instance, the 32-bit desktop-oriented [[PowerPC]] processors in little-endian mode act as little-endian from the point of view of the executing programs, but they require the motherboard to perform a 64-bit swap across all 8 byte lanes to ensure that the little-endian view of things will apply to [[I/O]] devices. In the absence of this unusual motherboard hardware, device driver software must write to different addresses to undo the incomplete transformation and also must perform a normal byte swap.{{or|date=November 2023}}

Some CPUs, such as many PowerPC processors intended for embedded use and almost all SPARC processors, allow per-page choice of endianness.

SPARC processors since the late 1990s (SPARC v9 compliant processors) allow data endianness to be chosen with each individual instruction that loads from or stores to memory.

The [[ARM architecture]] supports two big-endian modes, called ''BE-8'' and ''BE-32''.<ref>{{cite web|title=Differences between BE-32 and BE-8 buses|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html|access-date=2019-02-10|archive-date=2019-02-12|archive-url=https://web.archive.org/web/20190212070549/http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html|url-status=live}}</ref> CPUs up to ARMv5 only support BE-32 or word-invariant mode. Here any naturally aligned 32-bit access works like in little-endian mode, but access to a byte or 16-bit word is redirected to the corresponding address and unaligned access is not allowed. ARMv6 introduces BE-8 or byte-invariant mode, where access to a single byte works as in little-endian mode, but accessing a 16-bit, 32-bit or (starting with ARMv8) 64-bit word results in a byte swap of the data. This simplifies unaligned memory access as well as memory-mapped access to registers other than 32-bit.

Many processors have instructions to convert a word in a register to the opposite endianness, that is, they swap the order of the bytes in a 16-, 32- or 64-bit word. 

Recent Intel x86 and x86-64 architecture CPUs have a MOVBE instruction ([[Intel Core]] since generation 4, after [[Intel Atom|Atom]]),<ref>{{cite web |title = How to detect New Instruction support in the 4th generation Intel® Core™ processor family |url = https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf |access-date = 2 May 2017 |archive-date = 20 March 2016 |archive-url = https://web.archive.org/web/20160320222513/https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf |url-status = live }}</ref> which fetches a big-endian format word from memory or writes a word into memory in big-endian format. These processors are otherwise thoroughly little-endian.

There are also devices which use different formats in different places. For instance, the BQ27421 [[Texas Instruments]] battery gauge uses the little-endian format for its registers and the big-endian format for its [[random-access memory]].

[[SPARC]] historically used big-endian until version 9, which is bi-endian. Similarly early IBM POWER processors were big-endian, but the [[PowerPC]] and [[Power ISA]] descendants are now bi-endian. The [[ARM architecture]] was little-endian before version 3 when it became bi-endian.

=== Floating point ===

Although many processors use little-endian storage for all types of data (integer, floating point), there are a number of hardware architectures where [[floating-point]] numbers are represented in big-endian form while integers are represented in little-endian form.<ref>{{citation |title=Floating-Point Formats |author-first=John J. G. |author-last=Savard |date=2018 |orig-year=2005 |work=quadibloc |url=http://www.quadibloc.com/comp/cp0201.htm |access-date=2018-07-16 |url-status=live |archive-url=https://web.archive.org/web/20180703001709/http://www.quadibloc.com/comp/cp0201.htm |archive-date=2018-07-03}}</ref> There are [[ARM architecture|ARM]] processors that have mixed-endian floating-point representation for double-precision numbers: each of the two 32-bit words is stored as little-endian, but the most significant word is stored first. [[VAX]] floating point stores little-endian 16-bit words in big-endian order. Because there have been many floating-point formats with no network standard representation for them, the [[External Data Representation|XDR]] standard uses big-endian IEEE 754 as its representation. It may therefore appear strange that the widespread [[IEEE 754]] floating-point standard does not specify endianness.<ref>{{cite web |title = pack – convert a list into a binary representation |url = http://www.perl.com/doc/manual/html/pod/perlfunc/pack.html |access-date = 2009-02-04 |archive-date = 2009-02-18 |archive-url = https://web.archive.org/web/20090218010333/http://perl.com/doc/manual/html/pod/perlfunc/pack.html |url-status = live }}</ref> Theoretically, this means that even standard IEEE floating-point data written by one machine might not be readable by another. However, on modern standard computers (i.e., implementing IEEE 754), one may safely assume that the endianness is the same for floating-point numbers as for integers, making the conversion straightforward regardless of data type. Small [[embedded system]]s using special floating-point formats may be another matter, however.

=== Variable-length data ===

Most instructions considered so far contain the size (lengths) of their [[operand]]s within the [[operation code]]. Frequently available operand lengths are 1, 2, 4, 8, or 16 bytes. But there are also architectures where the length of an operand may be held in a separate field of the instruction or with the operand itself, e.g. by means of a [[word mark (computer hardware)|word mark]]. Such an approach allows operand lengths up to 256 bytes or larger. The data types of such operands are character strings or [[binary-coded decimal|BCD]]. Machines able to manipulate such data with one instruction (e.g. compare, add) include the [[IBM 1401]], [[IBM 1410|1410]], [[IBM 1620|1620]], [[System/360]], [[System/370]], [[ESA/390]], and [[z/Architecture]], all of them of type big-endian.

=== Middle-endian ===

Numerous other orderings, generically called ''middle-endian'' or ''mixed-endian'', are possible.

The [[PDP-11]] is in principle a 16-bit little-endian system. The instructions to convert between floating-point and integer values in the optional floating-point processor of the PDP-11/45, PDP-11/70, and in some later processors, stored 32-bit "double precision integer long" values with the 16-bit halves swapped from the expected little-endian order. The [[UNIX]] [[C (programming language)|C]] compiler used the same format for 32-bit long integers. This ordering is known as ''PDP-endian''.<ref>{{cite book|url=http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf |archive-date=2022-10-09 |url-status=live|title=PDP-11/45 Processor Handbook|page=165|year=1973|publisher=[[Digital Equipment Corporation]]}}</ref>

UNIX was one of the first systems to allow the same code to be compiled for platforms with different internal representations. One of the first programs converted was supposed to print out {{code|Unix}}, but on the Series/1 it printed {{code|nUxi}} instead.<ref name=":0">{{cite journal |last1=Jalics|first1=Paul J. |last2=Heines|first2=Thomas S. |title = Transporting a portable operating system: UNIX to an IBM minicomputer |journal=Communications of the ACM|date=1 December 1983|volume=26|issue=12|pages=1066–1072|doi=10.1145/358476.358504|s2cid=15558835 |doi-access=free}}</ref>

A way to interpret this endianness is that it stores a 32-bit integer as two little-endian 16-bit words, with a big-endian word ordering:

{| class="wikitable"
|+ Storage of a 32-bit integer, <kbd>0x0A0B0C0D</kbd>, on a PDP-11
|-
! scope="col" | byte offset
! scope="col" | 8-bit value
! scole="col" | 16-bit little-endian value
|-
! scope="row" | 0
| <kbd>0B<sub>h</sub></kbd>
| rowspan="2" | <kbd>0A0B<sub>h</sub></kbd>
|-
! scope="row" | 1
| <kbd>0A<sub>h</sub></kbd>
|-
! scope="row" | 2
| <kbd>0D<sub>h</sub></kbd>
| rowspan="2" | <kbd>0C0D<sub>h</sub></kbd>
|-
! scope="row" | 3
| <kbd>0C<sub>h</sub></kbd>
|}

[[Segment descriptors]] of [[IA-32]] and compatible processors keep a 32-bit base address of the segment stored in little-endian order, but in four nonconsecutive bytes, at relative positions 2, 3, 4 and 7 of the descriptor start.<ref>{{Cite tech report|title=AMD64 Architecture Programmer's Manual Volume 2: System Programming|page=80|url=http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf|year=2013|archiveurl=https://web.archive.org/web/20180218024045/http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2012/10/24593_APM_v21.pdf|archivedate=2018-02-18}}</ref>

== Software ==

=== Logic design ===

[[Hardware description language]]s (HDLs) used to express digital logic often support arbitrary endianness, with arbitrary granularity. For example, in [[SystemVerilog]], a word can be defined as little-endian or big-endian.{{cn|date=November 2023}}

=== Files and filesystems ===

The recognition of endianness is important when reading a file or filesystem created on a computer with different endianness.

Fortran sequential unformatted files created with one endianness usually cannot be read on a system using the other endianness because Fortran usually implements a [[storage record|record]] (defined as the data written by a single Fortran statement) as data preceded and succeeded by count fields, which are integers equal to the number of bytes in the data. An attempt to read such a file using Fortran on a system of the other endianness results in a run-time error, because the count fields are incorrect.

[[Unicode]] text can optionally start with a [[byte order mark]] (BOM) to signal the endianness of the file or stream. Its code point is U+FEFF. In [[UTF-32]] for example, a big-endian file should start with {{code|00 00 FE FF|class=nowrap}}; a little-endian should start with {{code|FF FE 00 00|class=nowrap}}.

Application binary data formats, such as [[MATLAB]] ''.mat'' files, or the ''.bil'' data format, used in topography, are usually endianness-independent. This is achieved by storing the data always in one fixed endianness or carrying with the data a switch to indicate the endianness. An example of the former is the binary [[XLS file]] format that is portable between Windows and Mac systems and always little-endian, requiring the Mac application to swap the bytes on load and save when running on a big-endian Motorola 68K or PowerPC processor.<ref>{{cite web |url=http://download.microsoft.com/download/0/B/E/0BE8BDD7-E5E8-422A-ABFD-4342ED7AD886/Excel97-2007BinaryFileFormat(xls)Specification.xps |title=Microsoft Office Excel 97 - 2007 Binary File Format Specification (*.xls 97-2007 format) |year=2007 |publisher=Microsoft Corporation |access-date=2014-08-18 |archive-date=2008-12-22 |archive-url=https://web.archive.org/web/20081222093136/http://download.microsoft.com/download/0/B/E/0BE8BDD7-E5E8-422A-ABFD-4342ED7AD886/Excel97-2007BinaryFileFormat(xls)Specification.xps |url-status=live }}</ref>

[[TIFF]] image files are an example of the second strategy, whose header instructs the application about the endianness of their internal binary integers. If a file starts with the signature {{code|MM}} it means that integers are represented as big-endian, while {{code|II}} means little-endian. Those signatures need a single 16-bit word each, and they are [[palindrome]]s, so they are endianness independent. {{code|I}} stands for [[Intel]] and {{code|M}} stands for [[Motorola]]. Intel CPUs are little-endian, while Motorola 680x0 CPUs are big-endian. This explicit signature allows a TIFF reader program to swap bytes if necessary when a given file was generated by a TIFF writer program running on a computer with a different endianness.

As a consequence of its original implementation on the Intel 8080 platform, the operating system-independent [[File Allocation Table]] (FAT) file system is defined with little-endian byte ordering, even on platforms using another endianness natively, necessitating byte-swap operations for maintaining the FAT on these platforms.

[[ZFS]], which combines a [[filesystem]] and a [[logical volume manager]], is known to provide adaptive endianness and to work with both big-endian and little-endian systems.<ref>{{cite AV media |url=http://open-zfs.org/wiki/Documentation/Read_Write_Lecture |title=FreeBSD Kernel Internals: An Intensive Code Walkthrough |author=Matt Ahrens |year=2016 |publisher=OpenZFS Documentation/Read Write Lecture |access-date=2016-03-30 |archive-date=2016-04-14 |archive-url=https://web.archive.org/web/20160414051047/http://open-zfs.org/wiki/Documentation/Read_Write_Lecture |url-status=live }}</ref>

=== Networking ===

Many [[IETF RFC]]s use the term ''network order'', meaning the order of transmission for bytes ''over the wire'' in [[network protocols]]. Among others, the historic {{IETF RFC|1700|link=no}} defines the network order for protocols in the [[Internet protocol suite]] to be big-endian.<ref>{{ cite IETF | title = Assigned Numbers | rfc = 1700 | std = 2 | sectionname = Data Notations | page = 3 | last1 = Reynolds | first1 = J. | author-link1 = Joyce K. Reynolds | last2 = Postel | first2 = J. | author-link2 = Jon Postel | date=October 1994 | publisher = [[IETF]] | access-date = 2012-03-02 }}</ref>

However, not all protocols use big-endian byte order as the network order. The [[Server Message Block]] (SMB) protocol uses little-endian byte order. In [[CANopen]], multi-byte parameters are always sent [[least significant byte]] first (little-endian). The same is true for [[Ethernet Powerlink]].<ref>Ethernet POWERLINK Standardisation Group (2012), ''EPSG Working Draft Proposal 301: Ethernet POWERLINK Communication Profile Specification Version 1.1.4'', chapter 6.1.1.</ref>

The [[Berkeley sockets]] [[API]] defines a set of functions to convert 16- and 32-bit integers to and from network byte order: the {{code|htons}} (host-to-network-short) and {{code|htonl}} (host-to-network-long) functions convert 16- and 32-bit values respectively from machine (''host'') to network order; the {{code|ntohs}} and {{code|ntohl}} functions convert from network to host order.<ref>{{cite book | title = The Open Group Base Specifications Issue 7 | author = IEEE and The Open Group | date = 2018 | volume = 2 | chapter = 3. System Interfaces | page = 1120 | url = https://pubs.opengroup.org/onlinepubs/9699919799/functions/htonl.html | access-date = 2021-04-09 | archive-date = 2021-04-18 | archive-url = https://web.archive.org/web/20210418041546/https://pubs.opengroup.org/onlinepubs/9699919799/functions/htonl.html | url-status = live }}</ref><ref>{{Cite web|title=htonl(3) - Linux man page|url=https://linux.die.net/man/3/htonl|access-date=2021-04-09|website=linux.die.net|archive-date=2021-04-18|archive-url=https://web.archive.org/web/20210418054331/https://linux.die.net/man/3/htonl|url-status=live}}</ref> These functions may be a [[no-op]] on a big-endian system.

While the high-level network protocols usually consider the byte (mostly meant as ''[[octet (computing)|octet]]'') as their atomic unit, the lowest layers of a [[network stack]] may deal with ordering of bits within a byte.

== See also ==

* {{annotated link|Bit order}}

== References ==

{{refs}}

== External links ==
{{Commons category}}
* {{Wiktionary-inline}}

[[Category:Computer memory]]
[[Category:Data transmission]]
[[Category:Metaphors]]
[[Category:Software wars]]