Editing Hardware description language

{{short description|Specialized computer language used to describe electronic circuits}}
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{{more citations needed|date=January 2013}}
{{technical|date=April 2014}}
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In [[computer engineering]], a '''hardware description language''' ('''HDL''') is a specialized [[computer language]] used to describe the structure and behavior of [[electronic circuit]]s, usually to design [[application-specific integrated circuit]]s (ASICs) and to program [[field-programmable gate array]]s (FPGAs).

A hardware description language enables a precise, [[Formal language|formal]] description of an electronic circuit that allows for the automated analysis and [[Electronic circuit simulation|simulation]] of the circuit. It also allows for the [[Logic synthesis|synthesis]] of an HDL description into a [[netlist]] (a specification of physical electronic components and how they are connected together), which can then be [[Place and route|placed and routed]] to produce the [[Mask set|set of masks]] used to create an [[integrated circuit]].

A hardware description language looks much like a [[programming language]] such as [[C (programming language)|C]] or [[ALGOL]]; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time.

HDLs form an integral part of [[electronic design automation]] (EDA) systems, especially for complex circuits, such as [[application-specific integrated circuit]]s, [[microprocessor]]s, and [[programmable logic device]]s.

==Motivation==
Due to the exploding complexity of digital electronic circuits since the 1970s (see [[Moore's law]]), circuit designers needed [[digital logic]] descriptions to be performed at a high level without being tied to a specific electronic technology, such as [[Emitter-coupled logic|ECL]], [[Transistor–transistor logic|TTL]] or [[CMOS]]. HDLs were created to implement [[register-transfer level]] abstraction, a model of the data flow and timing of a circuit.<ref>{{cite book|last=Ciletti|first=Michael D.|title=Advanced Digital Design with Verilog HDL|publisher=Prentice Hall|year=2011 |isbn=9780136019282 |edition=2nd}}</ref>

There are two major hardware description languages: [[VHDL]] and [[Verilog]]. There are different types of description in them: "dataflow, behavioral and structural".
Example of dataflow of VHDL:

<syntaxhighlight lang="vhdl">
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY not1 IS
    PORT(
        a : IN  STD_LOGIC;
        b : OUT STD_LOGIC
    );
END not1;

ARCHITECTURE behavioral OF not1 IS
BEGIN
    b <= NOT a;
END behavioral;
</syntaxhighlight>

==Structure of HDL==
HDLs are standard text-based expressions of the structure of electronic systems and their behaviour over time. Like [[concurrent programming]] languages, HDL syntax and semantics include explicit notations for expressing [[concurrency (computer science)|concurrency]]. However, in contrast to most software [[programming language]]s, HDLs also include an explicit notion of time, which is a primary attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as [[netlist]] languages used in electric [[computer-aided design]]. HDL can be used to express designs in structural, behavioral or register-transfer-level architectures for the same circuit functionality; in the latter two cases the [[Logic synthesis|synthesizer]] decides the architecture and logic gate layout.

HDLs are used to write executable specifications for hardware. A program designed to implement the underlying semantics of the language statements and simulate the progress of time provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being [[programming languages]], when they are more precisely classified as [[specification language]]s or [[modeling language]]s. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available.

===Comparison with control-flow languages===
It is certainly possible to represent hardware semantics using traditional programming languages such as [[C++]], which operate on [[control flow]] semantics as opposed to [[data flow]], although to function as such, programs must be augmented with extensive and unwieldy [[Class library#Object and class libraries|class libraries]]. Generally, however, software programming languages do not include any capability for explicitly expressing time, and thus cannot function as hardware description languages. Before the introduction of [[System Verilog]] in 2002, [[C++]] integration with a [[Logic simulation|logic simulator]] was one of the few ways to use [[object-oriented programming]] in hardware verification. System Verilog is the first major HDL to offer object orientation and garbage collection.

Using the proper subset of hardware description language, a program called a synthesizer, or [[Logic synthesis|logic synthesis tool]], can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives{{technical statement|date=April 2014}} to implement the specified behaviour.{{Citation needed|date=July 2010}} Synthesizers generally ignore the expression of any timing constructs in the text. Digital logic synthesizers, for example, generally use [[Clock signal|clock edges]] as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language does not itself make a hardware description language.

== History ==

The first hardware description languages appeared in the late 1960s, looking like more traditional languages.<ref>Barbacci, M. "A comparison of register transfer languages for describing computers and digital systems," Carnegie-Mellon Univ., Dept. of Computer Science, March 1973</ref> The first that had a lasting effect was described in 1971 in [[Gordon Bell|C. Gordon Bell]] and Allen Newell's text ''Computer Structures''.<ref>{{cite book|last1=Bell|first1=C. G.|last2=Newell|first2=A.|title=Computer Structures: Readings and Examples|publisher=McGraw-Hill|year=1971|isbn=0-07-004357-4|url-access=registration|url=https://archive.org/details/computerstructur00bell}}</ref> This text introduced the concept of [[register transfer level]], first used in the ISP language to describe the behavior of the [[Digital Equipment Corporation]] (DEC) [[PDP-8]].<ref>{{cite book|last=Reilly|first=E.D.|title=Milestones in computer science and information technology|url=https://archive.org/details/milestonesincomp0000reil|url-access=registration|page=[https://archive.org/details/milestonesincomp0000reil/page/183 183]|publisher=Greenwood Press|year=2003|isbn=1-57356-521-0}}</ref>

The language became more widespread with the introduction of DEC's PDP-16 RT-Level Modules (RTMs) and a book describing their use.<ref>{{cite book|last1=Bell|first1=C.G.|last2=Grason|first2=J.|last3=Newell|first3=A.|title=Designing Computers and Digital Systems|publisher=Digital Press|year=1972 |lccn=72-89566 |oclc=440245727}}</ref>
At least two implementations of the basic ISP language (ISPL and ISPS) followed.<ref>{{cite report |first1=M.C. |last1=Barbacci |date=1976 |title=The Symbolic Manipulation of Computer Descriptions: ISPL Compiler and Simulator |publisher=Department of Computer Science, Carnegie-Mellon University |doi=10.1184/R1/6610790.v1}}</ref><ref>{{cite report |first1=M.C. |last1=Barbacci |last2=Barnes |first2=G.E. |last3=Cattell |first3=R.G.G. |date=1977 |last4=Siewiorek |first4=D.P. |title=The ISPS Computer Description Language |publisher=Department of Computer Science, Carnegie-Mellon University |doi=10.1184/R1/6610637.v1}}</ref>
ISPS was well suited to describe relations between the [[Input/output|inputs and the outputs]] of the design and was quickly adopted by commercial teams at DEC, and by several research teams in the US and among its allies in the North Atlantic Treaty Organization ([[NATO]]).

The RTM products never succeeded commercially and DEC stopped marketing them in the mid-1980s, as new methods grew more popular, more so [[very-large-scale integration]] (VLSI).

Separate work done about 1979 at the [[University of Kaiserslautern]] produced a language called KARL ("KAiserslautern Register Transfer Language"), which included design calculus language features supporting VLSI chip floorplanning{{technical statement|date=April 2014}} and structured hardware design. This work was also the basis of KARL's interactive graphic sister language ABL, whose name was an [[initialism]] for "a block diagram language".<ref>{{cite report |title=ABL specification |author1=Girardi, G. |author2=Hartenstein, R. |publisher=[[CSELT]] and [[University of Kaiserslautern]] |date=1983}}</ref> ABL was implemented in the early 1980s by the Centro Studi e Laboratori Telecomunicazioni ([[CSELT]]) in Torino, Italy, producing the ABLED graphic VLSI design editor. In the mid-1980s, a VLSI design framework was implemented around KARL and ABL by an international consortium funded by the Commission of the European Union.<ref name=Hartenstein93>{{citation|editor1-first=J.|editor1-last=Mermet|year=2012 |title=Fundamentals and Standards in Hardware Description Languages|publisher=Springer |orig-year=1993 |isbn=9789401119146 |chapter-url=https://books.google.com/books?id=DBrtCAAAQBAJ&pg=PA447 |first1=Reiner W. |last1=Hartenstein |chapter=KARL and ABL |pages=447– |volume=249 |series=NATO Science Series E}}</ref>

By the late 1970s, design using [[programmable logic device]]s (PLDs) became popular, although these designs were primarily limited to designing [[finite-state machine]]s. The work at [[Data General]] in 1980 used these same devices to design the [[Data General Eclipse MV/8000]], and commercial need began to grow for a language that could map well to them. By 1983 [[Data I/O]] introduced ABEL to fill that need.

In 1985, as design shifted to VLSI, [[Gateway Design Automation]] introduced [[Verilog]], and [[Intermetrics]] released the first completed version of the VHSIC Hardware Description Language ([[VHDL]]). VHDL was developed at the behest of the [[United States Department of Defense]]'s [[Very High Speed Integrated Circuit Program]] (VHSIC), and was based on the [[Ada (programming language)|Ada programming language]], and on the experience gained with the earlier development of ISPS.<ref>{{cite report |first1=M.C. |last1=Barbacci |last2=Grout |first2=S. |last3=Lindstrom |first3=G. |last4=Maloney |first4=M.P. |date=1984 |title=Ada as a hardware description language : an initial report |publisher=Department of Computer Science, Carnegie-Mellon University |doi=10.1184/R1/6602984.v1 |citeseerx=10.1.1.938.8003}}</ref> Initially, Verilog and VHDL were used to document and simulate circuit designs already captured and described in another form (such as [[schematic]] files). HDL simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic level, and thus increased design capacity from hundreds of transistors to thousands.{{Citation needed|date=July 2010}} In 1986, with the support of the U.S Department of Defense, [[VHDL]] was sponsored as an [[IEEE standard]] (IEEE Std 1076), and the first IEEE-standardized version of VHDL, IEEE Std 1076-1987, was approved in December 1987. [[Cadence Design Systems]] later acquired Gateway Design Automation for the rights to Verilog-XL, the HDL simulator that would become the de facto standard of [[Verilog simulators]] for the next decade.

The introduction of [[logic synthesis]] for HDLs pushed HDLs from the background into the foreground of digital design. Synthesis tools compiled HDL [[source files]] (written in a constrained format called RTL) into a manufacturable netlist description in terms of [[gate]]s and [[transistor]]s. Writing synthesizable RTL files required practice and discipline on the part of the designer; compared to a traditional schematic layout, synthesized RTL netlists were almost always larger in area and slower in performance{{Citation needed|date=July 2010}}. A circuit design from a skilled engineer, using labor-intensive schematic-capture/hand-layout, would almost always outperform its logically-synthesized equivalent, but the productivity advantage held by synthesis soon displaced digital schematic capture to exactly those areas that were problematic for RTL synthesis: extremely high-speed, low-power, or asynchronous circuitry.

Within a few years, VHDL and Verilog emerged as the dominant HDLs in the electronics industry, while older and less capable HDLs gradually disappeared from use. However, VHDL and Verilog share many of the same limitations, such as being unsuitable for analog or [[Mixed-signal integrated circuit|mixed-signal circuit]] simulation. Specialized HDLs (such as Confluence) were introduced with the explicit goal of fixing specific limitations of Verilog and VHDL, though none were ever intended to replace them.

Over the years, much effort has been invested in improving HDLs. The latest iteration of Verilog, formally known as IEEE 1800-2005 SystemVerilog, introduces many new features (classes, random variables, and properties/assertions) to address the growing need for better [[test bench]] randomization, design hierarchy, and reuse. A future revision of VHDL is also in development{{when|date=April 2014}}, and is expected to match SystemVerilog's improvements.

== Design using HDL ==

As a result of the efficiency gains realized using HDL, a majority of modern digital circuit design revolves around it. Most designs begin as a set of requirements or a high-level architectural diagram. Control and decision structures are often prototyped in [[flowchart]] applications, or entered in a editor. The process of writing the HDL description is highly dependent on the nature of the circuit and the designer's preference for coding style. The HDL is merely the 'capture language', often beginning with a high-level algorithmic description such as a C++ mathematical model. Designers often use scripting languages such as [[Perl]] to automatically generate repetitive circuit structures in the HDL language. Special text editors offer features for automatic indentation, syntax-dependent coloration, and [[Macro (computer science)|macro]]-based expansion of the entity/architecture/signal declaration.

The HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDL description is subject to an array of automated checkers. The checkers report deviations from standardized code guidelines, identify potential ambiguous code constructs before they can cause misinterpretation, and check for common logical coding errors, such as floating [[Port (circuit theory)|port]]s or [[short circuit|short]]ed outputs. This process aids in resolving errors before the code is synthesized.

In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis tool has mapped the HDL description into a gate netlist, the netlist is passed off to the back-end stage. Depending on the physical technology ([[Field-programmable gate array|FPGA]], [[Application-specific integrated circuit|ASIC]] [[gate array]], ASIC [[standard cell]]), HDLs may or may not play a significant role in the back-end flow. In general, as the design flow progresses toward a physically realizable form, the design database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL description. Finally, an integrated circuit is manufactured or programmed for use.

== Simulating and debugging HDL code ==

{{Main|Logic simulation}}

Essential to HDL design is the ability to simulate HDL programs. Simulation allows an HDL description of a design (called a model) to pass [[Functional verification|design verification]], an important milestone that validates the design's intended function (specification) against the code implementation in the HDL description. It also permits architectural exploration. The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design.

To simulate an HDL model, an engineer writes a top-level simulation environment (called a [[test bench]]). At minimum, a testbench contains an instantiation of the model (called the device under test or DUT), pin/signal declarations for the model's I/O, and a clock waveform. The testbench code is event driven: the engineer writes HDL statements to implement the (testbench-generated) reset-signal, to model interface transactions (such as a host–bus read/write), and to monitor the DUT's output. An HDL simulator — the program that executes the testbench — maintains the simulator clock, which is the master reference for all events in the testbench simulation. Events occur only at the instants dictated by the testbench HDL (such as a reset-toggle coded into the testbench), or in reaction (by the model) to stimulus and triggering events. Modern HDL simulators have full-featured [[graphical user interface]]s, complete with a suite of debug tools. These allow the user to stop and restart the simulation at any time, insert simulator breakpoints (independent of the HDL code), and monitor or modify any element in the HDL model hierarchy. Modern simulators can also link the HDL environment to user-compiled libraries, through a defined [[Verilog#Program Language Interface (PLI)|PLI]]/[[VHDL Programming Language Interface|VHPI]] interface. Linking is system-dependent ([[x86]], [[SPARC]] etc. running [[Microsoft Windows|Windows]]/[[Linux]]/[[Solaris (operating system)|Solaris]]), as the HDL simulator and user libraries are compiled and linked outside the HDL environment.

Design verification is often the most time-consuming portion of the design process, due to the disconnect between a device's [[functional specification]], the designer's interpretation of the specification, and the imprecision{{Citation needed|date=July 2010}} of the HDL language. The majority of the initial test/debug cycle is conducted in the HDL ''simulator'' environment, as the early stage of the design is subject to frequent and major circuit changes. An HDL description can also be prototyped and tested in hardware — [[programmable logic device]]s are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing against other hardware devices and hardware prototypes. Even those running on slow FPGAs offer much shorter simulation times than pure HDL simulation.

== Design verification with HDLs ==

{{Main|Functional verification}}

Historically, design verification was a laborious, repetitive loop of writing and running simulation [[test case]]s against the design under test. As chip designs have grown larger and more complex, the task of design verification has grown to the point where it now dominates the schedule of a design team. Looking for ways to improve design productivity, the [[electronic design automation]] industry developed the [[Property Specification Language]].

In [[formal verification]] terms, a property is a factual statement about the expected or assumed behavior of another object. Ideally, for a given HDL description, a property or properties can be proven true or false using formal mathematical methods. In practical terms, many properties cannot be proven because they occupy an unbounded [[solution space]]. However, if provided a set of operating assumptions or constraints, a property checker can prove (or disprove) certain properties by narrowing the solution space.

The assertions do not model circuit activity, but capture and document the designer's intent in the HDL code. In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon any violation. Assertion based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset.

== HDL and programming languages ==

An HDL is grossly similar to a software [[programming language]], but there are major differences. Most programming languages are inherently [[Procedural programming|procedural]] (single-threaded), with limited syntactical and semantic support to handle [[Concurrency (programming)|concurrency]]. HDLs, on the other hand, resemble [[concurrent programming]] languages in their ability to model multiple parallel processes (such as [[flip-flop (electronics)|flip-flops]] and [[adder (electronics)|adders]]) that automatically execute independently of one another. Any change to the process's input automatically triggers an update in the simulator's process stack.

Both programming languages and HDLs are processed by a compiler (often called a synthesizer in the HDL case), but with different goals. For HDLs, "compiling" refers to [[logic synthesis]]; the process of transforming the HDL code listing into a physically realizable gate [[netlist]]. The netlist output can take any of many forms: a "simulation" netlist with gate-delay information, a "handoff" netlist for post-synthesis [[place and route|placement and routing]] on a semiconductor die, or a generic industry-standard [[Electronic Design Interchange Format]] (EDIF) (for subsequent conversion to a [[JEDEC]]-format file).

On the other hand, a software compiler converts the source-code listing into a [[microprocessor]]-specific object code for execution on the target microprocessor. As HDLs and programming languages borrow concepts and features from each other, the boundary between them is becoming less distinct. However, pure HDLs are unsuitable for general purpose [[application software]] development,{{Why|date=December 2018}} just as [[general-purpose programming language]]s are undesirable for modeling hardware.

Yet as electronic systems grow increasingly complex, and [[reconfigurable system]]s become increasingly common, there is growing desire in the industry for a single language that can perform some tasks of both hardware design and software programming. [[SystemC]] is an example of such—[[embedded system]] hardware can be modeled as non-detailed architectural blocks ([[black box]]es with modeled signal inputs and output drivers). The target application is written in C or C++ and natively compiled for the host-development system; as opposed to targeting the embedded CPU, which requires host-simulation of the embedded CPU or an emulated CPU.

The high level of abstraction of SystemC models is well suited to early [[Design space exploration|architecture exploration]], as architectural modifications can be easily evaluated with little concern for signal-level implementation issues. However, the threading model used in SystemC relies on [[shared memory]], causing the language not to handle parallel execution or low-level models well.

==High-level synthesis==
{{Main|High-level synthesis}}
In their level of abstraction, HDLs have been compared to [[assembly language]]s.{{citation needed|date=April 2014}} There are attempts to raise the abstraction level of hardware design in order to reduce the complexity of programming in HDLs, creating a sub-field called ''[[high-level synthesis]]''.

Companies such as [[Cadence Design Systems|Cadence]], [[Synopsys]] and Agility Design Solutions are promoting [[SystemC]] as a way to combine high-level languages with concurrency models to allow faster design cycles for [[FPGA]]s than is possible using traditional HDLs. Approaches based on standard [[C (programming language)|C]] or [[C++]] (with libraries or other extensions allowing parallel programming) are found in the [[Catapult C]] tools from [[Mentor Graphics]], and the [[Impulse C]] tools from Impulse Accelerated Technologies.

A similar initiative from Intel is the use of Data Parallel C++, related to [[SYCL]], as a high-level synthesis language.

[https://www.annapmicro.com/ Annapolis Micro Systems], Inc.'s CoreFire Design Suite<ref>{{Cite news|url=https://www.annapmicro.com/products/corefire-next/|title=VHDL-Based FPGA Programming Application Software Tool|work=Annapolis Micro Systems, Inc.|access-date=2018-12-01|language=en-US}}</ref> and [[National Instruments]] LabVIEW FPGA provide a graphical [[dataflow]] approach to high-level design entry and languages such as [[SystemVerilog]], SystemVHDL, and [[Handel-C]] seek to accomplish the same goal, but are aimed at making existing hardware engineers more productive, rather than making FPGAs more accessible to existing [[software engineer]]s.

It is also possible to design hardware modules using [[MATLAB]] and [[Simulink]] using the [[MathWorks]] HDL Coder tool<ref>{{cite web|url=http://www.mathworks.com/products/hdl-coder/ |title=VHDL code - HDL Coder - MATLAB & Simulink |publisher=Mathworks.com |date=2011-04-30 |access-date=2012-08-11}}</ref> or DSP Builder for Intel FPGAs<ref>{{Cite web|title=Digital Signal Processing (DSP) Builder - Intel® FPGAs|url=https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/dsp-builder.html|access-date=2021-09-20|website=Intel|language=en}}</ref> or Xilinx System Generator (XSG) from [[Xilinx]].<ref>{{cite web |url=http://www.xilinx.com/tools/sysgen.htm |title=System Generator for DSP |publisher=Xilinx.com |access-date=2012-08-11 |url-status=dead |archive-url=https://web.archive.org/web/20120712224415/http://www.xilinx.com/tools/sysgen.htm |archive-date=2012-07-12 }}</ref>

== Examples of HDLs ==
=== HDLs for analog circuit design ===

{| class="sortable wikitable"
|-
! Name
! Description
|-
| [[HDL-A]]
| A proprietary analog HDL
|-
| SpectreHDL
| A proprietary analog HDL from [[Cadence Design Systems]] for its Spectre circuit simulator
|-
| [[Verilog-AMS]] (Verilog for Analog and Mixed-Signal)
| An [[Accellera]] standard extension of IEEE&nbsp;Std&nbsp;1364 [[Verilog]] for analog and mixed-signal simulation
|-
| [[VHDL-AMS]] (VHDL with Analog/Mixed-Signal extension)
| An [[IEEE Standards Association|IEEE standard]] extension (IEEE&nbsp;Std&nbsp;1076.1) of [[VHDL]] for analog and mixed-signal simulation
|}

=== HDLs for digital circuit design ===

The two most widely used and well-supported HDL varieties used in industry are [[Verilog]] and [[VHDL]].

{| class="sortable wikitable"
|-
! Status
! Name
! Host [[Programming language|language]]
! Description
|-
! rowspan="47" |In use
| [[Altera Hardware Description Language]] (AHDL)
|
| [[Proprietary software|Proprietary]] language from [[Altera]]
|-
| A Hardware Programming language ([[AHPL]])
|
| Used as a tool for teaching
|-
| [https://github.com/amaranth-lang/amaranth Amaranth]
| [[Python (programming language)|Python]]
|
|-
| [[Bluespec]]
|
| High-level HDL based on [[Haskell]] (not embedded [[Domain-specific language|DSL]])<ref>''A History of Haskell: being lazy with class'' §12.4.2</ref>
|-
| [[Bluespec]] [[SystemVerilog]] (BSV)
|
| Based on [[Bluespec]], with [[Verilog]] HDL like syntax, by Bluespec, Inc.
|-
| C-to-Verilog
|
| Converter from C to Verilog
|-
| [[Chisel (programming language)|Chisel]] (Constructing Hardware in a Scala Embedded Language)<ref>{{Cite web |url=https://www.chisel-lang.org/ |title=Chisel/FIRRTL Hardware Compiler Framework}}</ref>
| [[Scala (programming language)|Scala]]
| Based on [[Scala (programming language)|Scala]] (embedded [[Domain-specific language|DSL]])
|-
| [https://clash-lang.org/ Clash] 
|
| Functional hardware description language that borrows its syntax and semantics from the functional language [[Haskell]]
|-
| Common Oriented Language for Architecture of Multi Objects (COLAMO)<ref>[https://web.archive.org/web/20091109155107/http://colamo.parallel.ru/ COLAMO]</ref><ref>{{Cite web |url=http://superevm.ru/index.php?page=higher-level-language-colamo |title=Higher-level language COLAMO – НИЦ супер-ЭВМ и нейрокомпьютеров}}</ref>
|
| [[Proprietary software|Proprietary]] language from “Supercomputers and Neurocomputers Research Center” Co Ltd.
|-
| Compiler for Universal Programmable Logic (CUPL)<ref>{{Cite journal |last1=Eurich |first1=J.P. |last2=Roth |first2=G. |year=1990 |title=EDIF grows up |journal=IEEE Spectrum |volume=27 |issue=11 |pages=68–72 |doi=10.1109/6.62219 |s2cid=381119}}</ref>
|
| [[Proprietary software|Proprietary]] language from Logical Devices, Inc.
|-
| [https://google.github.io/xls/dslx_reference DSLX]
|
| [[Domain-specific language]] for XLS toolchain
|-
| ESys.net
|
| [[.NET]] framework written in C#
|-
|[https://filamenthdl.com/ Filament]
|
|HDL with a type system inspired by Rust
|-
| [[Handel-C]]
|
| C-like design language
|-
| [https://github.com/ujamjar/hardcaml Hardcaml]
| [[OCaml]]
| Based on [[OCaml]] (embedded DSL)<ref>[http://www.ujamjar.com/hardcaml/ Hardcaml]</ref>
|-
| HHDL
| [[Haskell]]
| Based on [[Haskell]] (embedded DSL)
|-
| Hardware [[Join-pattern|Join Java]] (HJJ)
| [[Join-pattern|Join Java]]
| Based on [[Join-pattern|Join Java]]
|-
| Hardware ML (HML)
| [[Standard ML]]
| Based on [[Standard ML]]<ref>{{Cite book |last1=Li |first1=Yanbing |last2=Leeser |first2=M. |year=1995 |chapter=HML: An innovative hardware description language and its translation to VHDL |title=Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair |pages=691–696 |doi=10.1109/ASPDAC.1995.486388 |isbn=4-930813-67-0 |s2cid=14198160}}</ref>
|-
| Hydra
| [[Haskell]]
| Based on [[Haskell]]
|-
| [[Impulse C]]
|
| C-like HDL
|-
| Parallel C++ (ParC)
|
| kusu extended with HDL style threading and communication for task-parallel programming
|-
| JHDL
| [[Java (programming language)|Java]]
| Based on [[Java (programming language)|Java]]
|-
| Lava
| [[Haskell]]
| Based on [[Haskell]] (embedded DSL)<ref>[http://hackage.haskell.org/package/chalmers-lava2000 Chalmers Lava]</ref><ref>[http://hackage.haskell.org/package/xilinx-lava Xilinx Lava]</ref><ref>[http://hackage.haskell.org/package/kansas-lava Kansas Lava]</ref><ref>[http://hackage.haskell.org/package/york-lava York Lava]</ref>
|-
| [[Lola (hardware description language)|Lola]]
|
| Simple language used for teaching
|-
| [[M (HDL)|M]]
|
| HDL from [[Mentor Graphics]]
|-
| [https://github.com/m-labs/migen Migen]
| [[Python (programming language)|Python]]
|
|-
| [[MyHDL]]
| [[Python (programming language)|Python]]
| Based on [[Python (programming language)|Python]] (embedded [[Domain-specific language|DSL]])
|-
| [[PALASM]]
|
| For [[Programmable Array Logic]] (PAL) devices
|-
| [https://github.com/JulianKemmerer/PipelineC PipelineC]
|
| C-like hardware description language adding [[High-level synthesis]]-like automatic pipelining as a language construct and compiler feature.
|-
| [https://github.com/pymtl/pymtl3 PyMTL 3 (Mamba)]
| [[Python (programming language)|Python]]
| Based on Python, from Cornell University
|-
| [https://ucsbarchlab.github.io/PyRTL/ PyRTL]
| [[Python (programming language)|Python]]
| Based on Python, from University of California, Santa Barbara
|-
| Riverside Optimizing Compiler for Configurable Computing (ROCCC)
|
| Free and open-source C to HDL tool
|-
| RHDL
| [[Ruby (programming language)|Ruby]]
| Based on the [[Ruby (programming language)|Ruby programming language]]
|-
| Rapid Open Hardware Development (ROHD)<ref>{{Cite web |url=https://github.com/intel/rohd |title=Rapid Open Hardware Development (ROHD) Framework
| website=[[GitHub]]
| date=17 November 2021
}}</ref>
| [[Dart (programming language)|Dart]]
| [[Software framework|Framework]] for hardware design and verification, written in [[Dart (programming language)|Dart]]
|-
| [[Ruby (hardware description language)]]
|
|
|-
| [https://github.com/sylefeb/Silice Silice]
|
| HDL that simplifies designing hardware algorithms with parallelism and pipelines
|-
| [https://spade-lang.org/ Spade]
|
| HDL inspired by modern software languages like Rust
|-
| [[SystemC]]
|
| Standardized class of [[C++]] libraries for high-level behavioral and transaction modeling of [[digital hardware]] at a high level of abstraction, i.e., system-level
|-
| [[SystemVerilog]]
|
| Superset of Verilog, with enhancements to address system-level design and verification
|-
| [https://github.com/SpinalHDL/SpinalHDL SpinalHDL]
| [[Scala (programming language)|Scala]]
| Based on Scala (embedded DSL)
|-
| SystemTCL
|
| SDL based on Tcl
|-
| Templated HDL inspired by C++ (THDL++)
|
| Extension of VHDL with inheritance, advanced templates and policy classes
|-
| [https://github.com/frwang96/verik Verik]
|
| [[Kotlin (programming language)|Kotlin]] reinterpreted with the semantics of an HDL; transpiled to [[SystemVerilog]]
|-
| Transaction-Level Verilog (TL-Verilog)<ref>[http://www.tl-x.org TL-Verilog]</ref>
|
| Extension of Verilog/[[SystemVerilog]] with constructs for [[Pipeline (computing)|pipelines]] and [[Transactional memory|transactions]].
|-
| [[Verilog]]
|
| One of the most widely used and well-supported HDLs
|-
| [https://veryl-lang.org/ Veryl]
|
| HDL designed as SystemVerilog alternative
|-
| [[VHDL]] ([[VHSIC]] HDL)
|
| One of the most widely used and well-supported HDLs
|-
! rowspan="7" |No longer in common use
| [[Advanced Boolean Expression Language]] (ABEL)
|
| Obsolete HDL made by [[Data I/O Corporation]] in 1983
|-
| Confluence
|
| Functional HDL, discontinued
|-
| CoWareC
|
| C-based HDL by [[CoWare]]; discontinued in favor of SystemC
|-
| [[ELLA (programming language)|ELLA]]
|
| No longer in common use
|-
| ISPS
|
| Original HDL from CMU; no longer in common use
|-
| KAiserslautern Register Language (KARL)<ref name="Hartenstein93"/>
|
| [[Pascal (programming language)|Pascal]]-like hardware description language; no longer in common use
|-
| [https://gitlab.com/nmigen/nmigen nMigen]
| [[Python (programming language)|Python]]
| Predecessor to Amaranth
|}

=== HDLs for printed circuit board design ===

Several projects exist for defining [[printed circuit board]] connectivity using language based, textual-entry methods. Among these, new approaches have emerged that focus on enhancing readability, reusability, and validation. These modern methodologies employ open-source design languages specifically tailored for electronics, adopting declarative markup to specify what circuits should achieve. This shift integrates software development principles into hardware design, streamlining the process and emphasizing automation, reuse, and validation.

{| class="sortable wikitable"
|-
! Name
! Description
|-
| [https://github.com/atopile/atopile atopile]
| An open-source language and toolchain to describe electronic circuit boards with code.
|-
| [[PHDL]] (PCB HDL)
| A free and open source HDL for defining printed circuit board connectivity.
|-
| EDAsolver
| An HDL for solving schematic designs based on constraints.
|-
| [https://github.com/xesscorp/skidl SKiDL]
| Open source Python module to design electronic circuits.
|}

== See also ==
{{cmn|
*[[Bluespec]]
*[[C to HDL]]
*[[Flow to HDL]]
*[[Gezel]]
*[[Hardware verification language]]
*[[Modeling language]]
*[[Property Specification Language]]
*[[Rosetta-lang]]
*[[Specification language]]
*[[SystemC]]
*[[SystemVerilog]]
}}

== References ==

{{Reflist}}

==External links==
{{Commonscat}}
*[http://hct.sourceforge.net/ HCT] - The HDL Complexity tool, used to determine design complexity.

{{Computer language}}
{{Programmable Logic}}
{{Digital electronics}}
{{Authority control}}

{{DEFAULTSORT:Hardware Description Language}}
[[Category:Hardware description languages| ]]
[[Category:Technical communication]]
[[Category:Logic design]]
[[Category:Programming language classification]]