Editing IBM ROMP

{{Other uses|Romp (disambiguation){{!}}Romp}}
{{Infobox CPU architecture
| name = ROMP
| designer = [[IBM]]
| bits = [[32-bit computing|32-bit]]
| introduced = commercially {{Start date and age|1986|01}}
| design = [[Reduced instruction set computer|RISC]]
| type = [[Load–store]]
| encoding = Variable (2 or 4 bytes long)
| branching = [[Status register|Condition code]]
| endianness = 
| page size = 4 KB
| open = No
| gpr = 16× 32-bit
}}
[[Image:Romp.jpg|thumb|150px|right|ROMP]]
The '''ROMP''' is a [[reduced instruction set computer]] (RISC) [[microprocessor]] designed by [[IBM]] in the late 1970s. It is also known as the '''Research OPD Miniprocessor''' (after the two IBM divisions that collaborated on its inception, [[IBM Research]] and the Office Products Division (OPD)) and '''032'''.<ref>{{cite magazine |last=Heberlein |first=Larry |title=A programmer's view of the PC RT chip |magazine=Computer Language |volume=3 |issue=10 |date=October 1986 |pages=41–46}}</ref> The ROMP was originally developed for office equipment and small computers,<ref>{{cite book |last1=Hester |first1=P.D. |last2=Simpson |first2=Richard O. |last3=Chang |first3=Albert<!-- Citation bot-->|url=http://bitsavers.org/pdf/ibm/pc/rt/SA23-1057_IBM_RT_Personal_Computer_Technology_1986.pdf|chapter=The IBM RT PC ROMP and Memory Management Unit Architecture|title=The IBM RT Personal Computer Technology, Form No. SA23-1057|editor-first=Frank|editor-last=Waters|page=48}}</ref> intended as a follow-on to the mid-1970s IBM [[OPD Mini Processor]] microprocessor,{{citation needed|date=March 2012}} which was used in the [[IBM Office System/6]] word-processing system. The first examples became available in 1981, and it was first used commercially in the [[IBM RT PC]] announced in January 1986. For a time, the RT PC was planned to be a [[personal computer]], with ROMP replacing the [[Intel 8088]] found in the [[IBM Personal Computer]]. However, the RT PC was later repositioned as an engineering and scientific [[workstation computer]]. A later [[CMOS]] version of the ROMP was first used in the [[coprocessor]] board for the [[IBM 6152 Academic System]] introduced in 1988, and it later appeared in some models of the RT PC.

==History==
The [[Instruction set architecture|architectural]] work on the ROMP began in late spring of 1977, as a spin-off of [[IBM Research]]'s [[IBM 801|801]] RISC processor (hence the "Research" in the acronym). Most of the architectural changes were for cost reduction, such as adding 16-bit instructions for byte-efficiency. The original ROMP had a 24-bit architecture, but the instruction set was changed to 32 bits a few years into the development.<ref>{{cite book<!-- Citation bot-->|url=http://bitsavers.org/pdf/ibm/pc/rt/SA23-1057_IBM_RT_Personal_Computer_Technology_1986.pdf|first1=D.E.|last1=Waldecker|first2=P.Y.|last2=Woon|chapter=ROMP/MMU Technology Introduction|title=The IBM RT Personal Computer Technology, Form No. SA23-1057|editor-first=Frank|editor-last=Waters|page=44}}</ref>

The first chips were ready in early 1981, making ROMP the first industrial RISC. The processor was revealed at the [[International Solid-State Circuits Conference]] in 1984<ref name="Bambrick" /> ROMP first appeared in a commercial product as the processor for the [[IBM RT PC]] [[workstation]], which was introduced in 1986. To provide examples for RT PC production, volume production of the ROMP and its MMU began in 1985.<ref name="Bambrick" /> The delay between the completion of the ROMP design, and introduction of the RT PC was caused by overly ambitious software plans for the RT PC and its [[operating system]] (OS). This OS virtualized the hardware and could host multiple other operating systems. This technology, called [[Partial virtualization|virtualization]], while commonplace in [[Mainframe computer|mainframe]] systems, only began to gain traction in smaller systems in the 21st century. An improved CMOS version of the ROMP was first used in the [[IBM 6152 Academic System]] workstation, and later in some models of the RT PC.

[[IBM Research]] used the ROMP in its Research Parallel Processor Prototype (RP3), an early experimental scalable [[shared-memory multiprocessor]] that supported up to 512 processors first detailed in 1985; and the CMOS version in its ACE, an experimental NUMA multiprocessor that was operational in 1988.<ref>{{cite book |last1=Lerman |first1=G. |last2=Rudolph |first2=L. |title=Parallel Evolution of Parallel Processors |url=https://archive.org/details/parallelevolutio00lerm |url-access=limited |date=1993 |publisher=Springer Science & Business Media |isbn=9781461528562 |page=[https://archive.org/details/parallelevolutio00lerm/page/n152 146]}}</ref>

==Architecture==
The ROMP's architecture was based on the original version of the [[IBM Research]] [[IBM 801|801]] [[minicomputer]]. The main differences were a larger [[word size]] (32 bits instead of 24), and the inclusion of [[virtual memory]].<ref>{{cite book |last1=Dewar |first1=Robert B.K. |last2=Smosna |first2=Matthew |title=Microprocessors: A Programmer's View |publisher=McGraw-Hill |page=378}}</ref> The architecture supported 8-, 16-, and 32-bit integers, 32-bit addressing, and a 40-bit [[virtual address space]]. It had an [[instruction pointer]] register and sixteen 32-bit [[general-purpose register]]s. The microprocessor was controlled by 118 simple 16- and 32-bit instructions.<ref name="Furber">{{cite book |last1=Furber |first1=Stephen |title=VLSI RISC Architecture and Organization |date=1989 |publisher=CRC Press |pages=106–109 |url=https://books.google.com/books?id=jKOsdJ8Rk6EC|isbn=9780824781514}}</ref>

The ROMP's virtual memory has a [[Memory segmentation|segmented]] 40-bit (1{{nbsp}}TB) address space consisting of 4,096 256{{nbsp}}MB segments. The 40-bit virtual address is formed in the MMU by [[Concatenation|concatenating]] a 12-bit segment identifier with 28 low-order bits from a 32-bit ROMP-computed virtual address. The segment identifier is obtained from a set of 16 segment identifiers stored in the MMU, addressed by the four high-order bits of the 32-bit ROMP-computed virtual address.<ref>{{cite book |last1=Tabak |first1=Daniel |title=RISC Architecture |date=1987 |publisher=Research Studies Press |pages=102–103}}</ref>

==Implementation==
The ROMP is a [[scalar processor]] with a three-stage pipeline.<ref name="Furber"/> In the first stage, if there are instructions in the 16-byte instruction prefetch buffer, an instruction was fetched, decoded, and operands from the general-purpose register file read. The instruction prefetch buffer read a 32-bit word from the memory whenever the ROMP was not accessing it.<ref name="Furber"/> Instructions were executed in the second stage, and written back into the general-purpose register file in the third stage. The ROMP used a bypass network and appropriately scheduled the register file reads and writes to support back-to-back execution of dependent instructions.<ref name="Furber"/> Most register-to-register instructions were executed in one cycle; of the 118 instructions, 84 had a single-cycle latency.<ref name="Seymour_1986-06-10">{{cite magazine |last=Seymour |first=Jim |date=10 June 1986 |title=RISC Architecture |magazine=[[PC Magazine]] |page=113}}</ref> The ROMP had an IBM-developed companion [[integrated circuit]] which was code-named Rosetta during development.<ref>{{cite magazine |last=Chandler |first=David |title=The ROMP Is Not Just A Lark |magazine=UNIX Review |date=1986}}</ref> Rosetta was a [[memory management unit]] (MMU), and it provided the ROMP with address translation facilities, a [[translation lookaside buffer]], and a store buffer.<ref name="Furber"/>

The ROMP and Rosetta were originally implemented in an IBM 2{{nbsp}}μm [[silicon-gate]] [[n-channel|NMOS technology]] with two levels of metal interconnect.<ref name="IBM_book">{{cite book |editor-first=Frank |editor-last=Waters |title=The IBM RT Personal Computer Technology |page=8}}</ref><ref name="Bambrick">{{cite magazine |last=Bambrick |first=Richard |date=27 January 1986 |title=IBM's New RISC Processor Based on 10-Year Project |magazine=[[Electronic News]]}}</ref> The ROMP consists of 45,000 transistors and is 7.65{{nbsp}}×{{nbsp}}7.65{{nbsp}}mm large (58.52{{nbsp}}mm<sup>2</sup>), while Rosetta consists of 61,500 transistors and is 9.02{{nbsp}}×{{nbsp}}9.02{{nbsp}}mm large (81.36{{nbsp}}mm<sup>2</sup>). Both are packaged in 135-pin [[ceramic pin grid array]]s.<ref name="Bambrick" /> A CMOS version of the ROMP and Rosetta (called ROMP-C and Rosetta-C) was later developed.

==References==
{{Reflist}}

==External links==
*[https://ieeexplore.ieee.org/document/5387644 The IBM RT PC ROMP processor and memory management unit architecture]

{{RISC architectures}}

[[Category:IBM microprocessors]]