Editing IBM System/4 Pi

{{Short description|Family of avionics computers}}
{{More footnotes|date=May 2018}}
[[File:Space Shuttle General Purpose Computer.jpg|thumb|The IBM AP-101B CPU and I/O processor (right) and AP-101S (left)]]
The [[IBM]] '''System/4 Pi''' is a family of [[avionics]] [[computer]]s used, in various versions, on the [[F-15 Eagle]] fighter, [[E-3 Sentry]] AWACS, [[Harpoon (missile)|Harpoon Missile]], [[NASA]]'s [[Skylab]], [[Manned Orbital Laboratory|MOL]], and the [[Space Shuttle program|Space Shuttle]], as well as other aircraft. Development began in 1965, deliveries in 1967.{{sfn|IBM|1967|p=1-3 (9)}} They were developed by the [[IBM Federal Systems Division]] and produced by the Electronics Systems Center  in Owego, NY.{{sfn|IBM|1967|p=iv}}

It descends from the approach used in the [[System/360]] [[IBM mainframe|mainframe]] family of computers, in which the members of the family were intended for use in many varied user applications. (This is expressed in the name: there are 4[[Pi|π]] [[steradians]] in a sphere, just as there are 360 [[Degree (angle)|degrees]] in a circle.{{sfn|IBM|1967|loc=Foreword, p. iii/iv (6)}})  Previously, custom computers had been designed for each aerospace application, which was extremely costly.

== Early models ==
In 1967, the System/4 Pi family consisted of these basic models:{{sfn|IBM|1967}}<ref>{{cite book |last1=Bedford |first1=D. P. |last2=Markarian |first2=H. |last3=Pleszkoch |first3=N. L. |title=Study of control computers for control moment gyro stability and control systems. Volume I - Engineering |date=Mar 1967 |pages=E-1 - E-21 (126-147) |chapter-url=https://ntrs.nasa.gov/search.jsp?print=yes&R=19670020826 |chapter=Appendix E: SYSTEM 4 Pi COMPUTER CHARACTERISTICS|others=Model TC and CP-2}}</ref>

{| class="wikitable" style="text-align: right; float:right; margin-left: 10px;"
|+ Specifications{{sfn|IBM Overview}}
|-
! Model !! [[Instruction set architecture|ISA]] <br>(instructions) !! [[Instructions per second|Performance]] <br>(IPS) || Weight <br>(pounds)
|-
| style="text-align: left | TC || 54 || 48,500 || {{convert|17.3|lb|kg}}
|-
| style="text-align: left | CP || 36 || 91,000 || {{convert|80|lb|kg}}
|-
| style="text-align: left | CP-2 || 36 || 125,000 || {{convert|47|lb|kg}}
|-
| style="text-align: left | EP || 70 || 190,000 || {{convert|75|lb|kg}}
|}

* Model TC (Tactical Computer){{sfn|IBM|1967|loc=Section 2: Model TC, pp. 2-1 - 2-13/2-14 (20-32)}}{{sfn|IBM Overview|loc=Model TC, pp. -2-13 (1-16)}} - A briefcase-size computer for applications such as missile guidance, helicopters, satellites and submarines.
* Model CP (Customized Processor/Cost Performance){{sfn|IBM|1967|loc=Section 3: Model CP, pp. 3-1 - 3-9/3-10 (33-41)}}{{sfn|IBM Overview|loc=Model CP, pp. -3-15 (17-35)}} - An intermediate-range processor for applications such as aircraft navigation, weapons delivery, radar correlation and mobile battlefield systems.{{sfn|IBM Overview|loc=Model CP, p. 3 (23)}}
** Model CP-2 (Cost Performance - Model 2){{sfn|IBM Overview|loc=Model CP-2, pp. -2-13 (36-51)}}
* Model EP (Extended Performance){{sfn|IBM|1967|loc=Section 4: Model EP, pp. 4-1 - 4-13/4-14 (42-54)}}{{sfn|IBM Overview|loc=Model EP, pp. -2-18 (52-72)}} - A large-scale data processor for applications requiring real-time processing of large volumes of data, such as crewed spacecraft, airborne warning and control systems and command and control systems. Model EP used an instruction subset of IBM System/360<ref>{{cite book|chapter-url=https://archive.org/details/bitsavers_ibm4pi4PIEcationNov1966_12400348|title=System/4 Pi Engineering Description: Model EP|author=<!--Staff writer(s); no by-line.-->|date=1966|publisher=Federal Systems Division of IBM|location=Owego, NY|chapter=''1.1 System/360 Compatibility'' and ''2.2 System/360 Compatibility''|pages=1, 4-5 (6, 9-10)}}</ref> ([[IBM System/360 Model 44|Model 44]]){{sfn|IBM Overview|loc=Model EP: Summary, p. 2 (56)}} - user programs could be checked on System/360

The Skylab space station employed the model TC-1,<ref>{{cite web |url=https://history.nasa.gov/sts1/pages/computer.html |title=Advanced Vehicle Automation and Computers Aboard the Shuttle |last1=Jenkins |first1=Dennis |date=April 5, 2001  |website=NASA History Homepage |publisher=NASA |access-date=27 October 2013}}</ref> which had a [[16-bit]] [[Word (data type)|word length]] and 16,384 words of memory with a custom input/output assembly. Skylab had two, redundant, TC-1 computers: a prime (energized) and a backup (non energized.) There would be an automatic switchover (taking on the order of one second) to the backup in the event of a critical failure of the prime.<ref>{{cite journal |doi=10.1147/rd.201.0005 |title=Development of On-board Space Computer Systems |date=1976 |last1=Cooper |first1=A. E. |last2=Chow |first2=W. T. |journal=IBM Journal of Research and Development |volume=20 |pages=5–19 }}</ref> A total of twelve were delivered to NASA by 1972. Two were flown on Skylab in 1973-1974; the others were used for testing and mission simulators.<ref name=Tomayko1988 /> The software management effort was led by [[Harlan Mills]] and [[Fred Brooks]]. The Skylab flight software development process incorporated many lessons learned during the [[IBM System/360 Operating System]] project, as described in Brooks' 1975 book ''[[The Mythical Man-Month]]''.<ref name=Tomayko1988 />

==Advanced Processor==
The '''AP-101''', being the top-of-the-line of the System/4 Pi range, shares its general architecture with the [[System/360]] [[IBM mainframe|mainframe]]s.<ref name=Tomayko1988 /> It is a repackaged version of the IBM Advanced Processor-1 (AP-1)<ref name=F15 /> used in the [[F-15 Eagle|F-15]] fighter.<ref name=Tomayko1988 /> The AP-1 prototypes were delivered in 1971 and the AP-101 in 1973.<ref name=IBM1981 /> It has 16 [[32-bit]] [[processor register|registers]].  Originally only 16 bits were available for addressing memory; later this was extended with four bits from the [[status register|program status word]] register, allowing a directly addressable memory range of 1[[Mega-|M]] locations. This [[avionics]] computer has been used in the U.S. [[Space Shuttle program|Space Shuttle]], the [[B-52 Stratofortress|B-52]] and [[B-1B]] bombers,<ref name=Tomayko1988 /> and other aircraft. It remained in service on the Space Shuttle because it worked, was flight-certified, and developing a new system would have been too expensive.<ref>{{cite web |first=Ben |last=Rossi |title=The shuttle: NASA's IT legacy |date=18 July 2011 |publisher=Information Age |url=https://www.information-age.com/the-shuttle-nasas-it-legacy-1641693/}}</ref>

There were a number of variants of the AP101. The Offensive Avionics System, a retrofit update of the B-52, contains two AP-101C computers.<ref>{{cite report |last=Gross |first=James P. |author-link= |date=February 1981 |title=Techniques for Interfacing Multiplex Systems |url=https://apps.dtic.mil/sti/pdfs/ADA101457.pdf |publisher=Air Force Systems Command |page= |docket= |access-date= |quote=}}</ref> The AP-101C prototypes were delivered in 1978.<ref name=IBM1981 /> The B-1B employs a network of eight model AP-101F computers.<ref>{{cite book |last1=Stormont |first1=D.P. |last2=Welgan |first2=R. |title=Proceedings of National Aerospace and Electronics Conference (NAECON'94) |chapter=Risk management for the B-1B computer upgrade |date=23–27 May 1994 |chapter-url= https://zenodo.org/record/1232223|volume=2 |pages=1143–1149 |doi=10.1109/NAECON.1994.332913 |isbn=0-7803-1893-5 |s2cid=109575632 }}<!--|access-date=23 October 2013--></ref> The Space Shuttle used two variants of the AP-101: the earlier AP-101B and the upgraded AP-101S. The AP-101B was used for a series of [[Approach and Landing Tests]] in 1977. The [[STS-1|first ascent to orbit]] was in 1981. The AP-101S [[STS-101|first launched in 2000]].

[[File:IBM AP-101S logic board.jpg|thumb|Logic board from an IBM AP-101S Space Shuttle General Purpose Computer.]] Each AP-101 on the Shuttle was coupled with an [[I/O processor|input-output processor]] (IOP), consisting of one Master Sequence Controller (MSC) and 24 Bus Control Elements (BCEs).  The MSC and BCEs executed programs from the same memory system as the main CPU, offloading control of the Shuttle's serial data bus system from the CPU. The AP-101B originally used in the Space Shuttle had [[magnetic-core memory]]. The upgrade to the AP-101S in the early 1990s replaced the core with [[semiconductor memory]] and reduced the size from two to one chassis.<ref name=AP101S /> It was augmented by [[glass cockpit]] technology. Both variants use a [[microprogram]] to define the [[instruction set]] architecture. The early AP-101 variants used IBM'S Multipurpose Midline Processor (MMP) architecture.<ref name=MMP /> The AP-101B microprogram implemented MMP with 154 instructions. The AP101S could operate with a backwards compatible MMP with 158 instructions or the [[MIL-STD-1750A]] architecture with 243 instructions.<ref name=AP101S /> It was based on the AP-101F used in the B-1B. The AP-101S/G was an interim processor. The AP-101B performance was 0.420 [[Instructions_per_second#Millions_of_instructions_per_second_(MIPS)|MIPS]], while the AP-101S was 1.27 MIPS.<ref name=AP101S /> James E. Tomayko, who was contracted by NASA to write a history of computers in spaceflight,  has said:<ref name=Tomayko1985 /> {{blockquote|text="It was available in basically its present form when NASA was specifying requirements for the shuttle contracts in the 1970s. As such, it represents the first manned spacecraft computer system with hardware intentionally behind the state of the art."}}

The Space Shuttle used five AP-101 computers as ''General-Purpose Computers'' (GPCs). Four operated in sync, for redundancy, while the fifth was a backup running software written independently. The Shuttle's [[guidance, navigation and control]] software was written in [[HAL/S]], a special-purpose [[high-level programming language]], while much of the operating system and low-level utility software was written in [[assembly language]]. AP-101s used by the [[US Air Force]] are mostly programmed in [[JOVIAL]], such as the system found on the B-1B bomber.<ref>[https://web.archive.org/web/20121012015607/http://business.highbeam.com/438317/article-1G1-3161147/jovial-smooth-us-air-force-shift-ada Jovial to smooth U.S. Air Force shift to Ada. (processing language)]</ref>

The AP-102 variant design began in 1984. It is a MIL-STD-1750A standard instruction set architecture. It was first used in the [[Lockheed F-117 Nighthawk|F-117A Nighthawk]]. It was upgraded to the AP-102A in the early 1990s.<ref name=AP102 />

==References==
{{reflist | refs=
<ref name=Tomayko1988>{{cite report |author=James E. Tomayko |author-link= |date=March 1988 |title=Computers in Spaceflight: The NASA Experience |url=https://www.hq.nasa.gov/office/pao/History/computers/contents.html |archive-url=https://web.archive.org/web/20210828132457/https://www.hq.nasa.gov/office/pao/History/computers/contents.html |archive-date=28 August 2021 |publisher=NASA Scientific and Technical Division |page= |id=NASA Contractor Report 182505 |access-date=17 November 2024}}</ref>
<ref name=F15>{{cite journal |last1=McTigue |first1=T. V. |date=December 1976 |title=F-15 Computational Subsystem |url=https://arc.aiaa.org/doi/abs/10.2514/3.58734 |journal=Journal of Aircraft |volume=13 |issue=12 |pages=945–947 |doi=10.2514/3.58734 |access-date=18 November 2024 |url-access=subscription}}</ref>
<ref name=AP101S>{{Citation
 | title = The new AP101S General-Purpose Computer (GPC) for the Space Shuttle
 | year = 1987
 | author = Norman, P. Glenn
 | journal = IEEE Proceedings
 | pages = 308–319
 | volume = 75
 | issue = 3
 | doi = 10.1109/PROC.1987.13738
| bibcode = 1987IEEEP..75..308N
 | s2cid = 19179436
 }}</ref>
<ref name=Tomayko1985>{{cite journal |last1=Tomayko |first1=James E. |date=January 1985 |title=NASA's Manned Spacecraft Computers |url=https://ieeexplore.ieee.org/document/4392961 |journal=Annals of the History of Computing |volume=7 |issue=1 |pages=7–18 |doi=10.1109/MAHC.1985.10009 |access-date=18 November 2024 |url-access=subscription}}</ref>
<ref name=AP102>{{cite book |last1=Stuart |first1=Kenneth C. |title=&#91;1992&#93; Proceedings IEEE/AIAA 11th Digital Avionics Systems Conference |date= 1992|chapter=VHSIC technology insertion into the AP-102 avionics processor family |url=https://ieeexplore.ieee.org/document/282162 |volume= |pages= 183–188|doi=10.1109/DASC.1992.282162 |isbn=0-7803-0820-4 |access-date= |url-access=subscription}}</ref>
<ref name=IBM1981>{{cite journal
  | doi = 10.1147/rd.255.0405
  | last1 = Olsen
  | first1 = P.F.
  | last2=  Orrange
  | first2= R.J.
  | title = Real-Time Systems for Federal Applications: A Review of Significant Technological Developments
  | journal = IBM Journal of Research and Development
  | volume = 25
  | issue = 5
  | pages = 405–416
  | date = September 1981}}</ref>
<ref name=MMP>{{cite journal |doi=10.1145/384281.808211 |title=Applications of pipelining to firmware |date=1984 |last1=Proulx |first1=David M. |journal=ACM SIGMICRO Newsletter |volume=15 |issue=4 |pages=37–46 }}</ref>
}}

==Bibliography==
*{{cite journal |last=Vandling |first=Gilbert C. |title=Organization of a Microprogrammed Aerospace Computer |journal=Computer Design |pages=65–72 |date=February 1975 |volume=14 |issue=2 |oclc=1134857535 |issn=0010-4566}}
*{{cite book|url=https://archive.org/details/bitsavers_ibm4piTechBMSystem4PiComputers1967_10147919|title=Technical Description of IBM System/4 Pi Computers|author=<!--Staff writer(s); no by-line.-->|date=1967|publisher=Federal Systems Division of IBM|location=Owego, NY|access-date=27 October 2013|ref={{harvid|IBM|1967}}}}
*{{cite book|url=https://archive.org/details/bitsavers_ibm4pi4PIO_7750284|title=IBM System/4 Pi Overview|ref={{harvid|IBM Overview}}}}

==External links==
*[https://web.archive.org/web/20050119055725/http://www-03.ibm.com/ibm/history/exhibits/space/space_shuttle.html IBM Archive: IBM and the Space Shuttle]
*[https://web.archive.org/web/20050119055757/http://www-03.ibm.com/ibm/history/exhibits/space/space_skylab.html IBM Archive: IBM and Skylab]
*[https://web.archive.org/web/20010608173130/http://spaceflight.nasa.gov/shuttle/reference/shutref/orbiter/avionics/dps/gpc.html NASA description of Shuttle GPCs]
*[http://www.hq.nasa.gov/office/pao/History/computers/Ch4-3.html NASA history of AP-101 development] {{Webarchive|url=https://web.archive.org/web/20170215171047/http://www.hq.nasa.gov/office/pao/History/computers/Ch4-3.html |date=2017-02-15 }}
*[http://klabs.org/DEI/Processor/shuttle/ Space Shuttle Computers and Avionics]

{{Guidance Computer}}

{{DEFAULTSORT:IBM System 4 Pi}}
[[Category:Guidance computers]]
[[Category:IBM avionics computers|4999System 4 Pi]]
[[Category:Military computer systems of the U.S. Department of Defense]]