Editing Indirect branch

{{Short description|Type of program control instruction}}
{{refimprove|date=May 2018}}

{{Machine code}}

An '''indirect branch''' (also known as a '''computed jump''', '''indirect jump''' and '''register-indirect jump''') is a type of [[control flow|program control instruction]] present in some [[machine language]] [[instruction set]]s.  Rather than specifying the [[memory address|address]] of the next [[instruction (computer science)|instruction]] to [[execution (computers)|execute]], as in a direct [[Branch (computer science)|branch]], the [[parameter (computer science)|argument]] specifies where the address is located.  An example is 'jump indirect on the r1 [[processor register|register]]', which means that the next instruction to be executed is at the address in register r1. The address to be jumped to is not known until the instruction is executed.  Indirect branches can also depend on the value of a [[memory (computers)|memory location]].

An indirect branch can be useful to make a [[conditional branch]], especially a [[multiway branch]].  For instance, based on program [[Information|input]], a value could be looked up in a [[jump table]] of pointers to [[machine code|code]] for handling the various cases implied by the data value. The [[data#Uses of data in computing|data]] value could be added to the address of the table, with the result stored in a register. An indirect jump could then be made based on the value of that register, efficiently dispatching program control to the code appropriate to the input.

In a similar manner, [[subroutine]] call instructions can be indirect, with the address of the subroutine to be called specified in memory. [[Function pointer|Function Pointers]] are typically implemented with indirect subroutine calls.

Indirect branches were one of the attack surfaces of [[Spectre (security vulnerability)|Spectre]].  To mitigate the attack GCC 8.1 introduced the following new options: <code>-mindirect-branch=</code>, <code>-mfunction-return=</code> and <code>-mindirect-branch-register</code>.<ref name="GCC_2018_Spectre"/><ref group="nb" name="RETPOLINE_2018"/>

==Example assembler syntax==
:{|
| [[MSP430]]:&nbsp;&nbsp;||<code>br r15</code>
|-
| [[SPARC]]:&nbsp;&nbsp;||<code>jmpl %o7</code>
|-
| [[MIPS architecture|MIPS]]:&nbsp;&nbsp;&nbsp;||{{code|2=mips|jr $ra}}
|-
| [[x86]] (AT&T Syntax): &nbsp;&nbsp;&nbsp;&nbsp;||{{code|2=asm|jmp *%eax}}
|-
| [[x86]] (Intel Syntax): &nbsp;&nbsp;&nbsp;&nbsp;||{{code|2=nasm|jmp eax}}
|-
| [[ARM architecture|ARM]]:&nbsp;&nbsp;&nbsp;&nbsp;||{{code|2=asm|BX r0}}, {{code|2=asm|mov pc, r2}}
|-
| [[Itanium]] (x86 family):&nbsp;&nbsp;&nbsp;||<code>br.ret.sptk.few rp</code>
|-
| [[6502]]:&nbsp;&nbsp;&nbsp;||{{code|2=ca65|jmp ($0DEA)}}
|-
| [[65C816]]:&nbsp;||{{code|2=ca65|jsr ($0DEA,X)}}
|-
| [[6809]]:&nbsp;||<code>jmp [$0DEA]</code>, <code>jmp B,X</code>, <code>jmp [B,X]</code>
|-
| [[Motorola 6800|6800]]:&nbsp;||<code>jmp 0,X</code>
|-
| [[Z80]]:&nbsp;||<code>jp (hl)</code>
|-
| [[Intel MCS-51]]:&nbsp;||<code>jmp @A+DPTR</code>
|-
| [[Intel 8080]]:&nbsp;||<code>pchl</code>
|-
| [[IBM System z]]:&nbsp;||<code>bcr cond,r1</code><ref name="IBM"/>
|-
| [[PDP-11 architecture|PDP-11]]:&nbsp;||<code>jmp @R5</code>
|-
|[[RISC-V]]:
|<code>jalr x0, 0(x1)</code>
|}

==See also==
* [[Branch table]]
* [[Indirect threading]]
* [[Indirect branch control]] (IBC)
* [[Indirect branch restricted speculation]] (IBRS)
* [[Indirect branch prediction barrier]] (IBPB)
* [[Single thread indirect branch predictor]] (STIBP)

==Notes==
{{reflist|group="nb"|refs=
<ref group="nb" name="RETPOLINE_2018">Consult also the <code>RETPOLINE=y</code> feature added in Linux kernel 4.14.14/4.9.77/4.4.112. See also: [[Retpoline]]</ref>
}}

==References==
{{reflist|refs=
<ref name="GCC_2018_Spectre">{{cite web |title=Spectre Mitigation Added To GCC 8, Seeking Backport To GCC 7 |author-first=Michael |author-last=Larabel |author-link=Michael Larabel |date=2018-01-14 |url=https://www.phoronix.com/scan.php?page=news_item&px=GCC-8-Spectre-Mitigation-Lands |access-date=2018-01-19 |url-status=live |archive-url=https://web.archive.org/web/20180120070007/https://www.phoronix.com/scan.php?page=news_item&px=GCC-8-Spectre-Mitigation-Lands |archive-date=2018-01-20}}</ref>
<ref name="IBM">{{cite web |title=z/Architecture - Principles of Operation |edition=4 |date=May 2004 |orig-year=1990 |publisher=[[IBM]] |id=SA22-7832-03 |url=http://www-01.ibm.com/support/docview.wss?uid=isg26480faec85f44e2385256d5200627dee&aid=1 |access-date=2018-05-26 |url-status=live |archive-url=https://web.archive.org/web/20160304040255/http://www-01.ibm.com/support/docview.wss?uid=isg26480faec85f44e2385256d5200627dee&aid=1 |archive-date=2016-03-04}}</ref>
}}

{{DEFAULTSORT:Indirect Branch}}
[[Category:Control flow]]
[[Category:Machine code]]
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