Editing Instruction set architecture

{{Short description|Model that describe software's operations to a processor}}
{{Broader|Computer architecture}}
{{Distinguish|Industry Standard Architecture}}
{{Machine code}}

In [[computer science]], an '''instruction set architecture''' ('''ISA''') is an [[abstract model]] that generally defines how [[software]] controls the [[CPU]] in a computer or a family of computers.<ref>{{Cite web |title=GLOSSARY: Instruction Set Architecture (ISA) |url=https://www.arm.com/glossary/isa |archive-url=https://web.archive.org/web/20231111175250/https://www.arm.com/glossary/isa |archive-date=2023-11-11 |access-date=2024-02-03 |website=arm.com}}</ref> A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ''[[implementation]]'' of that ISA.

In general, an ISA defines the supported [[Machine code|instructions]], [[data type]]s, [[Register (computer)|registers]], the hardware support for managing [[Computer memory|main memory]],{{Clarify|date=April 2024|reason=See "What does "Hardware support for managing main memory" refer to?" on the talk page.]]}} fundamental features (such as the [[memory consistency]], [[addressing mode]]s, [[virtual memory]]), and the [[input/output]] model of implementations of the ISA.

An ISA specifies the behavior of [[machine code]] running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing [[binary compatibility]] between implementations. This enables multiple implementations of an ISA that differ in characteristics such as [[Computer performance|performance]], physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the [[microarchitecture]]s of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.

If an [[operating system]] maintains a standard and compatible [[application binary interface]] (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system.

An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute [[machine code]] for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions.

The binary compatibility that they provide makes ISAs one of the most fundamental abstractions in [[computing]].

==Overview==
An instruction set architecture is distinguished from a [[microarchitecture]], which is the set of [[processor design]] techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the [[Intel]] [[P5 (microarchitecture)|Pentium]] and the [[AMD]] [[Athlon]] implement nearly identical versions of the [[x86 instruction set]], but they have radically different internal designs.

The concept of an ''architecture'', distinct from the design of a specific machine, was developed by [[Fred Brooks]] at IBM during the design phase of [[System/360]]. {{quote|Prior to NPL [System/360], the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives.<ref name=Pugh>{{cite book|last1=Pugh|first1=Emerson W.|last2=Johnson|first2=Lyle R.|last3=Palmer|first3=John H.|title=IBM's 360 and Early 370 Systems|url=https://archive.org/details/ibms360early370s0000pugh|url-access=registration|year=1991|publisher=MIT Press|isbn=0-262-16123-0}}</ref>{{rp|p.137}}}}

Some [[virtual machine]]s that support [[bytecode]] as their ISA such as [[Smalltalk]], the [[Java virtual machine]], and [[Microsoft]]'s [[Common Language Runtime]], implement this by translating the bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see: [[Just-in-time compilation]]). [[Transmeta]] implemented the x86 instruction set atop [[very long instruction word]] (VLIW) processors in this fashion.

==Classification of ISAs==
An ISA may be classified in a number of different ways. A common classification is by architectural ''complexity''. A [[complex instruction set computer]] (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A [[reduced instruction set computer]] (RISC) simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.<ref>{{cite web |last1=Chen |first1=Crystal |last2=Novick |first2=Greg |last3=Shimano |first3=Kirk |date=December 16, 2006 |title=RISC Architecture: RISC vs. CISC |url=http://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/ |url-status=dead |archive-url=https://web.archive.org/web/20150221071744/http://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/ |archive-date=February 21, 2015 |access-date=February 21, 2015 |website=cs.stanford.edu}}</ref>

Other types include VLIW architectures, and the closely related {{citation needed span|''long instruction word'' (LIW)|date=March 2023}} and ''[[explicitly parallel instruction computing]]'' (EPIC) architectures. These architectures seek to exploit [[instruction-level parallelism]] with less hardware than RISC and CISC by making the [[compiler]] responsible for instruction issue and scheduling.<ref>{{cite journal|title=EPIC: Explicitly Parallel Instruction Computing|last1=Schlansker|first1=Michael S.|last2=Rau|first2=B. Ramakrishna|journal=[[Computer (magazine)|Computer]]|date=February 2000|volume=33|issue=2|pages=37–45 |doi=10.1109/2.820037}}</ref>

Architectures with even less complexity have been studied, such as the [[minimal instruction set computer]] (MISC) and [[one-instruction set computer]] (OISC). These are theoretically important types, but have not been commercialized.<ref>{{cite journal|url=https://www.researchgate.net/publication/267239549|title=On the Classification of Computer Architecture|last1=Shaout|first1=Adnan|last2=Eldos|first2=Taisir|journal=International Journal of Science and Technology|date=Summer 2003|access-date=March 2, 2023|volume=14|page=3}}</ref><ref>{{cite book|title=Computer Architecture: A Minimalist Perspective|last1=Gilreath|first1=William F.|last2=Laplante|first2=Phillip A.|publisher=[[Springer Science+Business Media]]|date=December 6, 2012|isbn=978-1-4615-0237-1}}</ref>

==<span id="NATIVE"></span>Instructions==
[[Machine_code|Machine language]] is built up from discrete ''statements'' or ''instructions''. On the processing architecture, a given instruction may specify:
*[[opcode]] (the instruction to be performed) e.g. add, copy, test
*any explicit operands:
::[[processor register|registers]]
::literal/constant values
::[[addressing mode]]s used to access memory
More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by [[control flow]] instructions.

===Instruction types===
Examples of operations common to many instruction sets include:

====Data handling and memory operations====
*''Set'' a [[processor register|register]] to a fixed constant value.
*''Copy'' data from a memory location or a register to a memory location or a register (a machine instruction is often called ''move''; however, the term is misleading). They are used to store the contents of a register, the contents of another memory location or the result of a computation, or to retrieve stored data to perform a computation on it later. They are often called [[load–store unit|''load'' or ''store'']] operations.
*''Read'' or ''write'' data from hardware devices.

====Arithmetic and logic operations====
*''Add'', ''subtract'', ''multiply'', or ''divide'' the values of two registers, placing the result in a register, possibly setting one or more [[flag (programming)|condition codes]] in a [[status register]].{{Sfn|Hennessy|Patterson|2003|p=108}}
**''{{vanchor|increment}}'', ''{{vanchor|decrement}}'' in some ISAs, saving operand fetch in trivial cases.
*Perform [[bitwise operation]]s, e.g., taking the ''[[logical conjunction|conjunction]]'' and ''[[logical disjunction|disjunction]]'' of corresponding bits in a pair of registers, taking the ''[[logical negation|negation]]'' of each bit in a register.
*''Compare'' two values in registers (for example, to see if one is less, or if they are equal).
*''{{vanchor|Floating-point instruction}}s'' for arithmetic on floating-point numbers.{{Sfn|Hennessy|Patterson|2003|p=108}}

====Control flow operations====
*''[[Branch (computer science)|Branch]]'' to another location in the program and execute instructions there.
*''[[Conditional branch|Conditionally branch]]'' to another location if a certain condition holds.
*''[[Indirect branch|Indirectly branch]]'' to another location.
*''Skip'' one of more instructions, depending on conditions
*''Trap'' Explicitly cause an [[interrupt]], either conditionally or unconditionally.
*''[[Subroutine|Call]]'' another block of code, while saving, e.g., the location of the next instruction, as a point to return to.

====Coprocessor instructions====
*Load/store data to and from a coprocessor or exchanging with CPU registers.
*Perform coprocessor operations.

===Complex instructions===
Processors may include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are [[typified]] by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include:

*transferring multiple registers to or from memory (especially the [[Call stack|stack]]) at once
*moving large blocks of memory (e.g. [[string copy]] or [[DMA transfer]])
*complicated integer and [[floating-point arithmetic]] (e.g. [[square root]], or [[transcendental function]]s such as [[logarithm]], [[sine]], [[cosine]], etc.)
*''{{vanchor|[[SIMD]] instruction|SIMD instruction}}s'', a single instruction performing an operation on many homogeneous values in parallel, possibly in dedicated [[SIMD register]]s
*performing an atomic [[test-and-set]] instruction or other [[read–modify–write]] [[atomic instruction]]
*instructions that perform [[arithmetic logic unit|ALU]] operations with an operand from memory rather than a register

Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets include [[Single instruction, multiple data|SIMD]] or [[vector processing|vector]] instructions that perform the same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy [[parallelization]] of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as [[MMX (instruction set)|MMX]], [[3DNow!]], and [[AltiVec]].

{{Anchor|Parts of an instruction}}

===Instruction encoding===
[[File:Mips32 addi.svg|thumb|right|upright=1.7|One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.]]

On traditional architectures, an instruction includes an [[opcode]] that specifies the operation to perform, such as ''add contents of memory to register''—and zero or more [[operand]] specifiers, which may specify [[processor register|registers]], memory locations, or literal data. The operand specifiers may have [[addressing mode]]s determining their meaning or may be in fixed fields. In [[very long instruction word]] (VLIW) architectures, which include many [[microcode]] architectures, multiple simultaneous opcodes and operands are specified in a single instruction.

Some exotic instruction sets do not have an opcode field, such as [[transport triggered architecture]]s (TTA), only operand(s).

Most [[stack machine]]s have "[[0-operand instruction set|0-operand]]" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix ([[reverse Polish notation]]) operations that work only on the expression [[Stack (abstract data type)|stack]], not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.<ref>{{cite web|url=http://www.cs.kent.edu/~durand/CS0/Notes/Chapter05/isa.html|title=Instruction Set Architecture (ISA)|work=Introduction to Computer Science CS 0|first=Paul|last=Durand}}</ref>

<!-- A conditional branch that falls though may still have other effects, e.g., decrementing a count register. -->
Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and the target location not modified, if the condition is false. Similarly, IBM [[z/Architecture]] has a conditional store instruction. A few instruction sets include a predicate field in every instruction. Having predicates for non-branch instructions is called [[predication (computer architecture)|predication]].

====Number of operands====
Instruction sets may be categorized by the maximum number of operands ''explicitly'' specified in instructions.

(In the examples that follow, ''a'', ''b'', and ''c'' are (direct or calculated) addresses referring to memory cells, while ''reg1'' and so on refer to machine registers.)

 C = A+B

*0-operand (''zero-address machines''), so called [[stack machine]]s: All arithmetic operations take place using the top one or two positions on the stack:{{Sfn|Hennessy|Patterson|2003|p=92}} <code>push a</code>, <code>push b</code>, <code>add</code>, <code>pop c</code>.
**<code>C = A+B</code> needs ''four instructions''.{{Sfn|Hennessy|Patterson|2003|p=93}} For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.
*1-operand (''one-address machines''), so called [[accumulator machine]]s, include early computers and many small [[microcontroller]]s: most instructions specify a single right operand (that is, constant, a register, or a memory location), with the implicit [[accumulator (computing)|accumulator]] as the left operand (and the destination if there is one): <code>load a</code>, <code>add b</code>, <code>store c</code>.
**<code>C = A+B</code> needs ''three instructions''.{{Sfn|Hennessy|Patterson|2003|p=93}}
*2-operand — many CISC and RISC machines fall under this category:
**CISC — <code>move A</code> to ''C''; then <code>add B</code> to ''C''.
***<code>C = A+B</code> needs ''two instructions''. This effectively 'stores' the result without an explicit ''store'' instruction.
**CISC — Often machines are [https://web.archive.org/web/20131105155703/http://cs.smith.edu/~thiebaut/ArtOfAssembly/CH04/CH04-3.html#HEADING3-79 limited to one memory operand] per instruction: <code>load a,reg1</code>; <code>add b,reg1</code>; <code>store reg1,c</code>; This requires a load/store pair for any memory movement regardless of whether the <code>add</code> result is an augmentation stored to a different place, as in <code>C = A+B</code>, or the same memory location: <code>A = A+B</code>.
***<code>C = A+B</code> needs ''three instructions''.
**RISC — Requiring explicit memory loads, the instructions would be: <code>load a,reg1</code>; <code>load b,reg2</code>; <code>add reg1,reg2</code>; <code>store reg2,c</code>.
***<code>C = A+B</code> needs ''four instructions''.
*3-operand, allowing better reuse of data:<ref name="Cocke">
{{Cite journal |last1=Cocke |first1=John |last2=Markstein |first2=Victoria |date=January 1990 |title=The evolution of RISC technology at IBM |url=https://www.cis.upenn.edu/~milom/cis501-Fall11/papers/cocke-RISC.pdf |journal=IBM Journal of Research and Development |volume=34 |issue=1 |pages=4–11 |doi=10.1147/rd.341.0004 |access-date=2022-10-05}}
</ref>
**CISC — It becomes either a single instruction: <code>add a,b,c</code>
***<code>C = A+B</code> needs ''one instruction''.
**CISC — Or, on machines limited to two memory operands per instruction, <code>move a,reg1</code>; <code>add reg1,b,c</code>;
***<code>C = A+B</code> needs ''two instructions''.
**RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed: <code>load a,reg1</code>; <code>load b,reg2</code>; <code>add reg1+reg2->reg3</code>; <code>store reg3,c</code>;
***<code>C = A+B</code> needs ''four instructions''.
***Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.<ref name=Cocke/>
*more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the [[VAX]] "POLY" polynomial evaluation instruction.

Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR, [[TI MSP430]], and some versions of [[ARM Thumb]]. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the [[ARM architecture family|ARM]], [[AVR32]], [[MIPS architecture|MIPS]], [[Power ISA]], and [[SPARC]] architectures.

Each instruction specifies some number of operands (registers, memory locations, or immediate values) ''explicitly''. Some instructions give one or both operands implicitly, such as by being stored on top of the [[stack (data structure)|stack]] or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the [[arity]]). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode.

==={{Anchor|REGISTER-PRESSURE}}Register pressure===
''Register pressure'' measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must be [[register spilling|spilled]] into memory. Increasing the number of registers in an architecture decreases register pressure but increases the cost.<ref>{{cite book |last=Page |first=Daniel |title=A Practical Introduction to Computer Architecture |chapter=11. Compilers |year=2009 |publisher=Springer |isbn=978-1-84882-255-9 |page=464|bibcode=2009pica.book.....P }}</ref>

While embedded instruction sets such as [[ARM Thumb|Thumb]] suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like [[MIPS architecture|MIPS]] and [[DEC Alpha|Alpha]] enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer.<ref>{{cite conference |last1=Venkat |first1=Ashish |last2=Tullsen |first2=Dean M. |title=Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor |year=2014 |conference=41st Annual International Symposium on Computer Architecture |url=http://dl.acm.org/citation.cfm?id=2665692}}</ref>

==={{Anchor|Fixed length|Fixed width|Variable length|Variable width}}Instruction length===
The size or length of an instruction varies widely, from as little as four bits in some [[microcontroller]]s to many hundreds of bits in some [[very long instruction word|VLIW]] systems. Processors used in [[personal computer]]s, [[mainframe computer|mainframe]]s, and [[supercomputer]]s have minimum instruction sizes between 8 and 64 bits. The longest possible instruction on x86 is 15 bytes (120 bits).<ref>{{cite web|title=Intel® 64 and IA-32 Architectures Software Developer's Manual|url=https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html|publisher=Intel Corporation|access-date=5 October 2022}}</ref> Within an instruction set, different instructions may have different lengths. In some architectures, notably most [[reduced instruction set computer]]s (RISC), {{vanchor|instructions are a fixed length|FIXED_LENGTH_INSTRUCTIONS}}, typically corresponding with that architecture's [[word (data type)|word size]]. In other architectures, instructions have [[variable-length code|variable length]], typically integral multiples of a [[byte]] or a [[halfword]]. Some, such as the [[ARMv7|ARM]] with ''Thumb-extension'' have ''mixed'' variable encoding, that is two fixed, usually 32-bit and 16-bit encodings, where instructions cannot be mixed freely but must be switched between on a branch (or exception boundary in ARMv8).

Fixed-length instructions are less complicated to handle than variable-length instructions for several reasons (not having to check whether an instruction straddles a cache line or virtual memory page boundary,<ref name=Cocke/> for instance), and are therefore somewhat easier to optimize for speed.

===Code density===
In early 1960s computers, main memory was expensive and very limited, even on mainframes. Minimizing the size of a program to make sure it would fit in the limited memory was often central. Thus the size of the instructions needed to perform a particular task, the ''code density'', was an important characteristic of any instruction set. It remained important on the initially-tiny memories of minicomputers and then microprocessors. Density remains important today, for smartphone applications, applications downloaded into browsers over slow Internet connections, and in ROMs for embedded applications. A more general advantage of increased density is improved effectiveness of caches and instruction prefetch. 

Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc. (therefore retroactively named ''Complex Instruction Set Computers'', [[complex instruction set computer|CISC]]). However, more typical, or frequent, "CISC" instructions merely combine a basic ALU operation, such as "add", with the access of one or more operands in memory (using [[addressing mode]]s such as direct, indirect, indexed, etc.). Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc. Software-implemented instruction sets may have even more complex and powerful instructions.

''Reduced instruction-set computers'', [[RISC]], were first widely implemented during a period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. A RISC instruction set normally has a fixed [[#Instruction length|instruction length]], whereas a typical CISC instruction set has instructions of widely varying length. However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories.

Certain embedded RISC ISAs like [[ARM architecture#Thumb|Thumb]] and [[AVR32]] typically exhibit very high density owing to a technique called code compression. This technique packs two 16-bit instructions into one 32-bit word, which is then unpacked at the decode stage and executed as two instructions.<ref name=weaver>{{cite conference|last1=Weaver|first1=Vincent M.|last2=McKee|first2=Sally A.|title=Code density concerns for new architectures|year=2009|conference=IEEE International Conference on Computer Design|doi=10.1109/ICCD.2009.5413117|citeseerx=10.1.1.398.1967}}</ref>

[[Minimal instruction set computer]]s (MISC) are commonly a form of [[stack machine]], where there are few separate instructions (8–32), so that multiple instructions can be fit into a single machine word. These types of cores often take little silicon to implement, so they can be easily realized in an FPGA ([[field-programmable gate array]]) or in a [[multi-core]] form. The code density of MISC is similar to the code density of RISC; the increased instruction density is offset by requiring more of the primitive instructions to do a task.<ref>{{Cite web|title=RISC vs. CISC|url=https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/|access-date=2021-12-18|website=cs.stanford.edu}}</ref>{{Failed verification|reason=That discusses RISC and CISC, but not MISC.|date=December 2021}}
<!-- Need examples here -->

There has been research into [[executable compression]] as a mechanism for improving code density. The mathematics of [[Kolmogorov complexity]] describes the challenges and limits of this.

In practice, code density is also dependent on the [[compiler]]. Most [[optimizing compiler]]s have options that control whether to optimize code generation for execution speed or for code density. For instance [[GNU Compiler Collection|GCC]] has the option <code>-Os</code> to optimize for small machine code size, and <code>-O3</code> to optimize for execution speed at the cost of larger machine code.

===Representation===
The instructions constituting a program are rarely specified using their internal, numeric form ([[machine code]]); they may be specified by programmers using an [[assembly language]] or, more commonly, may be generated from [[high-level programming language]]s by [[compiler]]s.{{Sfn|Hennessy|Patterson|2003|p=120}}

==Design==
The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (complex instruction set computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (reduced instruction set computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory and [[CPU cache|cache]] efficiency, or simplify programming.

Some instruction set designers reserve one or more opcodes for some kind of [[system call]] or [[software interrupt]]. For example, [[MOS Technology 6502]] uses 00<sub>H</sub>, [[Zilog Z80]] uses the eight codes C7,CF,D7,DF,E7,EF,F7,FF<sub>H</sub><ref>{{cite web|last=Ganssle|first=Jack|url=https://www.embedded.com/electronics-blogs/break-points/4023293/Proactive-Debugging|title=Proactive Debugging|date=February 26, 2001|website=embedded.com}}</ref> while [[Motorola 68000]] use codes in the range A000..AFFF<sub>H</sub>. <!-- Trivial parts catalog notes, while recondite terms like CISC and RISC are completely unsupported by any textbook. -->

Fast virtual machines are much easier to implement if an instruction set meets the [[Popek and Goldberg virtualization requirements]].{{Clarify|date=October 2012}}

The [[NOP slide]] used in immunity-aware programming is much easier to implement if the "unprogrammed" state of the memory is interpreted as a [[NOP (code)|NOP]].{{dubious|date=October 2012}}

On systems with multiple processors, [[non-blocking synchronization]] algorithms are much easier to implement{{Citation needed |reason=Opinion unsupported by a textbook |date=October 2012}} if the instruction set includes support for something such as "[[fetch-and-add]]", "[[load-link/store-conditional]]" (LL/SC), or "atomic [[compare-and-swap]]".

==Instruction set implementation==
{{Main|Processor design|Semiconductor device fabrication|Silicon compiler}}
A given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the same [[programming model]], and all implementations of that instruction set are able to run the same executables. The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc.

When designing the [[microarchitecture]] of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as adders, multiplexers, counters, registers, ALUs, etc. Some kind of [[register transfer language]] is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture.
There are two basic ways to build a [[control unit]] to implement this description (although many designs use middle ways or compromises):

# Some computer designs "hardwire" the complete instruction set decoding and sequencing (just like the rest of the microarchitecture).
# Other designs employ [[microcode]] routines or tables (or both) to do this, using [[ROM]]s or writable [[random-access memory|RAMs]] ([[writable control store]]), [[programmable logic array|PLAs]], or both.

Some microcoded CPU designs with a writable control store use it to allow the instruction set to be changed (for example, the [[Rekursiv]] processor and the [[Imsys]] [[Cjip]]).<ref>{{cite web|url=http://cpushack.net/CPU/cpu7.html |title=Great Microprocessors of the Past and Present (V 13.4.0) |website=cpushack.net |access-date=2014-07-25}}</ref>

CPUs designed for [[reconfigurable computing]] may use [[field-programmable gate array]]s (FPGAs).

An ISA can also be [[emulator|emulated]] in software by an [[interpreter (computing)|interpreter]]. Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless the hardware running the emulator is an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.

Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of the [[instruction pipeline]] only allow a single memory load or memory store per instruction, leading to a [[load–store architecture]] (RISC). For another example, some early ways of implementing the [[instruction pipeline]] led to a [[delay slot]].

The demands of high-speed digital signal processing have pushed in the opposite direction—forcing instructions to be implemented in a particular way. For example, to perform digital filters fast enough, the MAC instruction in a typical [[digital signal processor]] (DSP) must use a kind of [[Harvard architecture]] that can fetch an instruction and two data words simultaneously, and it requires a single-cycle [[multiply–accumulate operation|multiply–accumulate]] [[binary multiplier|multiplier]].

==See also==
*[[Comparison of instruction set architectures]]
*[[Compressed instruction set]]
*[[Computer architecture]]
*[[Emulator]]
*[[Instruction set simulator]]
*[[Micro-operation]]
*[[No instruction set computing]]
*[[OVPsim]] – full systems simulator providing ability to create/model/emulate any instruction set using C and standard APIs
*[[Processor design]]
*[[Simulation]]
*[[Register transfer language]] (RTL)

==References==
{{Reflist|30em}}

==Further reading==
*{{cite journal |title=Standard Microprocessor Programming Cards |journal=Microprocessors and Microsystems |first=Jonathan P. |last=Bowen |author-link=Jonathan Bowen |volume=9 |number=6 |pages=274–290 |date=July–August 1985 |doi=10.1016/0141-9331(85)90116-4}}
*{{cite book|url=https://books.google.com/books?id=XX69oNsazH4C|title=Computer Architecture: A Quantitative Approach|edition=Third|last1=Hennessy|first1=John L.|author1-link=John L. Hennessy|last2=Patterson|first2=David A.|author2-link=David Patterson (computer scientist)|publisher=[[Morgan Kaufmann Publishers]]|date=2003|access-date=2023-03-04|isbn=1-55860-724-2}}

==External links==
{{wikibooks
|1= Microprocessor Design
|2= Instruction Set Architectures
}}
*{{Commonscatinline|Instruction set architectures}}
*[http://www.textfiles.com/programming/CARDS/ Programming Textfiles: Bowen's Instruction Summary Cards]
*[https://people.computing.clemson.edu/~mark/hist.html Mark Smotherman's Historical Computer Designs Page]

{{CPU technologies}}
{{Authority control}}

[[Category:Central processing unit]]
[[Category:Instruction processing|Set architectures]]
[[Category:Instruction set architectures| ]]
[[Category:Microprocessors|*Instruction set]]