Editing Integrated circuit packaging

{{Short description|Final stage of semiconductor device fabrication}}
{{about|the final stage in the manufacturing process of integrated circuits|an article about the physical enclosure that surrounds integrated circuits|Semiconductor package }}
{{Use American English|date = March 2019}}
[[File:DIP_package_sideview.PNG|thumb|Cross section of a [[dual in-line package]]. This type of package houses a small [[Die (integrated circuit)|semiconducting die]], with microscopic wires attaching the die to the [[lead frame]]s, allowing for electrical connections to be made to a [[Printed circuit board|PCB]].]]
[[File:DIP zagotovka.jpg|thumb|Dual in-line (DIP) integrated circuit metal lead frame tape with contacts]]

'''Integrated circuit packaging''' is the final stage of [[fabrication (semiconductor)|semiconductor device fabrication]], in which the [[die (integrated circuit)|die]] is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "[[semiconductor package|package]]", supports the electrical contacts which connect the device to a circuit board.

The packaging stage is followed by testing of the integrated circuit.

== Design considerations ==
[[File:TSSOP RQFP SO SSOP QFN.jpg|thumb|right|Various IC packages (left to right): TSSOP-32, TQFP-100, SO-20, SO-14, SSOP-28, SSOP-16, SO-8, QFN-28]]

=== Electrical ===
The current-carrying traces that run out of the die, through the package, and into the [[printed circuit board]] (PCB) have very different electrical properties compared to on-chip signals.  They require special design techniques and need much more electric power than signals confined to the chip itself. Therefore, it is important that the materials used as electrical contacts exhibit characteristics like low resistance, low capacitance and low inductance.<ref name=":02"/> Both the structure and materials must prioritize signal transmission properties, while minimizing any [[Parasitic element (electrical networks)|parasitic elements]] that could negatively affect the signal.

Controlling these characteristics is becoming increasingly important as the rest of technology begins to speed up. Packaging delays have the potential to make up almost half of a high-performance computer's delay, and this bottleneck on speed is expected to increase.<ref name=":02">{{Cite book|title=Digital Integrated Circuits|last=Rabaey|first=Jan|publisher=Prentice Hall, Inc.|year=2007|isbn=978-0130909961|url-access=registration|url=https://archive.org/details/agilesoftwaredev00robe|edition=2nd}}</ref>

=== Mechanical and thermal ===
The [[integrated circuit]] package must resist physical breakage, keep out moisture, and also provide effective heat dissipation from the chip. Moreover, for [[RF]] applications, the package is commonly required to shield [[electromagnetic interference]], that may either degrade the circuit performance or adversely affect neighboring circuits. Finally, the package must permit interconnecting the chip to a [[Printed circuit board|PCB]].<ref name=":02"/> The materials of the package are either plastic ([[thermosetting polymer|thermoset]] or [[thermoplastic]]), metal (commonly [[Kovar]]) or ceramic. A common [[plastic]] used for this is [[epoxy]]-[[cresol]]-[[novolak]] (ECN).<ref>{{cite book |chapter-url=https://www.researchgate.net/publication/285397294 |doi=10.1016/B978-0-8155-1576-0.50006-1 |via=[[ResearchGate]]|chapter=Plastic Encapsulant Materials |title=Encapsulation Technologies for Electronic Applications |year=2009 |last1=Ardebili |first1=Haleh |last2=Pecht |first2=Michael G. |pages=47–127 |isbn=9780815515760 |s2cid=138753417 }}</ref> All three material types offer usable mechanical strength, moisture and heat resistance. Nevertheless, for higher-end devices, metallic and ceramic packages are commonly preferred due to their higher strength (which also supports higher pin-count designs), heat dissipation, [[hermetic seal|hermetic performance]], or other reasons.  Generally, ceramic packages are more expensive than similar plastic packages.<ref name=":1">{{Cite book|title=Integrated Circuit Packaging, Assembly and Interconnections|last=Greig|first=William|publisher=Springer Science & Business Media|year=2007|isbn=9780387339139}}</ref>

Some packages have [[Fin (extended surface)|metallic fins]] to enhance heat transfer, but these take up space. Larger packages also allow for more interconnecting pins.<ref name=":02"/>

=== Economic ===
Cost is a factor in selection of integrated circuit packaging. Typically, an inexpensive plastic package can dissipate heat up to 2W, which is sufficient for many simple applications, though a similar ceramic package can dissipate up to 50W in the same scenario.<ref name=":02"/> As the chips inside the package get smaller and faster, they also tend to get hotter. As the subsequent need for more effective heat dissipation increases, the cost of packaging rises along with it. Generally, the smaller and more complex the package needs to be, the more expensive it is to manufacture.<ref name=":1" /> Wire bonding can be used instead of techniques such as flip-chip to reduce costs.<ref>{{cite web | url=https://sst.semiconductor-digest.com/2005/07/wire-bond-vs-flip-chip-packaging/ | title=Wire Bond Vs. Flip Chip Packaging &#124; Semiconductor Digest | date=10 December 2016 }}</ref>

== History ==
[[File:Laptop Acrobat Model NBD 486C, Type DXh2 - California Micro Devices CMD 9324 on motherboard-9749.jpg|thumb|Small-outline integrated circuit. This package has 16 "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 inches.]]
Early integrated circuits were packaged in [[Flatpack (electronics)|ceramic flat packs]], which the military used for many years for their reliability and small size. The other type of packaging used in the 1970s, called the ICP (Integrated Circuit Package), was a ceramic package (sometimes round as the transistor package), with the leads on one side, co-axially with the package axis.

Commercial circuit packaging quickly moved to the [[dual in-line package]] (DIP), first in ceramic and later in plastic.<ref>{{Cite book|title=Electronic Inventions and Discoveries (2nd ed).|last=Dummer|first=G.W.A.|publisher=Pergamon Press|year=1978|isbn=0-08-022730-9}}</ref> In the 1980s [[VLSI]] pin counts exceeded the practical limit for DIP packaging, leading to [[pin grid array]] (PGA) and [[leadless chip carrier]] (LCC) packages.<ref name=":2">{{Cite book|title=CMOS: Circuit Design, Layout, and Simulation, Third Edition|last=Baker|first=R. Jacob|publisher=Wiley-IEEE|year=2010|isbn=978-0-470-88132-3}}</ref> [[Surface mount]] packaging appeared in the early 1980s and became popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by [[small-outline integrated circuit]]—a carrier which occupies an area about 30–50% less than an equivalent [[Dual in-line package|DIP]], with a typical thickness that is 70% less.<ref name=":2" />[[File:RUS-IC.JPG|right|thumb|Early USSR-made integrated circuit. The tiny block of semiconducting material (the "die"), is enclosed inside the round, metallic case (the "package").]]The next big innovation was the ''area array package'', which places the interconnection [[Terminal (electronics)|terminals]] throughout the surface area of the package, providing a greater number of connections than previous package types where only the outer perimeter is used. The first area array package was a ceramic [[pin grid array]] package.<ref name=":02"/> Not long after, the plastic [[ball grid array]] (BGA), another type of area array package, became one of the most commonly used packaging techniques.<ref>{{cite book|title=Area array packaging processes for BGA, Flip Chip, and CSP|publisher=[[McGraw-Hill Professional]]|year=2003|isbn=0-07-142829-1|page=251|author=Ken Gilleo}}</ref>

In the late 1990s, [[PQFP|plastic quad flat pack]] (PQFP) and [[thin small-outline package]]s (TSOP) replaced PGA packages as the most common for high pin count devices,<ref name=":02"/> though PGA packages are still often used for [[microprocessor]]s. However, industry leaders [[Intel]] and [[AMD]] transitioned in the 2000s from PGA packages to [[land grid array]] (LGA) packages.<ref>{{Cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/guides/lga-socket-and-package-technology-training-guide.pdf|title=Land Grid Array (LGA) Socket and Package Technology|website=Intel|access-date=April 7, 2016}}</ref>

[[Ball grid array]] (BGA) packages have existed since the 1970s, but evolved into flip-chip ball grid array (FCBGA) packages in the 1990s. FCBGA packages allow for much higher pin count than any existing package types. In an FCBGA package, the die is mounted upside-down (flipped) and connects to the [[package ball]]s via a substrate that is similar to a printed-circuit board rather than by wires.  FCBGA packages allow an array of input-output signals (called Area-I/O) to be distributed over the entire die rather than being confined to the die periphery.<ref>{{Cite web|url=http://flipchips.com/tutorial01.html |title=Flipchips: Tutorial #1 |last=Riley |first=George |date=2009-01-30 |access-date=2016-04-07 |url-status=unfit |archive-url=https://web.archive.org/web/20090130092400/http://flipchips.com/tutorial01.html |archive-date=January 30, 2009 }}</ref> Ceramic subtrates for BGA were replaced with organic substrates to reduce costs and use existing PCB manufacturing techniques to produce more packages at a time by using larger PCB panels during manufacturing.<ref>{{cite book | url=https://books.google.com/books?id=tyJZ3eZQy7UC&dq=hdi+pcb+ajinomoto&pg=PA243 | isbn=978-0-387-78219-5 | title=Materials for Advanced Packaging | date=17 December 2008 | publisher=Springer }}</ref>

Traces out of the die, through the package, and into the [[printed circuit board]] have very different electrical properties, compared to on-chip signals.  They require special design techniques and need much more electric power than signals confined to the chip itself.

Recent developments consist of stacking multiple dies in single package called SiP, for ''[[System In Package]]'', or [[three-dimensional integrated circuit]].  Combining multiple dies on a small substrate, often ceramic, is called an MCM, or [[Multi-Chip Module]]. The boundary between a big MCM and a small printed circuit board is sometimes blurry.<ref>R. Wayne Johnson, Mark Strickland and David Gerke, NASA Electronic Parts and Packaging Program. "[http://nepp.nasa.gov/docuploads/EA7E7EA1-BD30-4DA4-BD615FEA1A7F5AE9/3D%20Packaging%20Report%20071805.pdf 3-D Packaging: A Technology Review.]" June 23, 2005. Retrieved July 31, 2015</ref>

== Common package types ==
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 |footer    = Left is [[X-ray]] of right [[Printed circuit board|PCB]], showing metal lead frames inside IC packages
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{{Main|List of electronic component packaging types}}
* [[Through-hole technology]]
* [[Surface-mount technology]]
* [[Chip carrier]]
* [[Pin grid array]]
* [[Quad Flat Package|Flat package]]
* [[Small Outline Integrated Circuit]]
* [[Chip-scale package]]
* [[Ball grid array]]
* [[List of electronic component packaging types|Transistor, diode, small pin count IC packages]]
* [[Multi-chip module|Multi-chip packages]]

== Operations ==
For traditional ICs, after [[wafer dicing]], the die is picked from the diced wafer using a vacuum tip or suction cup<ref>Die Attachment, Fluid Dispensing catalog from SPT small precision tools</ref><ref>{{cite web | url=https://www.eetimes.com/die-bonding-techniques-and-methods/ | title=Die bonding techniques and methods | date=9 July 2012 }}</ref> and undergoes ''die attachment'' which is the step during which a die is mounted and fixed to the [[Chip carrier|package]] or support structure (header).<ref name="Turner762">L. W. Turner (ed), ''Electronics Engineers Reference Book'', Newnes-Butterworth, 1976, {{ISBN|0-408-00168-2}}, pages 11-34 through 11-37</ref> In high-powered applications, the die is usually [[eutectic]] bonded onto the package, using e.g. gold-tin or gold-silicon [[solder]] (for good [[heat conduction]]). For low-cost, low-powered applications, the die is often glued directly onto a substrate (such as a [[printed wiring board]]) using an [[epoxy]] [[adhesive]]. 
Alternatively dies can be attached using solder. These techniques are usually used when the die will be wire bonded; dies with [[flip chip]] technology do not use these attachment techniques.<ref>{{cite web | url=https://www.eetimes.com/die-bonding-techniques-and-methods/ | title=Die bonding techniques and methods | date=9 July 2012 }}</ref><ref>{{cite book | url=https://books.google.com/books?id=xpanL96_yBQC&q=die+attach+adhesive&pg=PA388 | title=Chip on Board: Technology for Multichip Modules | isbn=978-0-442-01441-4 | last1=Lau | first1=John H. | date=30 June 1994 | publisher=Springer }}</ref>

IC bonding is also known as die bonding, die attach, and die mount.<ref name="Oricus Semicon Solutions 2021 z292">{{cite web | title=What is the Die Attach process? | website=Oricus Semicon Solutions | date=2021-11-01 | url=https://oricus-semicon.com/what-is-the-die-attach-process/ | access-date=2024-04-22}}</ref>

The following operations are performed at the packaging stage, as broken down into bonding, encapsulation, and wafer bonding steps. Note that this list is not all-inclusive and not all of these operations are performed for every package, as the process is highly dependent on the [[List of electronic component packaging types|package type]].
*[[IC bonding]]
**[[Wire bonding]]
**[[Thermosonic bonding]]
**[[Down bonding]]
**[[Tape automated bonding]]
**[[Flip chip]]
**[[Quilt packaging]]
**[[Film attaching]]
**[[Spacer attaching]]
**[[Sintering die attach]]
*IC encapsulation
**[[Curing (chemistry)|Baking]]
**[[Plating]]
**[[Lasermarking]]
**[[Trim and form]]
*[[Wafer bonding]]

Sintering die attach is a process that involves placing the semiconductor die onto the substrate and then subjecting it to high temperature and pressure in a controlled environment.<ref>Buttay, Cyril, et al. [https://hal.science/file/index/docid/672619/filename/article.pdf "Die attach of power devices using silver sintering-bonding process optimization and characterization."] HiTEN 2011. 2011.</ref>

==See also==
* [[Advanced packaging (semiconductors)]]
* [[List of electronic component packaging types]]
* [[List of electronics package dimensions]]
* [[Gold–aluminium intermetallic]] "purple plague" 
* [[Co-fired ceramic]]
* [[B-staging]]
* [[Potting (electronics)]]
* [[Quilt packaging]]
* [[Electronic packaging]]
* [[Decapping]]

== References ==
{{reflist}}

{{Semiconductor packages}}

{{DEFAULTSORT:Integrated Circuit Packaging}}
[[Category:Semiconductor device fabrication]]
[[Category:Chip carriers]]
[[Category:Packaging (microfabrication)]]