Editing Intel 8008

{{Use dmy dates|date=October 2018|cs1-dates=y}}
{{Short description|8-bit microprocessor}}
{{Infobox CPU
|name = Intel 8008
|image= KL_Intel_C8008-1.jpg
|caption = An Intel C8008-1 processor variant with purple ceramic, gold-plated metal lid and pins 
|produced-start = April 1972
|produced-end = 1983<ref>{{cite web |title=The Life Cycle of a CPU |url=https://www.cpushack.com/life-cycle-of-cpu.html |website=www.cpushack.com}}</ref>
|slowest = 500  | slow-unit = kHz
|fastest = 800  | fast-unit = kHz
|size-from = [[10 μm process|10&nbsp;μm]]
|transistors = 3,500
|application = [[Computer terminal]]s, [[calculator]]s, bottling machines, 1970s [[ASEA]] [[industrial robot]]s<ref>{{cite web |url=http://www02.abb.com/global/gad/gad02077.nsf/lupLongContent/4F792B65B20267C5C1256FBE00546364 |title=Thirty years in robotics – Robotics |date=2014-05-19 |archive-url=https://web.archive.org/web/20140319013015/http://www02.abb.com/global/gad/gad02077.nsf/lupLongContent/4F792B65B20267C5C1256FBE00546364 |access-date=2018-04-11 |archive-date=2014-03-19}}</ref> (IRB 6), simple [[computer]]s, etc.
|manuf1 = Intel
|designfirm = [[Computer Terminal Corporation]] (CTC)
|arch = 8008
|pack1 = 18-pin [[dual in-line package]]
|predecessor = <!-- the consensus seems to be that the 8008 is not a descendant of the 4004 or 4040: see the discussion at https://en.wikipedia.org/w/index.php?title=Intel_8008&oldid=1132840740#HIstory -->
|successor = [[Intel 8080]]
|data-width = 8 bits
|address-width = 14 bits
|sock1 = [[dual in-line package|DIP18]]
|support status = Unsupported
|soldby=[[Intel]]}}

The '''Intel 8008''' ("''eight-thousand-eight''" or "''eighty-oh-eight''") is an early [[8-bit computing|8-bit]] microprocessor capable of addressing 16 KB of memory, introduced in April 1972. The 8008 architecture was designed by [[Computer Terminal Corporation]] (CTC) and was implemented and manufactured by [[Intel]]. While the 8008 was originally designed for use in CTC's [[Datapoint 2200]] programmable terminal, an agreement between CTC and Intel permitted Intel to market the chip to other customers after [[Seiko]] expressed an interest in using it for a [[calculator]].

==History==
In order to address several issues with the [[Datapoint 3300]], including excessive heat radiation, [[Computer Terminal Corporation]] (CTC) designed the architecture of the 3300's planned successor with a CPU as part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, CTC co-founder Austin O. "Gus" Roche turned to Intel, then primarily a vendor of memory chips.<ref name="Wood">{{citation |author-first=Lamont |author-last=Wood |url=http://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |title=Forgotten PC history: The true origins of the personal computer |journal=Computerworld |date=2008-04-08 |access-date=2014-12-02  |archive-date=2018-11-16  |archive-url=https://web.archive.org/web/20181116163842/https://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |url-status=dead }}</ref> Roche met with [[Bob Noyce]], who expressed concern with the concept; [[John Frassanito]] recalls that: {{quote|"Noyce said it was an intriguing idea, and that Intel could do it, but it would be a dumb move. He said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer."<ref name="Wood"/>}} Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs; if Intel introduced their own processor, they might be seen as a competitor, and their customers might look elsewhere for memory. Nevertheless, Noyce agreed to a US$50,000 development contract in early 1970 ({{Inflation|US|50000|1970|fmt=eq|r=-3}}). [[Texas Instruments]] (TI) was also brought in as a second supplier.{{fact|date=April 2024}}

In December 1969, Intel engineer [[Stan Mazor]] and a representative of CTC met to discuss options for the logic chipset to power a new CTC business terminal. Mazor, who had been working with [[Ted Hoff]] on the development of the [[Intel 4004]], proposed that a one-chip programmable microprocessor might be less cumbersome and ultimately more cost effective than building a custom logic chipset. CTC agreed and development work began on the chip, which at the time was known as the 1201.<ref name="8008 DEV">{{cite web|url=https://www.intel.com/content/www/us/en/history/virtual-vault/articles/the-8008.html|title=The Intel 8008|work=[[Intel]]|access-date=December 15, 2024}}</ref>

TI was able to make samples of the 1201 based on Intel drawings, calling it the TMX 1795. These proved to be buggy and were rejected.<ref>{{cite web |last1=Shirriff |first1=Ken |title=The Texas Instruments TMX 1795: the (almost) first, forgotten microprocessor |url=https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |website=righto.com |access-date=6 March 2025}}</ref> Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using [[Serial computer|serial]] discrete [[Transistor–transistor logic|TTL]] instead of waiting for a single-chip CPU. The new system was released as the [[Datapoint 2200]] in the spring of 1970, with their first sale to [[General Mills]] on 25 May 1970.<ref name="Wood"/> CTC paused development of the 1201 after the 2200 was released, as it was no longer needed. Later in early 1971, Seiko approached Intel, expressing an interest in using the 1201 in a scientific calculator, likely after seeing the success of the simpler 4004 used by Busicom in their business calculators.<ref name="8008 DEV"/> A small re-design followed, under the leadership of [[Federico Faggin]], the designer of the [[Intel 4004|4004]], now project leader of the 1201, expanding from a 16-pin to 18-pin design, and the new 1201 was delivered to CTC in late 1971.<ref name="Wood"/>

By that point, CTC had once again moved on, this time to the parallel-architecture [[Datapoint 2200 II]], which was faster than the 1201. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008 and put it in their catalog in April 1972 priced at US$120 ({{Inflation|US|120|1972|fmt=eq}}). This renaming tried to ride off the success of the 4004 chip, by presenting the 8008 as simply a 4 to 8 port, but the 8008 is ''not'' based on the [[Intel 4004|4004]].<ref>{{cite interview |author=Ken Shirriff |quote=First, the 4004 and the 8008 are entirely different chips. Marketing makes them sound like it's just a 4-bit and 8-bit version, but they're totally different. |url=https://oxide.computer/podcasts/on-the-metal/ken-shirriff/ |time=19:52 |date=2021-01-26 |interviewer1=Bryan Cantrill |interviewer2=Jessie Frazelle |interviewer3=Steve Tuck |work=Oxide Computing Podcast |title=On the Metal: Ken Shirriff }}</ref> The 8008 went on to be a commercially successful design. This was followed by the popular [[Intel 8080]], and then the hugely successful [[Intel x86]] family.<ref name="Wood"/> 

In the UK, a team at S. E. Laboratories Engineering (EMI) led by Tom Spink in 1972 built a microcomputer based on a pre-release sample of the 8008. Joe Hardman extended the chip with an external stack. This, among other things, gave it power-fail save and recovery. Joe also developed a direct screen printer. The operating system was written using a meta-assembler developed by L. Crawford and J. Parnell for a [[Digital Equipment Corporation]] [[PDP-11]].<ref>Brunel University, 1974. Master of Technology dissertation, L. R. Crawford.</ref> The operating system was burnt into a PROM. It was interrupt-driven, queued, and based on a fixed page size for programs and data. An operational prototype was prepared for management, who decided not to continue with the project.{{fact|date=April 2024}}

The 8008 was the CPU for the very first commercial non-calculator [[personal computer]]s (excluding the Datapoint 2200 itself): the US [[SCELBI]] kit and the pre-built French [[Micral N]] and Canadian [[MCM/70]]. It was also the controlling microprocessor for the first several models in Hewlett-Packard's [[HP 2640|2640]] family of computer terminals.{{fact|date=April 2024}}

{{anchor|INTERP}}In 1973, Intel offered an [[instruction set simulator]] for the 8008 named INTERP/8.<ref name="Intel_1973">{{cite book |title=MCS-8 Microcomputer Set - 8008 - 8 Bit Parallel Central Processor Unit - Users Manual |chapter=XI. Appendices III. MCS-8 Software Package - Simulator |date=1974 |orig-date=November 1973 |version=Revision 4, Second Printing |publisher=[[Intel Corporation]] |publication-place=Santa Clara, California, USA |id=MCS-056-0574/25K |pages=84–94 |url=https://en.wikichip.org/w/images/e/ec/MCS-8_User_Manual_%28Rev_4%29_%28Nov_1973%29.pdf |access-date=2023-11-25 |url-status=live |archive-url=https://web.archive.org/web/20231125221321/https://en.wikichip.org/w/images/e/ec/MCS-8_User_Manual_%28Rev_4%29_%28Nov_1973%29.pdf |archive-date=2023-11-25}} (132 pages)</ref> It was written<!-- in 1972 or 1973, exact date not known yet --> in [[FORTRAN IV]] by [[Gary Kildall]] while he worked as a consultant for Intel.<ref name="Kildall_1974">{{cite magazine |title=High-level language simplifies microcomputer programming |author-last=Kildall |author-first=Gary Arlen |author-link=Gary Arlen Kildall |website=[[Electronics (magazine)|Electronics]] |publisher=[[McGraw-Hill Education]] |date=1974-06-27 |pages=103–109 [108] |url=https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |access-date=2021-11-14 |url-status=live |archive-url=https://web.archive.org/web/20211114174610/https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |archive-date=2021-11-14}}</ref><ref name="Intel_1975">{{cite web |title=8008 Simulator INTERP/8 |series=Microcomputer Software |publisher=[[Intel Corporation]] |publication-place=Santa Clara, California, USA |date=March 1975 |id=Product Code 98-118A. MCS-514-0375/27.5K |url=https://mark-ogden.uk/files/intel/publications/98-118A%208008%20Simulator%20Interp_8-Mar75.pdf |access-date=2023-11-25 |url-status=live |archive-url=https://web.archive.org/web/20231125173745/https://mark-ogden.uk/files/intel/publications/98-118A%208008%20Simulator%20Interp_8-Mar75.pdf |archive-date=2023-11-25}} (2 pages)</ref>

==Design==
[[File:Intel 8008 arch.svg|thumb|i8008 microarchitecture]]
{| class="infobox" style="font-size:88%;width:29em;"
|+ Intel 8008 registers
|-
| style="text-align:center;"| <sup>1</sup><sub>3</sub>
| style="text-align:center;"| <sup>1</sup><sub>2</sub>
| style="text-align:center;"| <sup>1</sup><sub>1</sub>
| style="text-align:center;"| <sup>1</sup><sub>0</sub>
| style="text-align:center;"| <sup>0</sup><sub>9</sub>
| style="text-align:center;"| <sup>0</sup><sub>8</sub>
| style="text-align:center;"| <sup>0</sup><sub>7</sub>
| style="text-align:center;"| <sup>0</sup><sub>6</sub>
| style="text-align:center;"| <sup>0</sup><sub>5</sub>
| style="text-align:center;"| <sup>0</sup><sub>4</sub>
| style="text-align:center;"| <sup>0</sup><sub>3</sub>
| style="text-align:center;"| <sup>0</sup><sub>2</sub>
| style="text-align:center;"| <sup>0</sup><sub>1</sub>
| style="text-align:center;"| <sup>0</sup><sub>0</sub>
| ''(bit position)''
|-
|colspan="15" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| A
| style="width:auto; background:white; color:black;"| '''A'''ccumulator
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| B
| style="background:white; color:black;"| '''B''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| C
| style="background:white; color:black;"| '''C''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| D
| style="background:white; color:black;"| '''D''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| E
| style="background:white; color:black;"| '''E''' register
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| H
| style="background:white; color:black;"| '''H''' register ''(indirect)''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"| &nbsp;
| style="text-align:center;" colspan="8"| L
| style="background:white; color:black;"| '''L''' register ''(indirect)''
|-
|colspan="15" | '''Program counter'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|-
|colspan="15" | '''Push-down address call stack'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 1
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 2
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 3
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 4
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 5
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 6
|- style="background:silver;color:black"
| style="text-align:center;" colspan="14"| AS
| style="background:white; color:black;"| Call level 7
|-
|colspan="15" | '''Flags'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="10" | &nbsp;
| style="text-align:center;"| [[Carry flag|C]]
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| [[Sign flag|S]]
| style="background:white; color:black" | Flags<ref>{{cite book |title=8008 8 Bit Parallel Central Processor Unit |date=November 1973 |publisher=Intel |pages=14, 17 |edition=Rev 4, Second Printing |url=http://www.bitsavers.org/components/intel/MCS8/Intel_8008_8-Bit_Parallel_Central_Processing_Unit_Rev4_Nov73.pdf |access-date=30 April 2024}}</ref>{{efn|CPZS flags are presented as a group in this order during state 4 of the PCC cycle of the INP instruction.}}
|}

The 8008 was implemented in 10&nbsp;[[micrometre|μm]] silicon-gate enhancement-mode [[PMOS logic]]. Initial versions could work at clock frequencies up to 0.5&nbsp;MHz. This was later increased in the 8008-1 to a specified maximum of 0.8&nbsp;MHz. Instructions take between 3 and 11 T-states, where each T-state is 2 clock cycles.<ref name="MCS8">{{cite web |title=MCS-8 Micro Computer Set Users Manual |publisher=[[Intel Corporation]] |date=1972 |url=http://dunfield.classiccmp.org/mod8/8008um.pdf |access-date=2010-12-04}}</ref>
Register–register loads and ALU operations take 5T (20&nbsp;μs at 0.5&nbsp;MHz), register–memory 8T (32&nbsp;μs), while calls and jumps (when taken) take 11 T-states (44&nbsp;μs).<ref name="pastraiser">{{cite web |title=Intel 8008 Opcodes |url=http://www.pastraiser.com/cpu/i8008/i8008_opcodes.html |access-date=2010-12-04}}</ref>
The 8008 is a little slower in terms of [[instructions per second]] (36,000 to 80,000 at 0.8&nbsp;MHz) than the 4-bit [[Intel 4004]] and [[Intel 4040]].<ref>{{cite web |title=Intel 8008 (i8008) microprocessor family |publisher=CPU World |date=2003–2010 |url=http://www.cpu-world.com/CPUs/8008/index.html |access-date=2010-12-04}}</ref> but since the 8008 processes data 8 bits at a time and can access significantly more RAM, in most applications it has a significant speed advantage over these processors. The 8008 has 3,500 [[transistor]]s.<ref>{{cite web |url=http://www.intel.com/museum/archives/history_docs/Moore.htm |access-date=June 28, 2009 |url-status=dead |archive-url=https://web.archive.org/web/20090904175848/http://www.intel.com/museum/archives/history_docs/Moore.htm |archive-date=2009-09-04 |title=Gordon Moore and Moore's Law |author=Intel}}</ref><ref>Intel (2012). [http://www.intel.com/content/dam/www/public/us/en/documents/corporate-information/history-intel-chips-timeline-poster.pdf "Intel Chips: timeline poster"].</ref><ref>Intel (2008). [http://www.intel.com/pressroom/kits/quickreffam.htm "Microprocessor Quick Reference Guide"].</ref>

The chip, limited by its 18-pin [[dual in-line package|DIP]], has a single 8-bit bus working triple duty to transfer 8 data bits, 14 address bits, and two status bits. The small package requires about 30 TTL support chips to interface to memory.<ref>{{cite book |title=Oral History of Federico Faggin |date=22 September 2004 |publisher=Computer History Museum |page=82 |edition=X2941.2005 |url=http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |access-date=2023-07-14}}</ref> For example, the 14-bit address, which can access "16 K × 8 bits of memory", needs to be latched by some of this logic into an external memory address register (MAR). The 8008 can access 8 [[I/O port|input ports]] and 24 output ports.<ref name="MCS8"/>

For controller and [[Computer terminal|CRT terminal]] use, this is an acceptable design, but it is rather cumbersome to use for most other tasks, at least compared to the next generations of microprocessors. A few early computer designs were based on it, but most would use the later and greatly improved [[Intel 8080]] instead.{{citation needed|date=February 2017}}

=== Related processor designs ===
The subsequent 40-pin [[NMOS logic|NMOS]] [[Intel 8080]] expanded upon the 8008 registers and instruction set and implements a more efficient external bus interface (using the 22 additional pins). Despite a close architectural relationship, the 8080 was not made binary compatible with the 8008, so an 8008 program would not run on an 8080. However, as two different assembly syntaxes were used by Intel at the time, the 8080 could be used in an 8008 assembly-language backward-compatible fashion.

The [[Intel 8085]] is an electrically modernized version of the 8080 that uses [[Depletion-load NMOS logic|depletion-mode]] transistors and also added two new instructions.

The [[Intel 8086]], the original x86 processor, is a non-strict extension of the 8080, so it loosely resembles the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, and [[Zilog Z80|Z80]], but also in the instruction set of modern [[x86]] processors (although the instruction encodings are different).

===Features===
The 8008 architecture includes the following features:{{citation needed|date=February 2017}}
* Seven 8-bit "scratchpad" registers: The main accumulator (A) and six other registers (B, C, D, E, H, and L).
* 14-bit program counter (PC).
* Seven-level push-down address [[call stack]]. Eight registers are actually used, with the top-most register being the PC.
* Four condition code status flags: carry (C), even parity (P), zero (Z), and sign (S).
* Indirect memory access using the H and L registers (HL) as a 14-bit data pointer (the upper two bits are ignored).

==Instruction set==
Instructions are all one to three bytes long, consisting of an initial opcode byte, followed by up to two bytes of operands which can be an immediate operand or a program address. Instructions operate on 8-bits only; there are no 16-bit operations. There is only one mechanism to address data memory: indirect addressing pointed to by a concatenation of the H and L registers, referenced as M. The 8008 does, however, support 14-bit program addresses. It has automatic CAL and RET instructions for multi-level subroutine calls and returns which can be conditionally executed, like jumps. Eight one-byte call instructions (RST) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke interrupt service routines, but can employed as fast calls. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or an immediate value. Results are always deposited in A. Increments and decrements are supported for most registers but, curiously, not A. Register A does, however, support four different rotate instructions. All instructions are executed in 3 to 11 states. Each state requires two clocks.
{|class="wikitable" style="text-align:center"
!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| States ||rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || X || &mdash; || &mdash; ||align=left| {{mono|HLT}} || 4 ||align=left| Halt
|-
| 0 || 0 ||colspan=3|DDD || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| {{mono|INr}} || 5 ||align=left| DDD ← DDD + 1 (except A and M)
|-
| 0 || 0 ||colspan=3|DDD || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| {{mono|DCr}} || 5 ||align=left| DDD ← DDD - 1 (except A and M)
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| {{mono|RLC}} || 5 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
| 0 || 0 ||colspan=3|CC || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| {{mono|Rcc (RET conditional)}} || 3/5 ||align=left| If cc true, P ← (stack)
|-
| 0 || 0 ||colspan=3|ALU || 1 || 0 || 0 || ''data'' || &mdash; ||align=left| {{mono|ADI ACI SUI SBI NDI XRI ORI CPI ''data''}} || 8 ||align=left| A ← A [ALU operation] data
|-
| 0 || 0 ||colspan=3|N || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| {{mono|RST ''n''}} || 5 ||align=left| (stack) ← P, P ← N x 8
|-
| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || ''data'' || &mdash; ||align=left| {{mono|LrI ''data'' (Load r with immediate data)}} || 8/9 ||align=left| DDD ← data
|-
| 0 || 0 || X || X || X || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| {{mono|RET}} || 5 ||align=left| P ← (stack)
|-
| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| {{mono|RRC}} || 5 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
| 0 || 0 || 0 || 1 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| {{mono|RAL}} || 5 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; Cy ← A<sub>7</sub>; A<sub>0</sub> ← Cy
|-
| 0 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| {{mono|RAR}} || 5 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; Cy ← A<sub>0</sub>; A<sub>7</sub> ← Cy
|-
| 0 || 1 ||colspan=3|CC || 0 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|Jcc ''add'' (JMP conditional)}}|| 9/11 ||align=left| If cc true, P ← add
|-
| 0 || 1 || 0 || 0 ||colspan=3|port || 1 || &mdash; || &mdash; ||align=left| {{mono|INP ''port''}} || 8 ||align=left| A ← Port (ports 0-7 only)
|-
| 0 || 1 ||colspan=5|port || 1 || &mdash; || &mdash; ||align=left| {{mono|OUT ''port''}} || 6 ||align=left| Port ← A (ports 8-31 only)
|-
| 0 || 1 ||colspan=3|CC || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|Ccc ''add'' (CAL conditional)}}|| 9/11 ||align=left| If cc true, (stack) ← P, P ← add
|-
| 0 || 1 || X || X || X || 1 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|JMP ''add''}} || 11 ||align=left| P ← add
|-
| 0 || 1 || X || X || X || 1 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|CAL ''add''}} || 11 ||align=left| (stack) ← P, P ← add
|-
| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || &mdash; || &mdash; ||align=left| {{mono|ADr ACr SUr SBr NDr XRr ORr CPr}} || 5/8 ||align=left| A ← A [ALU operation] SSS
|-
| 1 || 1 ||colspan=3|DDD ||colspan=3|SSS || &mdash; || &mdash; ||align=left| {{mono|Lds (Load d with s)}} ||5/7/8 ||align=left| DDD ← SSS
|-
| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| {{mono|HLT}} || 4 ||align=left| Halt
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || States || Description
|-
!colspan=13|
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
|-
|colspan=5| A || 0 || 0 || 0 ||colspan=2|FC, C false ||align=left| {{mono|ADr ADI (A ← A + arg)}}
|-
|colspan=5| B || 0 || 0 || 1||colspan=2|FZ, Z false||align=left| {{mono|ACr ACI (A ← A + arg + Cy)}}
|-
|colspan=5| C || 0 || 1 || 0||colspan=2|FS, S false ||align=left| {{mono|SUr SUI (A ← A - arg)}}
|-
|colspan=5| D || 0 || 1 || 1||colspan=2|FP, P odd ||align=left| {{mono|SBr SBI (A ← A - arg - Cy)}}
|-
|colspan=5| E || 1 || 0 || 0||colspan=2|TC, C true ||align=left| {{mono|NDr NDI (A ← A ∧ arg)}}
|-
|colspan=5| H || 1 || 0 || 1||colspan=2|TZ, Z true ||align=left| {{mono|XRr XRI (A ← A ⊻ arg)}}
|-
|colspan=5| L || 1 || 1 || 0||colspan=2|TS, S true ||align=left| {{mono|ORr ORI (A ← A ∨ arg)}}
|-
|colspan=5| M || 1 || 1 || 1||colspan=2|TP, P even ||align=left| {{mono|CPr CPI (A - arg)}}
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU
|}
===Code example 1===
[[File:Intel 8008 wafer.jpg|thumb|Intel 8008 wafer and two processors, closed and open]]
The following 8008 [[assembly language|assembly]] source code is for a subroutine named <code>MEMCPY</code> that copies a block of data bytes of a given size from one location to another. Intel's 8008 assembler supported only + and - operators. This example borrows the 8080's assembler AND and SHR (shift right) operators to select the low and high bytes of a 14-bit address for placement into the 8 bit registers. A contemporaneous 8008 programmer was expected to calculate the numbers and type them in for the assembler.
<!--NOTE: This is not intended to be optimized code, but to illustrate the variety of instructions available on the CPU-->
{|
|
<pre>
                   
                   
                   
                   
                   
                   
                   
                   
                   
001700  000        
001701  000        
001702  000        
001703  000        
001704  000        
001705  000        
                   
                   
002000  066 304    
002002  056 003    
002004  327        
002005  060        
002006  317        
002007  302        
002010  261        
002011  053        
002012  302        
002013  024 001    
002015  320        
002016  301        
002017  034 000    
002021  310        
002022  066 300    
002024  056 003    
002026  302        
002027  207        
002030  340        
002031  060        
002032  301        
002033  217        
002034  350        
002035  364        
002036  337        
002037  066 302    
002041  056 003    
002043  302        
002044  207        
002045  340        
002046  060        
002047  301        
002050  217        
002051  350
002052  364
002053  373        
002054  104 007 004
002057             
</pre>
|
<syntaxhighlight lang="nasm">
; MEMCPY --
; Copy a block of memory from one location to another.
;
; Entry parameters
;       SRC: 14-bit address of source data block
;       DST: 14-bit address of target data block
;       CNT: 14-bit count of bytes to copy
 
            ORG     1700Q       ;Data at 001700q
SRC         DFB     0           ;SRC, low byte
            DFB     0           ;     high byte
DST         DFB     0           ;DST, low byte
            DFB     0           ;     high byte
CNT         DFB     0           ;CNT, low byte
            DFB     0           ;     high byte
 
            ORG     2000Q       ;Code at 002000q
MEMCPY      LLI     CNT AND 255 ;HL = addr(CNT)
            LHI     CNT SHR 8   ;(AND and SHR not supported)
            LCM                 ;BC = CNT
            INL
            LBM
LOOP        LAC                 ;If BC = 0,
            ORB
            RTZ                 ;Return
DECCNT      LAC                 ;BC = BC - 1
            SUI     1
            LCA
            LAB
            SBI     0
            LBA
GETSRC      LLI     SRC AND 255 ;HL = addr(SRC)
            LHI     SRC SHR 8
            LAC                 ;HL = SRC + BC
            ADM                 ;E = C + (HL)
            LEA                 ;(lower sum)
            INL                 ;point to upper SRC
            LAB
            ACM                 ;H = B + (HL) + CY
            LHA                 ;(upper sum)
            LLE                 ;L = E
            LDM                 ;Load D from (HL)
GETDST      LLI     DST AND 255 ;HL = addr(DST)
            LHI     DST SHR 8
            LAC                 ;HL = DST + BC
            ADM                 ;ADD code same as above
            LEA
            INL 
            LAB
            ACM
            LHA
            LLE
            LMD                 ;Store D to (HL)
            JMP     LOOP        ;Repeat the loop
            END
</syntaxhighlight>
|}

In the code above, all values are given in octal. Locations {{code|SRC}}, {{code|DST}}, and {{code|CNT}} are 16-bit parameters for the subroutine named {{code|MEMCPY}}. In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored in [[little-endian]] format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with the {{code|CNT}} parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode.

===Code example 2===
The following 8008 assembly source code is for a simplified subroutine named MEMCPY2 that copies a block of data bytes from one location to another. By reducing the byte counter to 8 bits, there is enough room to load all the subroutine parameters into the 8008's register file.
<!--This routine was assembled by brain and might contain errors-->
{|
|
<pre>
                   
                   
                   
                   
                   
                   
                   
                   
    
002000  307    
002001  206 015 004
002004  370        
002005  206 015 004
002010  021        
002011  110 000 004
002014  007        
        
          
002015  316
002016  364        
002017  341        
002020  315
002021  353        
002022  331
002023  040
002024  013 
002025  030 
002026  007        
002027             
</pre>
|
<syntaxhighlight lang="nasm">
; MEMCPY2 --
; Copy a block of memory from one location to another
;
; Entry parameters in registers
;       HL: 14-bit address of source data block
;       DE: 14-bit address of target data block
;       C: 8-bit count of bytes to copy. (1 to 256 bytes)
 
            ORG     2000Q       ;Code at 002000q
MEMCPY2     LAM                 ;Read source byte into A
            CAL     XCHGI       ;Exchange HL<->DE and increment DE
            LMA                 ;Save A to target byte
            CAL     XCHGI       ;Exchange HL<->DE and increment DE
            DCC                 ;Decrement byte counter
            JFZ     MEMCPY2     ;Continue for all bytes
            RET
            
;Exchange DE and HL register pairs then increment DE as 16 bits
XCHGI       LBL                 ;Exchange L and E
            LLE
            LEB
            LBH                 ;Exchange H and D
            LHD
            LDB
            INE                 ;Inc E, low byte of DE
            RFZ                 ;Return if no carry
            IND                 ;Otherwise inc high byte D
            RET
            END
</syntaxhighlight>
|}

==Interrupts==
[[File:JB.SIM8-01.jpg|thumb|Intel SIM8-01 CPU board, possibly the first use of the 8008. Contains 1K bytes of RAM in 32 chips and 2K byte of EPROM in eight chips. No provision for interrupts.]]
[[Interrupt|Interrupts]] on the 8008 are only partially implemented. After the INT line is asserted, the 8008 acknowledges the interrupt by outputting a state code of S0,S1,S2 = 011 at T1I time. At the subsequent instruction fetch cycle, an instruction is "jammed" (Intel's word) by external hardware on the bus. Typically this is a one-byte RST instruction.

At this point, there is a problem. The 8008 has no provision to save its [[architectural state]]. The 8008 can only write to memory via an address in the HL register pair. When interrupted, there is no mechanism to save HL so there is no way to save the other registers and flags via HL. Because of this, some sort of external memory device such as a hardware [[Stack (abstract data type)|stack]] or a pair of read/write [[Hardware register|registers]] must be attached to the 8008 via the I/O ports to help save the state of the 8008.<ref>{{cite journal |last1=Chamberklin |first1=Hal |title="Add a Stack to your 8008 |journal=Byte |date=October 1975 |volume=0 |issue=2 |pages=52–56 |url=https://archive.org/details/byte-magazine-1975-10/page/n53/mode/2up |access-date=5 October 2024}}</ref>

==Designers==
*'''CTC''' (''Instruction set and architecture''): [[Victor Poor]] and [[Harry Pyle]].
*'''Intel''' (''Implementation in silicon''):
** [[Marcian Hoff|Ted Hoff]] and [[Stanley Mazor|Stan Mazor]] proposed a single-chip implementation of the CTC architecture, using RAM-register memory rather than shift-register memory, and also added a few instructions and interrupt facility. The 8008 (originally called 1201) chip design started before the 4004 development. Hoff and Mazor, however, could not and did not develop a "silicon design" because they were neither chip designers nor process developers, and furthermore the necessary [[bootstrap load]] silicon-gate-based design methodology and circuits, under development by Federico Faggin for the 4004, were not yet available.<ref>{{cite journal |author-last1=Faggin |author-first1=Federico |author-link1=Federico Faggin |author-last2=Hoff, Jr. |author-first2=Marcian E. |author-link2=Marcian Hoff |author-last3=Mazor |author-first3=Stanley |author-link3=Stanley Mazor |author-last4=Shima |author-first4=Masatoshi |author-link4=Masatoshi Shima |title=The History of the 4004 |journal=IEEE Micro |volume=16 |issue=6 |pages=10–19 |publisher=IEEE Computer Society |location=Los Alamitos, USA |date=December 1996 |issn=0272-1732 |doi=10.1109/40.546561}}</ref><!-- also dubious; neither Hoff nor Mazor were process designers, but Hoff developed dynamic ram, so he could be a chip designer. Hoff, Mazor, and a process engineer (who was not Faggin) were responsible for NPULS (SPICE-like) circuit models and circuit simulations. Mazor was running architecture simulations. -->
** [[Federico Faggin]], having finished the design of the 4004, became leader of the project from January 1971 until its successful completion in April 1972, after it had been suspended – for lack of progress – for about seven months. 
** [[Hal Feeney]], project engineer, did the detailed logic design, circuit design, and physical layout under Faggin's supervision, employing the same design methodology that Faggin had originally developed for the Intel 4004 microprocessor, and utilizing the basic circuits he had developed for the 4004. A combined "HF" logo was etched onto the chip about halfway between the D5 and D6 bonding pads.<!-- Need an image for this claim |date=October 2017 -->

==Second sources==
<gallery caption="Intel 8008 [[second source]]s" mode="packed" heights="150px">
image:KL MME U808.jpg|[[Kombinat Mikroelektronik Erfurt|VEB Mikroelektronik "Karl Marx" Erfurt (MME)]] U808 ([[GDR]])
image:KL MF8008.jpg|[[MicroSystems International]] (MIL) MF8008
image:Siemens SAB8008 1C 1.jpg|[[Siemens]] SAB8008
</gallery>

==See also==
* [[Intel Intellec 8]]
* [[Mark-8]] and [[SCELBI]], 8008-based computer kits
* [[MCM/70]] and [[Micral]], pioneering microcomputers
* [[PL/M]], the first programming language targeting a microprocessor, the Intel 8008, developed by [[Gary Kildall]]

==Notes==
{{Notelist}}

==References==
{{Reflist|30em}}

==External links==
* [http://dunfield.classiccmp.org/mod8/8008um.pdf MCS-8 User Manual] with 8008 data sheet (1972)
* {{cite news |url=http://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |newspaper=Computer World |author-first=Lamont |author-last=Wood |date=2008-08-08 |title=Forgotten PC history: The true origins of the personal computer |access-date=2014-12-02  |archive-date=2018-11-16  |archive-url=https://web.archive.org/web/20181116163842/https://www.computerworld.com/article/2532590/computer-hardware/forgotten-pc-history--the-true-origins-of-the-personal-computer.html |url-status=dead }}
* [http://petsd.net/8008.php The Intel 8008 support page] unofficial
* {{cite book |url=http://donbot.com/MicrocomputerDesign/First_Edition/F001.html |author-first=Donald P. |author-last=Martin |title=Microcomputer Design |publisher=[[Martin Research]] |date=1974}}
** {{cite book |url=http://donbot.com/MicrocomputerDesign/SE/M001.html |author-mask=1 |author-first1=Donald P. |author-last1=Martin |title=Microcomputer Design |edition=2 |date=1976 |publisher=[[Martin Research]] |oclc=911808003}} 
* {{cite journal |url=https://archive.org/details/kilobaudmagazine-1977-04 |author-first=Grant |author-last=Runyan |title=Now — BASIC for the 8008 — Even! |journal=Kilobaud Magazine |date=April 1977 |pages=116–118}}
* {{cite web |url=https://archive.org/details/basiclanguageint658weav |title=A BASIC language interpreter for the Intel 8008 microprocessor |publisher=University of Illinois |date=1974}}
*[http://bitsofthegoldenage.org/download/intel-8008-reference-card/ 8008 Assembly Language Reference Card]
* {{cite web |author-first=Ken |author-last=Shirriff |title=Die photos and analysis of the revolutionary 8008 microprocessor, 45 years old |date=December 2016 |url=http://www.righto.com/2016/12/die-photos-and-analysis-of_24.html}}
** {{cite web |author-mask=1 |author-first1=Ken |author-last1=Shirriff |title=Reverse-engineering the surprisingly advanced ALU of the 8008 microprocessor |date=February 2017 |url=http://www.righto.com/2017/02/reverse-engineering-surprisingly.html}}
** {{cite web |author-mask=1 |author-first1=Ken |author-last1=Shirriff |title=How the bootstrap load made the historic Intel 8008 processor possible |date=October 2020 |url=http://www.righto.com/2020/10/how-bootstrap-load-made-historic-intel.html}}
** {{cite web |author-mask=1 |author-first1=Ken |author-last1=Shirriff |title=Reverse-engineering the carry-lookahead circuit in the Intel 8008 processor |date=November 2020 |url=http://www.righto.com/2020/11/reverse-engineering-carry-lookahead.html}}

{{Intel processors|discontinued}}
[[Category:Intel microprocessors|8008]]
[[Category:8-bit microprocessors]]
[[Category:Computer-related introductions in 1972]]