Editing Intel 8086

{{Short description|16-bit microprocessor}}
{{Refimprove|date=June 2024}}
{{Infobox CPU
| name = Intel 8086
| image = Intel C8086.jpg
| caption = A rare Intel C8086 processor in purple ceramic DIP package with side-brazed pins
| produced-start = 1978
| produced-end = 1998<ref>{{Cite web |title=The Life Cycle of a CPU |url=https://www.cpushack.com/life-cycle-of-cpu.html |website=www.cpushack.com|access-date=26 January 2025}}</ref>
| slowest = 5 | slow-unit = MHz
| fastest = 10 | fast-unit = MHz
| manuf1 = [[Intel]], [[AMD]], [[NEC]], [[Fujitsu]], [[Harris Corporation|Harris]] ([[Intersil]]), [[Oki Electric Industry|OKI]], [[Siemens]], [[Texas Instruments]], [[Mitsubishi Electric|Mitsubishi]], [[Panasonic]] (Matsushita)
| arch = [[x86-16]]
| pack1 = 40 pin [[dual in-line package]]
| predecessor = [[Intel 8085]]
| variant = [[Intel 8088|8088]]
| successor = [[Intel 80186|80186]] and [[Intel 80286|80286]] (both of which were introduced in early 1982)
| co-processor  = [[Intel 8087]], [[Intel 8089]]
| size-from = [[3 μm process|3&nbsp;μm]]
| data-width = 16 bits
| address-width = 20 bits
| sock1 = [[Dual in-line package|DIP40]]
| transistors=29,000<ref>Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2</ref>
| support status = Unsupported
}}

The '''8086'''<ref>{{cite web  |title=Microprocessor Hall of Fame  |url=http://www.intel.com/museum/online/hist%5Fmicro/hof/ |publisher=Intel |access-date=2007-08-11 |archive-url=https://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/ |archive-date=2007-07-06}}</ref> (also called '''iAPX 86''')<ref name="i286">{{cite book|url=http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference |page= 1-1 |publisher=Intel |year=1983}}</ref> is a [[16-bit computing|16-bit]] [[microprocessor]] chip designed by [[Intel]] between early 1976<ref>{{Cite book |last1=Szewczyk |first1=Roman |url=https://books.google.com/books?id=yM1sCwAAQBAJ&pg=PA67 |title=Embedded Engineering Education |last2=Kaštelan |first2=Ivan |last3=Temerinac |first3=Miodrag |last4=Barak |first4=Moshe |last5=Sruk |first5=Vlado |date=2016-01-19 |publisher=Springer |isbn=978-3-319-27540-6 |language=en}}</ref> and June 8, 1978, when it was released.<ref name="Intel">{{cite press release|date=5 June 2018|url-status=dead|archive-url=https://web.archive.org/web/20230212150554/https://newsroom.intel.com/news/intel-i7-8086k-processor/|archive-date=12 February 2023|title=Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience|work=Intel Newsroom |url=https://newsroom.intel.com/news/intel-i7-8086k-processor/|publisher=Intel}}</ref> The [[Intel 8088]], released July 1, 1979,<ref>{{cite web|url=https://timeline.intel.com/1979/the-8088-processor|title=The 8088 Processor|website=timeline.intel.com|publisher=Intel|access-date=26 January 2025}}</ref> is a slightly modified chip with an external 8-bit [[Bus (computing)|data bus]] (allowing the use of cheaper and fewer supporting [[Integrated circuit|IC]]s),<ref group="note">Fewer TTL buffers, latches, multiplexers (although the amount of TTL  <u>logic</u> was not drastically reduced). It also permits the use of cheap 8080-family ICs, where the 8254 CTC, [[Intel 8255|8255]] PIO, and 8259 PIC were used in the IBM PC design. In addition, it makes PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.</ref> and is notable as the processor used in the original [[IBM Personal Computer|IBM PC]] design.

The 8086 gave rise to the [[x86]] architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released a limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called the [[Coffee Lake|Intel Core i7-8086K]].<ref name="Intel"/>

==History==

===Background===
In 1972, Intel launched the [[Intel 8008|8008]], Intel's first 8-bit microprocessor.<ref group="note" >using enhancement load [[PMOS logic]] (requiring 14&nbsp;[[Volt|V]], achieving TTL compatibility by having V<sub>CC</sub> at +5&nbsp;V and V<sub>DD</sub> at −9&nbsp;V).</ref> It implemented an [[instruction set]] designed by [[Datapoint|Datapoint Corporation]] with programmable [[Computer terminal|CRT terminals]] in mind, which also proved to be fairly general-purpose. The device needed several additional [[Integrated circuit|IC]]s to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily a [[DRAM]] manufacturer at the time).

Two years later, Intel launched the [[Intel 8080|8080]], employing the new 40-pin [[Dual in-line package|DIL package]]s originally developed for [[calculator]] ICs to enable a separate address bus. It had an extended instruction set that is [[source-compatible]] (not [[binary compatible]]) with the 8008<ref>{{Cite web
  |website=CPU World
  |title=8080 family
  |url=https://www.cpu-world.com/CPUs/8080/
}}</ref> and also included some [[16-bit computing|16-bit]] instructions to make programming easier. The 8080 device was eventually replaced by the [[Depletion-load NMOS logic|depletion-load]]-based [[Intel 8085|8085]] (1977), which used a single +5&nbsp;V power supply instead of the three different operating voltages of earlier chips.<ref group="note">Made possible with depletion-load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086).</ref> Other well known 8-bit microprocessors that emerged during these years are [[Motorola 6800]] (1974), [[PIC microcontroller|General Instrument PIC16X]] (1975), [[MOS Technology 6502]] (1975), [[Zilog Z80]] (1976), and [[Motorola 6809]] (1978).

===The first x86 design===
[[File:Intel 8086 CPU Die.JPG|thumb|Intel 8086 CPU die image]]
The 8086 project started in May 1976<ref>{{Cite web |title=Birth of a standard: The Intel 8086 microprocessor turns 40 today |url=https://www.pcworld.com/article/535966/article-7512.html |access-date=2025-03-08 |website=PCWorld |language=en}}</ref> and was originally intended as a temporary substitute for the ambitious and delayed [[iAPX 432]] project. It was an attempt to draw attention from the less-delayed 16-bit and [[32-bit computing|32-bit]] processors of other manufacturers — [[Motorola]], [[Zilog]], and [[National Semiconductor]].

Whereas the 8086 was a 16-bit microprocessor, it used the same [[microarchitecture]] as Intel's 8-bit microprocessors (8008, 8080, and 8085). This allowed [[assembly language]] programs written in 8-bit to [[Assembly language translator|seamlessly migrate]].<ref name="Scanlon_1988"/> New instructions and features — such as signed integers, base+offset addressing, and self-repeating operations — were added. Instructions were added to assist source code compilation of [[nested function]]s in the [[ALGOL]]-family of languages, including [[Pascal (programming language)|Pascal]] and [[PL/M]]. According to principal architect [[Stephen P. Morse]], this was a result of a more software-centric approach. Other enhancements included [[microcode]] instructions for the multiply and divide assembly language instructions. Designers also anticipated [[coprocessors]], such as [[Intel 8087|8087]] and [[Intel 8089|8089]], so the bus structure was designed to be flexible.

The first revision of the instruction set and high level architecture was ready after about three months,<ref group="note" >Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.</ref> and as almost no CAD tools were used, four engineers and 12&nbsp;layout people were simultaneously working on the chip.<ref group="note" >Using [[rubylith]], light boards, rulers, electric erasers, and a [[digitizer]] (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's webpage for its 25th birthday).</ref> The 8086 took a little more than two years from idea to working product, which was considered fast for a complex design in the 1970s.

The 8086 was sequenced<ref group="note" >8086 used less microcode than many competitors' designs, such as the MC68000 and others</ref> using a mixture of [[random logic]]<ref>{{cite book |first1=Randall L. |last1=Geiger |first2=Phillip E. |last2=Allen |first3=Noel R. |last3=Strader |title=VLSI design techniques for analog and digital circuits |publisher=McGraw-Hill |year=1990 |isbn=0-07-023253-9 |pages=779 |chapter=Random Logic vs. Structured Logic Forms}} — Illustration of use of "random" describing CPU control logic</ref> and [[microcode]] and was implemented using depletion-load nMOS circuitry with approximately 20,000&nbsp;active [[transistor]]s (29,000 counting all [[read-only memory|ROM]] and [[Programmable logic array|PLA]] sites). It was soon moved to a new refined nMOS manufacturing process called [[HMOS]] (for High performance MOS) that Intel originally developed for manufacturing of fast [[static RAM]] products.<ref group="note" >Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period.</ref> This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static [[CMOS]] version for battery powered devices, manufactured using Intel's [[CHMOS]] processes.<ref group="note" >CHMOS is Intel's name for CMOS circuits manufactured using processing steps very similar to [[HMOS]].</ref> The original chip measured 33&nbsp;mm² and minimum feature size was 3.2&nbsp;μm. The MUL and DIV instructions were very slow due to being microcoded so x86 programmers usually just used the bit shift instructions for multiplying and dividing instead. {{Dubious|1=MUL and DIV|reason=Programmers use shifts for powers of two and shift/adds/subs for small multipliers but it is impossible to write a general 16 x 16 bit multiply on the 8086 that is faster than the MUL instruction|date=December 2024}}

The 8086 was die-shrunk to 2 μm in 1981; this version also corrected a stack register bug in the original 3.5 μm chips.{{clarification needed|date=April 2025}} Later 1.5 μm and CMOS variants were outsourced to other manufacturers and not developed in-house.{{citation needed|date=April 2025}}

The architecture was defined by [[Stephen P. Morse]] with some help from Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<ref group="note" >Other members of the design team were Peter A.Stoll and Jenny Hernandez.</ref> and Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the [[Intel 286]] and the [[Intel 386]], all of which eventually became known as the [[x86]] family. (Another reference is that the [[PCI Configuration Space|PCI Vendor ID]] for Intel devices is 8086<sub>h</sub>.)

==Details==
[[File:Intel 8086 pinout.svg|thumb|300px|The 8086 pin assignments in min and max mode]]

===Buses and operation===
All internal registers, as well as internal and external data buses, are 16&nbsp;bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1&nbsp;[[Mebibyte|MiB]] physical address space (2<sup>20</sup> = 1,048,576 x 1 [[byte]]). This address space is addressed by means of internal memory "segmentation". The data bus is [[multiplexed]] with the address bus in order to fit all of the control lines into a standard 40-pin [[dual in-line package]]. It provides a 16-bit I/O address bus, supporting 64&nbsp;[[Kilobyte|KB]] of separate I/O space. The maximum linear address space is limited to 64&nbsp;KB, simply because internal address/index registers are only 16&nbsp;bits wide. Programming over 64&nbsp;KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the [[80386]] architecture introduced wider (32-bit) registers (the memory management hardware in the [[80286]] did not help in this regard, as its registers are still only 16 bits wide).

===Hardware modes of 8086===
Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in ''min'' or ''max'' mode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using an 8087 or 8089 coprocessor. The voltage on pin 33 (MN/{{overline|MX}}) determines the mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus.<ref group="note" >The IBM PC and PC/XT use an Intel 8088 running in maximum mode, which allows the CPU to work with an optional 8087 coprocessor installed in the math coprocessor socket on the PC or PC/XT mainboard. (The PC and PC/XT may require maximum mode for other reasons, such as perhaps to support the DMA controller.)</ref> The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by the 8086 itself.

===Registers and instruction===
{| class="infobox" style="font-size:88%;width:38em;"
|-
|+ Intel 8086 registers
|-
|
{| style="font-size:88%;"
|-
| style="width:10px; text-align:center;"| <sup>1</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|-
|colspan="21" | '''Main registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| AH
| style="text-align:center;" colspan="8"| AL
| style="background:white; color:black;"| '''[[Accumulator (computing)|AX]]''' (primary accumulator)
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="8"| BH
| style="text-align:center;" colspan="8"| BL
| style="background:white; color:black;"| '''BX''' (base, accumulator)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| CH
| style="text-align:center;" colspan="8"| CL
| style="background:white; color:black;"| '''CX''' (counter, accumulator)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;" colspan="8"| DH
| style="text-align:center;" colspan="8"| DL
| style="background:white; color:black;"| '''DX''' (accumulator, extended acc)
|-
|colspan="21" | '''Index registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Index register|SI]]
| style="background:white; color:black;"| '''S'''ource '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| DI
| style="background:white; color:black;"| '''D'''estination '''I'''ndex
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| BP
| style="background:white; color:black;"| '''B'''ase '''P'''ointer
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Stack register|SP]]
| style="background:white; color:black;"| '''S'''tack '''P'''ointer
|-
|colspan="21" | '''Program counter''' <br />
|- style="background:silver;color:black"
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="text-align:center;" colspan="16"| [[Program counter|IP]]
| style="background:white; color:black;"| '''I'''nstruction '''P'''ointer
|-
|colspan="21" | '''Segment registers''' <br />
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| CS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''C'''ode '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| DS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''D'''ata '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| ES
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''E'''xtra '''S'''egment
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| SS
| style="text-align:center;background:#DDD" colspan="4"| 0&nbsp;0&nbsp;0&nbsp;0
| style="background:white; color:black;"| '''S'''tack '''S'''egment
|-
|colspan="21" | '''Status register'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="4"| &nbsp;
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| -
| style="text-align:center;"| [[Overflow flag|O]]
| style="text-align:center;"| [[Direction flag|D]]
| style="text-align:center;"| [[IF (x86 flag)|I]]
| style="text-align:center;"| [[Trap flag|T]]
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Adjust flag|A]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| -
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | Flags
|}
|}
The 8086 has eight more-or-less general 16-bit [[processor register|registers]] (including the [[Stack-based memory allocation|stack pointer]] but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.

Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the ''destination'', while the other operand, the ''source'', can be either ''register'' or ''immediate''. A single memory location can also often be used as both ''source'' and ''destination'' which, among other factors, further contributes to a [[code density]] comparable to (and often better than) most eight-bit machines at the time.

The degree of generality of most registers is much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary [[minicomputer]]s and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the [[PDP-11]], [[VAX]], [[68000]], [[32016]], etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the [[MOS Technology 6502|6502]], [[Motorola 6800|6800]], [[6809]], [[Intel 8085|8085]], [[MCS-48]], [[Intel 8051|8051]], and other contemporary accumulator-based machines, it is significantly easier to construct an efficient [[code generation (compiler)|code generator]] for the 8086 architecture.

Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and [[PL/M]]; some of the more useful instructions are <code>'''push''' ''mem-op''</code>, and '''ret''' ''size'', supporting the "Pascal [[calling convention]]" directly. (Several others, such as <code>'''push'''&nbsp;''immed''</code> and <code>'''enter'''</code>, were added in the subsequent 80186, 80286, and 80386 processors.)

A 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] growing towards lower addresses is supported in [[computer hardware|hardware]]; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256&nbsp;[[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[return address (computing)|return address]]es.

The 8086 has 64&nbsp;K of 8-bit (or alternatively 32&nbsp;K of 16-bit word) [[I/O port]] space.

===Flags===
The 8086 has a 16-bit [[status register|flags register]]. Nine of these condition code flags are active, and indicate the current state of the processor: [[Carry flag]] (CF), [[Parity flag]] (PF), [[Auxiliary flag|Auxiliary carry flag]] (AF), [[Zero flag]] (ZF), [[Sign flag]] (SF), [[Trap flag]] (TF), [[IF (x86 flag)|Interrupt flag]] (IF), [[Direction flag]] (DF), and [[Overflow flag]] (OF).
Also referred to as the status word, the layout of the flags register is as follows:<ref>{{Cite book |title=IAPX 86, 88, 186, and 188 user's manual : programmer's reference |author=Intel Corporation |year=1983 |isbn=978-0835930352 |oclc=11091251 |pages=3–5|publisher=Intel }}</ref>
{| class="wikitable"
! Bit
| 15-12
| 11
| 10
| 9
| 8
| 7
| 6
| 5
| 4
| 3
| 2
| 1
| 0
|-
! Flag
| &nbsp;
| OF
| DF
| IF
| TF
| SF
| ZF
| &nbsp;
| AF
| &nbsp;
| PF
| &nbsp;
| CF
|}
===Segmentation===
{{See also|x86 memory segmentation}}
There are also four 16-bit [[x86 memory segmentation|segment]] registers (see figure) that allow the 8086 [[Central processing unit|CPU]] to access one [[megabyte]] of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, any external address could be referred to by up to 2<sup>12</sup> = 4096 different segment:offset pairs.<ref>{{cite web |last1=Sedory |first1=Daniel B|title=The Segment:Offset Addressing Scheme |url=https://thestarman.pcministry.com/asm/debug/Segments.html |website=thestarman.pcministry.com |access-date=6 March 2025}}</ref>

{| style="margin-left:5em"
|-
| <code>&nbsp; </code><code style="background:#DED">0110 1000 1000 0111</code><code>0000</code>
| '''Segment''',
| 16 bits, shifted 4 bits left (or multiplied by 0x10)
|-
| <code>+ &nbsp;&nbsp;&nbsp;&nbsp; </code><code style="background:#DDF">1011 0100 1010 1001</code>
| '''Offset''',
| 16 bits
|- style="text-decoration:line-through"
| <code>&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</code>
|
|-
| <code>&nbsp; </code><code style="background:#FDF">0111 0011 1101 0001 1001</code>
| '''Address''',
| 20 bits
|}

Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64&nbsp;KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for [[Relocation (computing)|relocation]], with at most 15&nbsp;bytes of alignment waste.

Compilers for the 8086 family commonly support two types of [[pointer (computer programming)|pointer]], ''near'' and ''far''. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support ''huge'' pointers, which are like far pointers except that [[pointer arithmetic]] on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer [[integer overflow|wraps around]] within its 16-bit offset without touching the segment part of the address.

To avoid the need to specify ''near'' and ''far'' on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The ''tiny'' (max 64K), ''small'' (max 128K), ''compact'' (data > 64K), ''medium'' (code > 64K), ''large'' (code,data > 64K), and ''huge'' (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The ''tiny'' model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build ''[[COM file|.com]]'' files for instance. Precompiled libraries often come in several versions compiled for different memory models.

According to Morse et al.,.<ref>{{cite journal |first1=Stephen P. |last1=Morse |first2=Bruce W |last2=Ravenel |first3=Stanley |last3=Mazor |first4=William B. |last4=Pohlman |title=Intel Microprocessors: 8008 to 8086 |journal=IEEE Computer |volume=13 |issue=10 |pages=42–60 |date=October 1980 |doi=10.1109/MC.1980.1653375 |s2cid=206445851 |url=https://stevemorse.org/8086history/8086history.doc|url-access=subscription }}</ref> the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16&nbsp;MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1&nbsp;MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins.

In principle, the address space of the x86 series ''could'' have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<ref group="note" >Some 80186 clones did change the shift value, but were never commonly used in desktop computers.</ref> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way.

The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of the instruction stream to be queued while waiting for decoding and execution. The queue acts as a First-In-First-Out (FIFO) buffer, from which the Execution Unit (EU) extracts instruction bytes as required. Whenever there is space for at least two bytes in the queue, the BIU will attempt a word fetch memory cycle. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.<ref name="8086Datasheet">{{cite web |title=8086 16-BIT HMOS Processor datasheet |url=https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf |publisher=Intel |access-date=26 November 2021 |archive-date=26 November 2021 |archive-url=https://web.archive.org/web/20211126175101/https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf |url-status=dead }}</ref>

====Porting older software====
Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows [[8-bit computing|8-bit]] software to be quite easily ported to the 8086. The authors of most [[DOS]] implementations took advantage of this by providing an [[Application Programming Interface]] very similar to [[CP/M]] as well as including the simple ''.com'' executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform.

== Example code ==
The following 8086 [[assembly language|assembly]] source code is for a subroutine named <code>_strtolower</code> that copies a null-terminated [[ASCIIZ]] character string from one location to another, converting all alphabetic characters to lower case. The string is copied one byte (8-bit character) at a time.

<!--NOTE: The hex codes were assembled by hand, so there may be errors-->
{| style="font-size:70%"
|
<!--NOTE: DO NOT REMOVE BLANK LINES, 0000 line sets block width--><pre>









0000            
0000  55
0001  89 E5
0003  56
0004  57
0005  8B 75 06
0008  8B 7D 04
000B  FC

000C  AC
000D  3C 41
000F  7C 06
0011  3C 5A
0013  7F 02
0015  04 20
0017  AA
0018  08 C0
001A  75 F0

001C  5F
001D  5E
001E  5D
001F  C3
001F 
</pre>
|
<syntaxhighlight lang="nasm">
; _strtolower:
; Copy a null-terminated ASCII string, converting
; all alphabetic characters to lower case.
; ES=DS
; Entry stack parameters
;   [SP+4] = src, Address of source string
;   [SP+2] = dst, Address of target string
;   [SP+0] = Return address
;
_strtolower proc
            push    bp              ;Set up the call frame
            mov     bp,sp
            push    si
            push    di
            mov     si,[bp+6]       ;Set si = src (+2 due to push bp)
            mov     di,[bp+4]       ;Set di = dst
            cld                     ;string direction ascending
            
loop:       lodsb                   ;Load al from [si], inc si
            cmp     al,'A'          ;If al < 'A',
            jl      copy            ; skip conversion
            cmp     al,'Z'          ;If al > 'Z',
            jg      copy            ; skip conversion
            add     al,'a'-'A'      ;Convert al to lowercase
copy:       stosb                   ;Store al to es:[di], inc di
            or      al,al           ;If al <> 0,
            jne     loop            ; repeat the loop
            
done:       pop     di              ;restore di and si
            pop     si
            pop     bp              ;Restore the prev call frame
            ret                     ;Return to caller
            end     proc
</syntaxhighlight>
|}

The example code uses the BP (base pointer) register to establish a [[call frame]], an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of [[calling convention]] supports [[reentrancy (computing)|reentrant]] and [[recursion (computer science)|recursive]] code and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed, specifically, that the DS and ES segments address the same region of memory.

===Performance===
[[File:Intel 8086 block scheme.svg|thumb|405px|''Simplified block diagram over Intel 8088 (a variant of 8086); 1=main & index registers; 2=segment registers and IP; 3=address adder; 4=internal address bus; 5=instruction queue; 6=control unit (very simplified!); 7=bus interface; 8=internal databus; 9=ALU; 10/11/12=external address/data/control bus.'']]

Although partly shadowed by other design choices in this particular chip, the [[multiplexed]] address and [[Bus (computing)|data buses]] limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made [[Concurrency (computer science)|concurrent]] and decoupled into separate units (as it remains in today's x86 processors): The ''bus interface unit'' feeds the instruction stream to the ''execution unit'' through a 6-byte prefetch queue (a form of loosely coupled [[Pipeline (computing)|pipelining]]), speeding up operations on [[Processor register|register]]s and [[Operand|immediate]]s, while memory operations became slower (four years later, this performance problem was fixed with the [[80186]] and [[80286]]). However, the full (instead of partial) 16-bit architecture with a full width [[Arithmetic logic unit|ALU]] meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with [[orthogonalization]]s of operations versus [[operand]] types and [[addressing mode]]s, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below).

{| class="wikitable" style="text-align: center; width: 100px; height: 50px;"
|+ Execution times for typical instructions (in clock cycles)<ref>{{cite book|title=Microsoft Macro Assembler 5.0 Reference Manual|year=1987|publisher=Microsoft Corporation| quote=Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986.|title-link=MASM}} (Similarly for iAPX 286, 80386, 80387.)</ref>
|-  style="vertical-align:bottom; border-bottom:3px double #999;"
!align=left | instruction
!align=left | register-register
!align=left | register immediate
!align=left | register-memory
!align=left | memory-register
!align=left | memory-immediate
|-  style="vertical-align:top; border-bottom:1px solid #999;"
|mov || 2 || 4|| 8+EA || 9+EA || 10+EA
|-  style="vertical-align:top; border-bottom:1px solid #999;"
|ALU || 3 ||4|| 9+EA, || 16+EA,|| 17+EA
|-  style="vertical-align:top; border-bottom:1px solid #999;"
|jump || colspan="5" | ''register'' ≥ 11 ; ''label'' ≥ 15 ; ''condition,label'' ≥ 16
|-  style="vertical-align:top; border-bottom:1px solid #999;"
|integer multiply || colspan="5" | 70~160 (depending on operand ''data'' as well as size) ''including'' any EA
|-  style="vertical-align:top; border-bottom:1px solid #999;"
|integer divide || colspan="5" | 80~190 (depending on operand ''data'' as well as size) ''including'' any EA
|}
* EA = time to compute effective address, ranging from 5 to 12 cycles.
* Timings are best case, depending on prefetch status, instruction alignment, and other factors.

As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple [[Intel 8080|8080]] and [[Intel 8085|8085]], and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold:
* Loosely coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures).
* No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicated ''segment'' + ''offset'' adder).
* The address and data buses were [[multiplexing|multiplex]]ed, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors.{{Dubious|1=Multiplexed bus|reason=The multiplexed bus is unlikely to slow things by "33~50%." The address was only delayed by the 18 nanosecond max propagation delay of the 74LS373 transparent latch.|date=May 2023}}

However, memory access performance was drastically enhanced with Intel's next generation of 8086 family CPUs. The [[Intel 80186|80186]] and [[Intel 80286|80286]] both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses.

===Floating point===
The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-based [[floating-point]] performance. The [[Intel 8087]] was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like [[Cyrix]] (8087-compatible) and [[Weitek]] (''not'' 8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087.

==Chip versions==
The clock frequency was originally limited to 5&nbsp;MHz,<ref group="note" >(IBM PC used 4.77&nbsp;MHz, 4/3 the standard NTSC [[color burst]] frequency)</ref> but the last versions in [[HMOS]] were specified for 10&nbsp;MHz. HMOS-III and [[CMOS]] versions were manufactured for a long time (at least a while into the 1990s) for [[embedded system]]s, although its successor, the [[Intel 80186|80186]]/[[Intel 80188|80188]] (which includes some on-chip peripherals), has been more popular for embedded use.

The 80C86, the CMOS version of the 8086, was used in many portable computers and embedded systems, including the [[GridPad]], [[Toshiba T1200]], [[HP 110]], and finally the 1998–1999 [[Lunar Prospector]].

For the packaging, the Intel 8086 was available both in ceramic and plastic DIP packages.

<gallery mode="packed" heights="150px">
File:Intel D8086 CS.jpg|A ceramic D8086 variant
File:Intel P8086.jpg|A plastic P8086 variant
</gallery>

===List of Intel 8086===
{| class="wikitable"
|-
! Model number
! Frequency
! Technology
! Temperature range
! Package
! Date of release
! Price (USD)<ref group=list2>In quantity of 100.</ref>
|-
| 8086
| 5&nbsp;MHz<ref name=Intel79>{{cite book |publisher=Intel Corporation |title=The 8086 Family User's Manual |date=October 1979 |page=B-1 |oclc=65699372}}</ref>
| HMOS
| 0&nbsp;°C to 70&nbsp;°C<ref name="Intel Preview Special Issue 1980, page 29">{{cite journal |author=Intel Corporation |title=8086 Available for industrial environment |journal=Intel Preview |issue=Special Issue: 16-Bit Solutions |date=May–June 1980 |page=29 |oclc=803251993}}</ref>
|
| June 8, 1978<ref>{{Cite web|url=https://www.intel.com/pressroom/kits/quickrefyr.htm|title=Intel® Microprocessor Quick Reference Guide - Year|website=www.intel.com}}</ref>
| $86.65<ref>{{cite journal |author=Intel Corporation |title=The 8086 Family: Concepts and realities |journal=Intel Preview |issue=Special Issue: 16-Bit Solutions |date=May–June 1980 |page=19 |issn=1041-8547 |oclc=10331599}}</ref>
|-
| 8086-1
| 10&nbsp;MHz
| HMOS II
| Commercial
|
|
|
|-
| 8086-2
| 8&nbsp;MHz<ref name=Intel79/>
| HMOS II
| Commercial
|
| January/February 1980<ref name=IntelPrevJan80p22>{{cite journal |author=Intel Corporation |title=New Products: Faster 8086 provides 60% more performance |journal=Intel Preview |date=January–February 1980 |page=22}}</ref>
| $200<ref name=IntelPrevJan80p22/><ref>{{cite journal |author=Intel Corporation |title=New 8086 family products boost processor performance by 50 percent |journal=Intel Preview |issue=Special Issue: 16-Bit Solutions |date=May–June 1980 |page=17}}</ref>
|-
| 8086-4
| 4&nbsp;MHz<ref name=Intel79/>
| HMOS
| Commercial
| 
| 
| $72.50<ref group=list2>Price reduced by 21% from USD $99.00, no information in quantity value listed.</ref><ref>{{cite journal |author=Intel Corporation |title=Microcomputer Components: New price reductions and production improvements make the popular 8086 microprocessor even more attractive |journal=Intel Preview |date=May–June 1979 |page=11}}</ref>
|-
| I8086
| 5&nbsp;MHz
| HMOS
| Industrial −40&nbsp;°C to +85&nbsp;°C<ref name="Intel Preview Special Issue 1980, page 29"/>
| 
| May/June 1980<ref name="Intel Preview Special Issue 1980, page 29"/>
| $173.25<ref name="Intel Preview Special Issue 1980, page 29"/>
|-
| M8086
| 5&nbsp;MHz
| HMOS
| Military grade −55&nbsp;°C to +125&nbsp;°C<ref>{{cite book |author=Intel Corporation |title=Intel iAPX86, 88 User's manual |date=August 1981 |page=B-25 |publisher=Intel Corporation |isbn=0835930165 |oclc=8459750}}</ref>
| 
| 
| 
|-
| 80C86<ref>Intel Corporation, "NewsBit: Intel Licenses Oki on CMOS Version of Several Products", Solutions, July/August 1984, Page 1.</ref>
| 
| CMOS
| 
| 44 Pin [[Chip_carrier#Leadless|PLCC]]<ref group=list2>Sampling Q4 1985</ref><ref>Ashborn, Jim; "Advanced Packaging: A Little Goes A Long Way", Intel Corporation, Solutions, January/February 1986, Page 2</ref>
| 
| 
|}

{{reflist|group=list2}}

===Derivatives and clones===
Compatible—and, in many cases, enhanced—versions were manufactured by [[Fujitsu]],<ref>Intel Corporation, "NewsBits: Second Source News", Solutions, January/February 1985, Page 1</ref> [[Harris Corporation|Harris]]/[[Intersil]], [[Oki Electric Industry|OKI]], [[Siemens]], [[Texas Instruments]], [[NEC]], [[Mitsubishi Electric|Mitsubishi]], and [[AMD]]. For example, the [[NEC V20]] and [[NEC V30]] pair were hardware-compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems.

The electronics industry of the [[Soviet Union]] was able to replicate the 8086 through {{citation needed-span|both [[industrial espionage]] and reverse engineering|date=October 2013}}. The resulting chip, [[K1810VM86]], was binary and pin-compatible with the 8086.

i8086 and i8088 were respectively the cores of the Soviet-made PC-compatible [[EC1831]] and [[EC1832]] desktops. (EC1831 is the EC identification of IZOT 1036C and EC1832 is the EC identification of IZOT 1037C, developed and manufactured in Bulgaria. EC stands for Единая Система.) However, the EC1831 computer (IZOT 1036C) had significant hardware differences from the IBM PC prototype. The EC1831 was the first PC-compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the EC1831 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989).

<gallery mode="packed" heights="150px">
Image:KL USSR KP1810BM86.jpg|Soviet clone [[K1810VM86]]
Image:Oki 80c86a.jpg|[[Oki Electric Industry|OKI]] M80C86A [[QFP|QFP-56]]
Image:UPD8086D-2 NEC 1984year 19week JAPAN.JPG|NEC μPD8086D-2 (8&nbsp;MHz) from the year 1984, week 19 JAPAN (clone of Intel D8086-2)
Image:KL AMD D8086.jpg|The [[AMD]] D8086
</gallery>

==Support chips==
* [[Intel 8237]]: direct memory access (DMA) controller
* [[Intel 8251]]: universal synchronous/asynchronous receiver/transmitter at 19.2&nbsp;kbit/s
* [[Intel 8253]]: programmable interval timer, 3x 16-bit max 10&nbsp;MHz
* [[Intel 8255]]: programmable peripheral interface, 3x 8-bit I/O pins used for printer connection etc.
* [[Intel 8259]]: programmable interrupt controller
* [[Intel 8279]]: keyboard/display controller, scans a keyboard matrix and display matrix like [[Seven-segment display|7-seg]]
* [[Intel 8282]]/[[Intel 8283|8283]]: 8-bit latch
* [[Intel 8284]]: clock generator
* [[Intel 8286]]/[[Intel 8287|8287]]: bidirectional 8-bit driver. In 1980 both Intel I8286/I8287 (industrial grade) version were available for US$16.25 in quantities of 100.<ref name="Intel Preview Special Issue 1980, page 29"/>
* [[Intel 8288]]: bus controller
* [[Intel 8289]]: bus arbiter
* [[Floppy-disk controller|NEC μPD765 or Intel 8272A]]: floppy controller<!--also NE72065--><ref>{{cite web|title=The floppy controller evolution &#124; OS/2 Museum |date=2011-05-26 |access-date=2016-05-12 |url=https://www.os2museum.com/wp/the-floppy-controller-evolution/ |quote=In the original IBM PC (1981) and PC/XT (1983), the FDC was physically located on a separate diskette adapter card. The FDC itself was a NEC μPD765A or a compatible part, such as the Intel 8272A.}}</ref>

==Microcomputers using the 8086==
* The Intel [[Multibus]]-compatible [[single-board computer]] ISBC 86/12 was announced in 1978.<ref>{{cite magazine | title = Intel Adds 16-Bit Single Board | magazine = [[Computerworld]] | date = December 11, 1978 | pages = 86 | volume = XII | issue = 50 | issn = 0010-4841 | url = https://books.google.com/books?id=07X0ovA_MmEC&pg=PA86| author=<!-- unspecified --> }}</ref>
* The [[Xerox NoteTaker]] was one of the earliest [[portable computer]] designs in 1978 and used three 8086 chips (as CPU, graphics processor, and I/O processor), but never entered commercial production.
* [[Seattle Computer Products]] shipped [[S-100 bus]] based 8086 systems (SCP200B) as early as November 1979.
* The Norwegian [[Mycron]] 2000, introduced in 1980.
* One of the most influential microcomputers of all, the [[IBM PC]], used the [[Intel 8088]], a version of the 8086 with an 8-bit [[Bus (computing)|data bus]] (as mentioned above).
* The first [[Compaq Deskpro]] used an 8086 running at 7.16&nbsp;MHz, but was compatible with add-in cards designed for the 4.77&nbsp;MHz [[IBM PC XT]] and could switch the CPU down to the lower speed (which also switched in a memory bus buffer to simulate the 8088's slower access) to avoid software timing issues.
* An 8&nbsp;MHz 8086-2 was used in the [[Olivetti M24|AT&T 6300 PC]] (built by [[Olivetti]], and known globally under several brands and model numbers), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the [[IBM PC AT]], but different in the design details, and physically incompatible), and all system peripherals including the onboard video system also enjoy 16-bit data transfers. The later Olivetti M24SP featured an 8086-2 running at the full maximum 10&nbsp;MHz.
* The [[IBM Personal System/2|IBM PS/2]] models [[IBM PS/2 Model 25|25]] and [[IBM PS/2 Model 30|30]] were built with an 8&nbsp;MHz 8086.
* The [[Amstrad PC1512]], [[Amstrad PC1640|PC1640]], PC2086, PC3086 and PC5086 all used 8086 CPUs at 8&nbsp;MHz.
* The [[NEC PC-9801]].
* The [[Tandy 1000]] SL-series and RL machines used 9.47&nbsp;MHz 8086 CPUs.
* The [[IBM Displaywriter]] word processing machine<ref name = "InfoWorld Aug 1982" >{{cite magazine  | last = Zachmann | first = Mark  | title = Flaws in IBM Personal Computer frustrate critic  | magazine = [[InfoWorld]] | volume = 4 | issue = 33  | pages =57–58  | date = August 23, 1982  | url = https://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57| issn = 0199-6649  | quote = the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086.}}</ref> and the Wang Professional Computer, manufactured by [[Wang Laboratories]], also used the 8086.
* [[NASA]] used original 8086 CPUs on equipment for ground-based maintenance of the [[Space Shuttle Discovery]] until the end of the space shuttle program in 2011. This decision was made to prevent [[software regression]] that might result from upgrading or from switching to imperfect clones.<ref>{{cite news |url=https://www.nytimes.com/2002/05/12/technology/ebusiness/12NASA.html?pagewanted=2 |title=For Old Parts, NASA Boldly Goes ... on eBay |date=May 12, 2002 |newspaper=New York Times |url-access=limited}}</ref>
* KAMAN Process and Area Radiation Monitors<ref>Kaman Tech. Manual</ref>
* The [[Tektronix]] 4170 ran [[CP/M-86]] and used an 8086 {{citation|url=https://bitsavers.org/pdf/tektronix/4170/061-2880-00_4170_Local_Graphics_Processing_Unit_Instruction_Manual_Apr1984.pdf|title=4170 Local Graphics Processing Unit Instruction Manual}}

==See also==
* [[Transistor count]]
* [[iAPX]], for the iAPX name

==Notes==
{{Reflist|group=note|2}}

==References==
{{Reflist|refs=
<ref name="Scanlon_1988">{{cite book |title=8086/8088/80286 assembly language |author-last=Scanlon |author-first=Leo J. |date=1988 |publisher=Brady Books |isbn=978-0-13-246919-7 |page=[https://archive.org/details/8086808880286ass0000scan/page/12 12] |url=https://archive.org/details/8086808880286ass0000scan/page/12 |url-access=registration |quote=[…] The [[8086]] is software-compatible with the [[8080]] at the assembly-language level. […]}}</ref>
}}

==External links==
{{Commons category}}
* [http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086 Intel datasheets]
* [https://www.cpu-world.com/CPUs/8086/ List of 8086 CPUs and their clones at CPUworld.com]
* [https://www.cpu-world.com/info/Pinouts/8086.html 8086 Pinouts]
* [http://www.8085projects.info/post/Maximum-Mode-Interface.aspx Maximum Mode Interface] [https://web.archive.org/web/20110721183206/http://www.8085projects.info/post/Maximum-Mode-Interface.aspx Archived] from the original on July 21, 2011. Retrieved July 10, 2022.
* [http://matthieu.benoit.free.fr/cross/data_sheets/Intel_8086_users_manual.htm The 8086 User's manual October 1979 INTEL Corporation] ([[PDF]] document)
* [https://web.archive.org/web/20140821053853/http://www.shubhsblog.com/category/8086-programs/ 8086 program codes using emu8086 (Version 4.08) Emulator]
* {{cite web |first=Andrew |last=Jenner |title=8086 microcode disassembled |date=September 2020 |work=Reenigne blog |url=https://www.reenigne.org/blog/8086-microcode-disassembled/}}
* {{cite web |first=Ken |last=Shirriff |title=A look at the die of the 8086 processor |date=June 2020 |url=https://www.righto.com/2020/06/a-look-at-die-of-8086-processor.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Die shrink: How Intel scaled down the 8086 processor |date=June 2020 |url=https://www.righto.com/2020/06/die-shrink-how-intel-scaled-down-8086.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The Intel 8086 processor's registers: from chip to transistors  |date=July 2020 |url=https://www.righto.com/2020/07/the-intel-8086-processors-registers.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the adder inside the Intel 8086 |date=August 2020 |url=https://www.righto.com/2020/08/reverse-engineering-adder-inside-intel.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the 8086's Arithmetic/Logic Unit from die photos |date=August 2020 |url=https://www.righto.com/2020/08/reverse-engineering-8086s.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The unusual bootstrap drivers inside the 8086 microprocessor chip |date=November 2022 |url=https://www.righto.com/2022/11/the-unusual-bootstrap-drivers-inside.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=A bug fix in the 8086 microprocessor, revealed in the die's silicon |date=November 2022 |url=https://www.righto.com/2022/11/a-bug-fix-in-8086-microprocessor.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=How the 8086 processor's microcode engine works |date=December 2022 |url=https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Inside the 8086 processor's instruction prefetch circuitry |date=January 2023 |url=https://www.righto.com/2023/01/inside-8086-processors-instruction.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The 8086 processor's microcode pipeline from die analysis |date=January 2023 |url=https://www.righto.com/2023/01/the-8086-processors-microcode-pipeline.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Counting the transistors in the 8086 processor: it's harder than you might think |date=January 2023 |url=https://www.righto.com/2023/01/counting-transistors-in-8086-processor.html}}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the conditional jump circuitry in the 8086 processor |date=January 2023 |url=https://www.righto.com/2023/01/reverse-engineering-conditional-jump.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the Intel 8086 processor's HALT circuits |date=January 2023 |url=https://www.righto.com/2023/01/reverse-engineering-intel-8086.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Understanding the x86's Decimal Adjust after Addition (DAA) instruction |date=January 2023 |url=https://www.righto.com/2023/01/understanding-x86s-decimal-adjust-after.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Silicon reverse-engineering: the Intel 8086 processor's flag circuitry |date=February 2023 |url=https://www.righto.com/2023/02/silicon-reverse-engineering-intel-8086.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the interrupt circuitry in the Intel 8086 processor |date=February 2023 |url=https://www.righto.com/2023/02/8086-interrupt.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the ModR/M addressing microcode in the Intel 8086 processor |date=February 2023 |url=https://www.righto.com/2023/02/8086-modrm-addressing.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=How the 8086 processor determines the length of an instruction |date=March 2023 |url=https://www.righto.com/2023/02/how-8086-processor-determines-length-of.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the multiplication algorithm in the Intel 8086 processor |date=March 2023 |url=http://www.righto.com/2023/03/8086-multiplication-microcode.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the register codes for the 8086 processor's microcode |date=March 2023 |url=http://www.righto.com/2023/03/8086-register-codes.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The microcode and hardware in the 8086 processor that perform string operations |date=April 2023 |url=http://www.righto.com/2023/04/8086-microcode-string-operations.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the division microcode in the Intel 8086 processor |date=April 2023 |url=http://www.righto.com/2023/04/reverse-engineering-8086-divide-microcode.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The Group Decode ROM: The 8086 processor's first step of instruction decoding |date=May 2023 |url=http://www.righto.com/2023/05/8086-processor-group-decode-rom.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Reverse-engineering the 8086 processor's address and data pin circuits |date=July 2023 |url=http://www.righto.com/2023/07/8086-pins.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Undocumented 8086 instructions, explained by the microcode |date=July 2023 |url=http://www.righto.com/2023/07/undocumented-8086-instructions.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Tracing the roots of the 8086 instruction set to the Datapoint 2200 minicomputer |date=August 2023 |url=http://www.righto.com/2023/08/datapoint-to-8086.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=A close look at the 8086 processor's bus hold circuitry |date=August 2023 |url=http://www.righto.com/2023/08/intel-8086-bus-hold.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=How flip-flops are implemented in the Intel 8086 processor |date=October 2023 |url=http://www.righto.com/2023/09/8086-flip-flops.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=The Intel 8088 processor's instruction prefetch circuitry: a look inside |date=March 2024 |url=http://www.righto.com/2024/03/8088-prefetch-circuitry.html }}
** {{cite web |author-mask=1 |first=Ken |last=Shirriff |title=Talking to memory: Inside the Intel 8088 processor's bus interface state machine |date=April 2024 |url=http://www.righto.com/2024/04/intel-8088-bus-state-machine.html }}

{{Intel processors|discontinued}}
{{Authority control}}

[[Category:Intel x86 microprocessors|80086]]<!--Note: NOT a typo for 8086, this is done for numerical ordering of categories-->
[[Category:16-bit microprocessors]]
[[Category:Computer-related introductions in 1978]]
[[Category:X86 microarchitectures]]