Editing Intel MCS-51

{{Short description|Single chip microcontroller series by Intel}}
{{Infobox CPU
| name = Intel 8051
| image = KL Intel P8051.jpg
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| caption = Intel P8051 [[microcontroller]]
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| predecessor = [[Intel MCS-48]]
| successor = Intel MCS-151 <!-- Not linking because it is a redirect to this article -->
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The '''Intel MCS-51''' (commonly termed '''8051''') is a single-chip [[microcontroller]] (MCU) series developed by [[Intel]] in 1980 for use in [[embedded system]]s. The architect of the Intel MCS-51 instruction set was [[John H.&nbsp;Wharton]].<ref>{{cite web |author=John Wharton |author-link=John H. Wharton |url=https://drive.google.com/uc?export=download&id=0B9rh9tVI0J5mZTFmZjRjZTItNDQ0Yy00MDFlLTgzZTgtM2I3MzVkMTliNTFl |title=An Introduction to the Intel MCS-51 Single-Chip Microcomputer Family |id=Application Note AP-69 |date=May 1980 |publisher=Intel Corporation}}</ref><ref name="Intel8051OralHistory">{{Citation
| url = http://archive.computerhistory.org/resources/text/Oral_History/Intel_8051/102658339.05.01.acc.pdf
| title = Intel 8051 Microprocessor Oral History Panel
| access-date = November 17, 2018
| publisher = [[Computer History Museum]]
| date = September 16, 2008
| archive-url = https://web.archive.org/web/20120225062256/http://archive.computerhistory.org/resources/text/Oral_History/Intel_8051/102658339.05.01.acc.pdf
| archive-date = February 25, 2012
| url-status = dead
}}.</ref> Intel's original versions were popular in the 1980s and early 1990s, and enhanced [[binary compatible]] derivatives remain popular today. It is a [[complex instruction set computer]] with separate memory spaces for program instructions and data.

Intel's original MCS-51 family was developed using N-type metal–oxide–semiconductor ([[NMOS logic|NMOS]]) technology, like its predecessor [[Intel MCS-48]], but later versions, identified by a letter C in their name (e.g., 80C51) use complementary metal–oxide–semiconductor ([[CMOS]]) technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices.

The family was continued in 1996 with the enhanced [[8-bit]] MCS-151 and the 8/[[16-bit|16]]/[[32-bit]] MCS-251 family of binary compatible microcontrollers.<ref name="1+2-51"/> While Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family, enhanced [[binary compatible]] derivatives made by numerous vendors remain popular today. Some derivatives integrate a [[digital signal processor]] (DSP) or a [[floating-point unit]] (coprocessor, FPU). Beyond these physical devices, several companies also offer MCS-51 derivatives as [[IP core]]s for use in [[field-programmable gate array]] (FPGA) or [[application-specific integrated circuit]] (ASIC) designs.

== Important features and applications ==
[[File:Intel 8051 arch.svg|right|thumb|i8051 microarchitecture]]
The 8051 architecture provides many functions ([[central processing unit]] (CPU), [[random-access memory]] (RAM), [[read-only memory]] (ROM), [[input/output]] (I/O) ports, serial port, [[interrupt]] control, [[timer]]s) in one [[Integrated circuit packaging|package]]:
* 8-[[bit]] [[arithmetic logic unit]] (ALU) and [[accumulator (computing)|accumulator]], 8-bit [[processor register|registers]] (one [[16-bit]] register with special [[instruction set#Data handling and memory operations|move instructions]]), 8-bit [[data bus]] and 2&nbsp;× 16-bit [[address bus]]es, [[program counter]], [[data pointer]], and related 8/11/16-bit operations; hence it is mainly an 8-bit [[microcontroller]]
* [[Boolean data type|Boolean]] processor with 17 instructions, 1-bit accumulator, 32 registers (4&nbsp;× 8-bit, bit-addressable) and up to 144 special 1 bit-addressable RAM variables (18&nbsp;× 8-bit)<ref>{{cite web |url=http://www2.elo.utfsm.cl/~lsb/elo311/aplicaciones/intel/booleanproc.pdf |author=John Wharton |title=Using the Intel MCS-51 Boolean Processing Capabilities |id=Application Note AP-70 |date=May 1980 |publisher=Intel Corporation |archive-url=https://web.archive.org/web/20160303234549/http://www2.elo.utfsm.cl/~lsb/elo311/aplicaciones/intel/booleanproc.pdf |archive-date=2016-03-03 |url-status=dead}}</ref>
* [[Binary multiplier|Multiply]], divide and [[relational operator|compare]] instructions
* Four fast [[bank switching|switchable register banks]] with 8 registers each (memory-mapped)
* Fast interrupt with optional register bank switching
* [[Interrupt]]s and [[thread (computing)|threads]] with selectable priority<ref>{{Cite web |url=http://www.8052.com/tutint.phtml |title=8051 Tutorial: Interrupts |access-date=2012-12-21 |archive-url=https://web.archive.org/web/20121228002749/http://www.8052.com/tutint.phtml |archive-date=2012-12-28 |url-status=dead }}</ref>
* 128 or 256 [[byte]]s of on-chip RAM (IRAM)
* Dual 16-bit [[address bus]]; it can access 2&nbsp;× 2<sup>16</sup> memory locations: 64&nbsp;[[kilobyte|KB]] (65,536 locations) each of ROM (PMEM) and external RAM (XRAM), using two memory buses in a [[Harvard architecture]].
* On-chip ROM (not included on 803x variants)
* Four (three full) 8-[[bit]] bidirectional [[input/output]] ports, bit-addressable
* UART ([[serial port]])
* Two 16-bit counters/[[timer]]s
* [[Power management|Power-saving]] mode (on some derivatives)

One feature of the 8051 core is the inclusion of a Boolean processing engine, which allows [[bit]]-level [[Boolean logic]] operations to be carried out directly and efficiently on select internal [[Processor register|registers]], ports and select [[RAM]] locations. Another feature is the inclusion of four [[bank switching|bank-selectable]] working register sets, which greatly reduce the time required to perform the [[context switch]]es to enter and leave [[interrupt service routine]]s. With one instruction, the 8051 can switch register banks, avoiding the time-consuming task of transferring the critical registers to RAM.

=== Derivative features ===
{{As of|2013}}, new derivatives are still being developed by many major chipmakers, and major compiler suppliers such as [[IAR Systems]], [[Keil (company)|Keil]] and [[TASKING]]<ref>{{Cite web |url=https://www.tasking.com/products/8051 |title=8051 Software Development Toolset - Overview |website=TASKING |access-date=2025-02-13}}</ref> continuously release updates.

MCS-51-based microcontrollers typically include one or two [[UART]]s, two or three timers, 128 or 256&nbsp;bytes of internal data [[RAM]] (16&nbsp;bytes of which are bit-addressable), up to 128&nbsp;bytes of [[I/O]], 512&nbsp;bytes to 64&nbsp;KB of internal program memory, and sometimes a quantity of extended data RAM (ERAM) located in the external data space. External RAM and ROM share the data and address buses. The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12&nbsp;MHz [[clock frequency]], the 8051 could thus execute 1&nbsp;million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle (denoted "1T") and have clock frequencies of up to 100&nbsp;MHz, thus being capable of an even greater number of instructions per second. All [[Silicon Labs]], some [[Dallas Semiconductor|Dallas]] (now part of [[Maxim Integrated]]) and a few [[Atmel]] (now part of [[Microchip Technology|Microchip]]) devices have [[Single-cycle processor|single-cycle cores]].<ref name=":0">{{Cite web |title=8-bit Microcontrollers – 8-bit MCUs – EFM8 |website=Silicon Labs |url=https://www.silabs.com/mcu/8-bit |access-date=2021-06-21 |language=en}}</ref><ref>{{Cite web |title=Site Search |website=Maxim Integrated |url=https://www.maximintegrated.com/en/site-search.html#q=DS80&sort=relevancy&f:@common_product_hierarchy=%5BMCU%20-%20Microcontroller%5D |access-date=2021-06-21 |archive-date=2021-06-24 |archive-url=https://web.archive.org/web/20210624210156/https://www.maximintegrated.com/en/site-search.html#q=DS80&sort=relevancy&f:@common_product_hierarchy=%5BMCU%20-%20Microcontroller%5D |url-status=dead }}</ref><ref name=":1">{{Cite web |title=8051 MCUs |website=Microchip Technology |url=https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/8-bit-mcus/8051-mcus |access-date=2021-06-21}}</ref>

8051 variants may include built-in reset timers with [[Brownout (electricity)#Digital systems|brown-out]] detection, on-chip oscillators, self-programmable [[flash ROM]] program memory, built-in external RAM, extra internal program storage, [[bootloader]] code in ROM, [[EEPROM]] non-volatile data storage, [[I2C|I<sup>2</sup>C]], [[Serial Peripheral Interface|SPI]], and [[USB]] host interfaces, [[controller–area network|CAN]] or [[Local Interconnect Network|LIN]] bus, [[Zigbee]] or [[Bluetooth]] radio modules, [[pulse-width modulation|PWM]] generators, analog [[comparator]]s, [[analog-to-digital]] and [[digital-to-analog converter]]s, [[real-time clock|RTCs]], extra counters and timers, in-circuit [[debugging]] facilities, more interrupt sources, extra power-saving modes, more or fewer parallel ports etc. Intel manufactured a mask-programmed version, 8052AH-BASIC, with a [[BASIC]] interpreter in ROM, capable of running user programs loaded into RAM.

MCS-51-based microcontrollers have been adapted to extreme environments. Examples for high-temperature variants are the Tekmos TK8H51 family for −40{{nbsp}}°C to +250{{nbsp}}°C<ref>{{cite web
 | title=TK80H51 250&nbsp;°C Microcontroller
 | url=http://www.tekmos.com/products/80c51-microcontrollers/tk80h51-250-c-microcontroller
 | publisher=Tekmos Inc.
 | access-date=23 August 2017
 | archive-url=https://web.archive.org/web/20170820093849/http://www.tekmos.com/products/80c51-microcontrollers/tk80h51-250-c-microcontroller
 | archive-date=20 August 2017
 | url-status=dead
 }}</ref> or the [[Honeywell]] HT83C51 for −55{{nbsp}}°C to +225{{nbsp}}°C (with operation for up to 1 year at +300{{nbsp}}°C).<ref>
{{cite web
 | title=HIGH TEMPERATURE 83C51 MICROCONTROLLER
 | url=http://www.keil.com/dd/docs/datashts/honeywell/ht83c51.pdf
 | publisher=Honeywell
 | access-date=23 August 2017
}}</ref> [[Radiation hardening|Radiation-hardenend]] MCS-51 microcontrollers for use in spacecraft are available; e.g., from [[Cobham plc|Cobham]] (formerly [[Aeroflex]]) as the UT69RH051<ref>{{cite web
 | title=Microcontrollers and Microprocessors
 | url=http://ams.aeroflex.com/pagesproduct/prods-hirel-uprocessors.cfm
 | publisher=Cobham Semiconductor Solutions
 | access-date=23 August 2017
 | archive-date=23 August 2017
 | archive-url=https://web.archive.org/web/20170823020620/http://ams.aeroflex.com/pagesproduct/prods-hirel-uprocessors.cfm
 | url-status=dead
 }}</ref> or from NIIET as the 1830VE32 ({{langx|ru|1830ВЕ32}}).<ref name=niiet/>

In some engineering schools, the 8051 microcontroller is used in introductory microcontroller courses.<ref>{{Cite web |url=http://play.tojsiab.com/WFhtU3d2djNXckUz |title=Download link Youtube: ELEC2700 – 8051 Ultrasonic Radar |access-date=2017-08-22 |archive-url=https://web.archive.org/web/20170822215715/http://play.tojsiab.com/WFhtU3d2djNXckUz |archive-date=2017-08-22 |url-status=dead }}</ref><ref>Archived at [https://ghostarchive.org/varchive/youtube/20211205/H9sDn89EvD8 Ghostarchive]{{cbignore}} and the [https://web.archive.org/web/20200608025501/https://www.youtube.com/watch?v=H9sDn89EvD8&gl=US&hl=en Wayback Machine]{{cbignore}}: {{cite web| url = https://www.youtube.com/watch?v=H9sDn89EvD8| title = ELEC2700 Assignment 1 2014: 1D Pong | website=[[YouTube]]| date = 10 April 2014 }}{{cbignore}}</ref><ref>{{Cite web |url=https://www.zookal.com/ |title=ELEC2700 – Computer Engineering 2 (University of Newcastle Textbooks) |website=Zookal |access-date=2017-08-22 |archive-date=2017-07-27 |archive-url=https://web.archive.org/web/20170727171633/https://www.zookal.com/ |url-status=dead }}</ref><ref>{{cite web |url=http://s3.amazonaws.com/f01.justanswer.com/88willy/2012-06-29_065532_assignment_03.pdf |access-date=30 April 2023 |date=29 June 2012 |website=JustAnswer |title=ELEC2700 Assignment 3: Ultrasonic Radar}}</ref>

== Family naming conventions ==
{{See also|List of Intel processors#Intel 8051}}
Intel's first MCS-51 microcontroller was the 8051, with 4&nbsp;KB ROM and 128&nbsp;byte RAM. Variants starting with 87 have a user-programmable EPROM, sometimes UV-erasable. Variants with a C as the third character are some kind of [[CMOS]]. 8031 and 8032 are ROM-less versions, with 128 and 256 bytes of RAM. The last digit can indicate memory size, e.g. 8052 with 8&nbsp;KB ROM, 87C54 16&nbsp;KB EPROM, and 87C58 with 32&nbsp;KB EPROM, all with 256-byte RAM.

== Memory architecture ==
The MCS-51 has four distinct types of memory: internal RAM, special function registers, program memory, and external data memory. To access these efficiently, some compilers<ref name="keil">{{cite book |title=Keil C51 Users' Manual |date=2021 |publisher=Keil, a division of ARM Inc. |url=https://www.keil.com/c51/man/c51.htm |access-date=17 May 2021}}</ref> utilize as many as 7 types of memory definitions: internal RAM, single-bit access to internal RAM, special function registers, single-bit access to selected (divisible by 8) special function registers, program RAM, external RAM accessed using a register indirect access, using one of the standard 8-bit registers, and register indirect external RAM access utilizing the 16-bit indirect access register.

The 8051's instruction set is designed as a [[Harvard architecture]] with segregated memory (data and instructions); it can only execute code fetched from program memory and has no instructions to write to program memory. However, the bus leaving the IC has a single address and data path, and strongly resembles a [[von&nbsp;Neumann architecture]] bus.

Most 8051 systems respect the instruction set and require customized features to download new executable programs, e.g. in flash memory.

=== Internal RAM ===
[[Internal RAM]] (IRAM) has an 8-bit address space, using addresses 0 through 0xFF. IRAM from 0x00 to 0x7F contains 128 directly addressable 1-byte registers, which can be accessed using an 8-bit absolute address that is part of the instruction. Alternatively, IRAM can be accessed indirectly: the address is loaded into R0 or R1, and the memory is accessed using the <code>@R0</code> or <code>@R1</code> syntax, or as stack memory through the stack pointer SP, with the <code>PUSH</code>/<code>POP</code> and <code>*CALL</code>/<code>RET</code> operations.

The original 8051 has only 128 bytes of IRAM. The 8052 added IRAM from 0x80 to 0xFF, which can ''only'' be accessed indirectly (e.g. for use as stack space). Most 8051 clones also have a full 256 bytes of IRAM.

Direct accesses to the IRAM addresses 0x80–0xFF are, instead, mapped onto the special function registers (SFR), where the accumulators A, B, carry bit C, and other special registers for control, status, etc., are located.

=== Special function registers ===
Special function registers (SFR) are located in the same address space as IRAM, at addresses 0x80 to 0xFF, and are accessed directly using the same instructions as for the lower half of IRAM. They cannot be accessed indirectly via <code>@R0</code> or <code>@R1</code> or by the stack pointer SP; indirect access to those addresses will access the second half of IRAM instead.

The special function registers (SFR) include the accumulators A (or ACC, at E0) and B (at F0) and program status word (or PSW, at D0), themselves, as well as the 16-bit data pointer DPTR (at 82, as DPL and 83 as DPH). In addition to these, a small core of other special function registers{{snd}} including the interrupt enable IE at A8 and interrupt priority IP at B8; the I/O ports P0 (80), P1 (90), P2 (A0), P3 (B0); the serial I/O control SCON (98) and buffer SBUF (99); the CPU/power control register PCON (87); and the registers for timers 0 and 1 control (TCON at 88) and operation mode (TMOD at 89), the 16-bit timer 0 (TL0 at 8A, TH0 at 8C) and timer 1 (TL1 at 8B, TH1 at 8D){{snd}} are present on all versions of the 8051. Other addresses are version-dependent; in particular, the registers of timer&nbsp;2 for the 8052, the control register T2CON (at C8), the 16-bit capture/latch (RCAP2L at CA, RCAP2H at CB) and timer&nbsp;2 (TL2 at CC and TH2 at CD) are not included with the 8051.

=== Register windows ===
The 32 bytes in IRAM from 0x00 to 0x1F contain space for four 8-byte [[register window]]s, which the eight registers R0–R7 map to. The currently active window is determined by a two-bit address contained in the program status word.

=== Bit registers ===
The 16 bytes (128 bits) at IRAM locations 0x20–0x2F contain space for 128 1-bit registers, which are separately addressable as bit registers 00–7F.

The remaining bit registers, addressed as 80–FF, are mapped onto the 16 special function registers 80, 88, 90, 98,&nbsp;..., F0 and F8 (those whose addresses are multiples of 8), and therefore include the bits comprising the accumulators A, B and program status word PSW. The register window address, being bits 3 and 4 of the PSW, is itself addressable as bit registers D3 and D4 respectively; while the carry bit C (or CY), at bit 7 of the PSW, is addressable as bit register D7.

=== Program memory ===
Program memory (PMEM, though less common in usage than IRAM and XRAM) is up to 64&nbsp;KB of read-only memory, starting at address 0 in a separate address space. It may be on- or off-chip, depending on the particular model of chip being used. Program memory is read-only, though some variants of the 8051 use on-chip flash memory and provide a method of re-programming the memory in-system or in-application.

In addition to code, it is possible to store read-only data such as [[lookup table]]s in program memory, retrieved by the {{code|lang=asm|MOVC A,@A+DPTR}} or {{code|lang=asm|MOVC A,@A+PC}} instructions. The address is computed as the sum of the 8-bit accumulator and a 16-bit register (PC or DPTR).

Special jump and call instructions ({{code|lang=asm|AJMP}} and {{code|lang=asm|ACALL}}) slightly reduce the size of code that accesses local (within the same 2&nbsp;KB) program memory.<ref>ACALL is a 2-byte subroutine calling instruction, it can access locations within the same 2{{nbsp}}KB segment of memory. The absolute memory address is formed by the high 5 bits of the PC and the 11 bits defined by the instruction.</ref>

When code larger than 64&nbsp;KB is required, a common system makes the code bank-switched, with general-purpose I/O selecting the upper address bits. Some 8051 compilers<ref name="keil"/> make provisions to automatically access paged code. In these systems, the interrupt vectors and paging table are placed in the first 32&nbsp;KB of code and are always resident.

=== External data memory ===
External data memory (XRAM) is a third address space, also starting at address 0, and allowing 16 bits of address space. It can also be on- or off-chip; what makes it "external" is that it must be accessed using the {{code|lang=asm|MOVX}} (move external) instruction. Many variants of the 8051 include the standard 256&nbsp;bytes of IRAM plus a few kilobytes of XRAM on the chip.

The first 256 bytes of XRAM may be accessed using the {{code|lang=asm|MOVX A,@R0}}, {{code|lang=asm|MOVX A,@R1}}, {{code|lang=asm|MOVX @R0,A}}, and {{code|lang=asm|MOVX @R1,A}} instructions. The full 64&nbsp;KB may be accessed using {{code|lang=asm|MOVX A,@DPTR}} and {{code|lang=asm|MOVX @DPTR,A}}. The 16-bit address requires the programmer to load the 16-bit index register. For this reason, RAM accesses with 16-bit addresses are substantially slower.

Some CPUs<ref name="teridian">{{cite web |title=Silergy 71M6513 Data sheet |url=https://www.silergy.com/download/upload/pdffile/71M6513_DS_Rev4.pdf/2673 |website=Silergy electricity metering ICs |publisher=Silergy Corp. |access-date=17 May 2021}}</ref> permit the 8-bit indirect address to use any 8-bit general-purpose register.

To permit the use of this feature, some 8051-compatible microcontrollers with internal RAM larger than 256 bytes, or an inability to access external RAM,<ref name="teridian"/> access internal RAM as if it were external and have a special function register (e.g. PDATA) that permits them to set the upper address of the 256-byte page. This emulates the MCS8051 mode that can page the upper byte of a RAM address by setting the general-purpose I/O pins.

When RAM larger than 64&nbsp;KB is required, a common system makes the RAM bank-switched, with general-purpose I/O selecting the upper address bits. Some 8051 compilers<ref name="keil"/> make provisions to automatically access paged data.

== Registers ==
The only register on an 8051 that is not memory-mapped is the 16-bit program counter (PC).  This specifies the address of the next instruction to execute.  Relative branch instructions supply an 8-bit signed offset which is added to the PC.

Eight general-purpose registers R0–R7 may be accessed with instructions one byte shorter than others.  They are mapped to IRAM between 0x00 and 0x1F.  Only eight bytes of that range are used at any given time, determined by the two bank-select bits in the PSW.

The following is a partial list of the 8051's registers, which are memory-mapped into the special function register space:

; Stack pointer, SP (0x81):  This is an 8-bit register used by subroutine call and return instructions.  The stack grows upward; the SP is incremented before pushing and decremented after popping a value.
; Data pointer, DP (0x82–83):  This is a 16-bit register that is used for accessing PMEM and XRAM.
; Program status word, PSW (0xD0):  This contains important status flags, by bit number: {{ordered list
 | start=0
 | Parity, P.  Gives the parity ([[XOR]] of the bits) of the accumulator, A.
 | User defined, UD.  May be read and written by software; not otherwise affected by hardware.
 | [[Overflow flag]], OV.  Set when addition produces a signed overflow.
 | Register select 0, RS0.  The low-order bit of the register bank.  Set when banks at 0x08 or 0x18 are in use.
 | Register select 1, RS1.  The high-order bit of the register bank.  Set when banks at 0x10 or 0x18 are in use.
 | Flag 0, F0.  May be read and written by software; not otherwise affected by hardware.
 | [[Adjust flag|Auxiliary carry]], AC.  Set when addition produces a carry from bit 3 to bit 4.
 | [[Carry bit]], C. Often used as the general register for bit computations, or the "Boolean accumulator".
 }}
; Accumulator, A (0xE0):  This register is used by most instructions.
; B register (0xF0):  This is used as an extension to the accumulator for multiply and divide instructions.

256 single bits are directly addressable.  These are the 16 IRAM locations from 0x20–0x2F, and the 16 special function registers 0x80, 0x88, 0x90, ..., 0xF8.  Any bit of these bytes may be directly accessed by a variety of logical operations and conditional branches.

Note that the PSW does not contain the common [[Negative flag|negative (N)]], or [[Zero flag|zero (Z) flags]]. For the former, the most significant bit of the accumulator can be addressed directly, as it is a bit-addressable SFR. For the latter, there are explicit instructions to jump on whether or not the accumulator is zero. There is also a two-operand compare and jump operation.

The parity (P) bit is often used to implement serial modes that include parity. To support this, the standard MCS51 [[UART]]s could send 9 bits.

== Microarchitecture ==
The microarchitecture of the Intel MCS8051 is proprietary, but published<ref name="mcs51um">{{cite book |title=MCS-51 Microcontroller Family User's Manual |date=1994 |publisher=Intel |location=publication number 121517 |url=http://datasheets.chipdb.org/Intel/MCS51/MANUALS/27238302.PDF |access-date=17 May 2021 |ref=mcs51um}}</ref> features suggest how it works. It is a [[multi-cycle processor]]. The MCS8051 used 12 clock cycles<ref name="mcs51um"/> for most instructions. Many instructions utilize an accumulator.<ref name="mcs51um" /> In contrast, most compatible computers execute instructions in one to three cycles, except for the multiply and divide instructions. The much higher speed is a major reason why these have replaced the MCS8051 in most applications.

Each interrupt has four priorities.<ref name="mcs51um" /> Within each priority, the interrupts of devices are in a fixed priority.<ref name="mcs51um" />

== Instruction set ==
Instructions are all 1 to 3 bytes long, consisting of an initial opcode byte, followed by up to 2 bytes of operands.

{{frac|1|4}} of the opcode bytes, '''''x''0–''x''3''', are used for irregular opcodes.

{{frac|3|4}} of the opcode bytes, '''''x''4–''x''F''', are assigned to 16 basic ALU instructions with 12 possible operands.  The least significant [[nibble]] of the opcode selects the primary operand as follows:

* '''''x''8–''x''F''': Register direct, R0–R7.
* '''''x''6–''x''7''': Register indirect, @R0 or @R1.
* '''''x''5''': Memory direct, a following byte specifies an IRAM or SFR location.
* '''''x''4''': Immediate, a following byte specifies an 8-bit constant.  When the operand is a destination ({{code|lang=asm|INC operand}}, {{code|lang=asm|DEC operand}}) ''or'' the operation already includes an immediate source ({{code|lang=asm|MOV operand,#data}}, {{code|lang=asm|CJNE operand,#data,offset}}), this instead specifies that the accumulator is used.

The most significant nibble specifies the operation as follows.  Not all support all addressing modes; the immediate mode in particular is unavailable when the primary operand is written to.  Instruction mnemonics use ''destination'', ''source'' operand order.

; 0''y''{{colon}} {{code|lang=asm|INC operand}}: Increment the specified operand.  Immediate mode (opcode 0x04) specifies the accumulator, {{code|lang=asm|INC A}}.
; 1''y''{{colon}} {{code|lang=asm|DEC operand}}: Decrement the specified operand.  Immediate mode (opcode 0x14) specifies the accumulator, {{code|lang=asm|DEC A}}.
; 2''y''{{colon}} {{code|lang=asm|ADD A,operand}}: Add the operand to the accumulator, A.  Opcode 0x23 ({{code|lang=asm|RL A}}, "rotate left" but actually a [[shift left]]) may be thought of as {{code|lang=asm|ADD A,A}}.
; 3''y''{{colon}} {{code|lang=asm|ADDC A,operand}}: Add the operand, plus the C bit, to the accumulator.  Opcode 0x33 ({{code|lang=asm|RLC A}}, rotate left through carry) may be thought of as {{code|lang=asm|ADDC A,A}}.
; 4''y''{{colon}} {{code|lang=asm|ORL A,operand}}: Logical OR the operand into the accumulator.  Two memory-destination forms of this operation, {{code|lang=asm|ORL address,#data}} and {{code|lang=asm|ORL address,A}}, are specified by opcodes 0x43 and 0x42.
; 5''y''{{colon}} {{code|lang=asm|ANL A,operand}}: Logical AND the operand into the accumulator.  Two memory-destination forms of this operation, {{code|lang=asm|ANL address,#data}} and {{code|lang=asm|ANL address,A}}, are specified by opcodes 0x53 and 0x52.
; 6''y''{{colon}} {{code|lang=asm|XRL A,operand}}: Logical exclusive-OR the operand into the accumulator.  Two memory-destination forms of this operation, {{code|lang=asm|XRL address,#data}} and {{code|lang=asm|XRL address,A}}, are specified by opcodes 0x63 and 0x62.
; 7''y''{{colon}} {{code|lang=asm|MOV operand,#data}}: Move immediate to the operand.  Immediate mode (opcode 0x74) specifies the accumulator, {{code|lang=asm|MOV A,#data}}.
; 8''y''{{colon}} {{code|lang=asm|MOV address,operand}}: Move value to an IRAM or SFR register.  Immediate mode (opcode 0x84) is not used for this operation, as it duplicates opcode 0x75.
; 9''y''{{colon}} {{code|lang=asm|SUBB A,operand}}: Subtract the operand from the accumulator.  This operation borrows and there is no subtract ''without'' borrow.
; A''y''{{colon}} {{code|lang=asm|MOV operand,address}}: Move value from an IRAM or SFR register.  Immediate mode (opcode 0xA4) is not used, as immediates serve only as sources. Memory direct mode (opcode 0xA5) is not used, as it duplicates 0x85. 
; B''y''{{colon}} {{code|lang=asm|CJNE operand,#data,offset}}: Compare ''operand'' to the immediate {{code|lang=asm|#data}}, and jump to {{nowrap|PC + ''offset''}} if not equal.  Immediate and memory direct modes (opcodes 0xB4 and 0xB5) compare the operand against the accumulator, {{code|lang=asm|CJNE A,operand,offset}}.  Note that there is no compare and jump if equal instruction, {{code|lang=asm|CJE}}.
; C''y''{{colon}} {{code|lang=asm|XCH A,operand}}: Exchange the accumulator and the operand.  Immediate mode (opcode 0xC4) is not used for this operation.
; D''y''{{colon}} {{code|lang=asm|DJNZ operand,offset}}: Decrement the operand, and jump to {{nowrap|PC + ''offset''}} if the result is non-zero.  Immediate mode (opcode 0xD4), and register indirect mode (0xD6, 0xD7) are not used.
; E''y''{{colon}} {{code|lang=asm|MOV A,operand}}: Move operand to the accumulator.  Immediate mode is not used for this operation (opcode 0xE4), as it duplicates opcode 0x74.
; F''y''{{colon}} {{code|lang=asm|MOV operand,A}}: Move accumulator to the operand.  Immediate mode (opcode 0xF4) is not used, as it would have no effect.

Only the {{code|lang=asm|ADD}}, {{code|lang=asm|ADDC}}, and {{code|lang=asm|SUBB}} instructions set PSW flags.  The {{code|lang=asm|INC}}, {{code|lang=asm|DEC}}, and logical instructions do not.  The {{code|lang=asm|CJNE}} instruction modifies the C bit only, to the borrow that results from {{nowrap|''operand1'' − ''operand2''}}.

The irregular instructions comprise 64 opcodes, having more limited addressing modes, plus several opcodes scavenged from inapplicable modes in the regular instructions.

{| class=wikitable
|+ 8051/8052 irregular instructions
|-
! Opcode !! ''x''0 !! ''x''1 !! ''x''2 !! ''x''3 !! ''x''4
|-
! 0''y''
| {{code|lang=asm|NOP}}
| rowspan=16 | {{ubl
 | {{code|lang=asm|AJMP addr11}},
 | {{nobr|{{code|lang=asm|ACALL addr11}}}}
 }}
| {{code|lang=asm|LJMP addr16}} || {{code|lang=asm|RR A}} (rotate right) || {{n/a|{{code|lang=asm|INC A}}}}
|-
! 1''y''
| {{code|lang=asm|JBC bit,offset}} (jump if bit set with clear)
| {{nobr|{{code|lang=asm|LCALL addr16}}}} || {{code|lang=asm|RRC A}} (rotate right through carry) || {{n/a|{{code|lang=asm|DEC A}}}}
|-
! 2''y''
| {{code|lang=asm|JB bit,offset}} (jump if bit set)
| {{code|lang=asm|RET}} || {{code|lang=asm|RL A}} (rotate left) || {{n/a|{{code|lang=asm|ADD A,#data}}}}
|-
! 3''y''
| {{code|lang=asm|JNB bit,offset}} (jump if bit clear)
| {{code|lang=asm|RETI}} || {{code|lang=asm|RLC A}} (rotate left through carry) || {{n/a|{{code|lang=asm|ADDC A,#data}}}}
|-
! 4''y''
| {{code|lang=asm|JC offset}} (jump if carry set)
| {{n/a|{{code|lang=asm|ORL address,A}}}} || {{n/a|{{code|lang=asm|ORL address,#data}}}} || {{n/a|{{code|lang=asm|ORL A,#data}}}}
|-
! 5''y''
| {{code|lang=asm|JNC offset}} (jump if carry clear)
| {{n/a|{{code|lang=asm|ANL address,A}}}} || {{n/a|{{code|lang=asm|ANL address,#data}}}} || {{n/a|{{code|lang=asm|ANL A,#data}}}}
|-
! 6''y''
| {{code|lang=asm|JZ offset}} (jump if zero)
| {{n/a|{{code|lang=asm|XRL address,A}}}} || {{n/a|{{code|lang=asm|XRL address,#data}}}} || {{n/a|{{code|lang=asm|XRL A,#data}}}}
|-
! 7''y''
| {{code|lang=asm|JNZ offset}} (jump if non-zero)
| {{code|lang=asm|ORL C,bit}} || {{code|lang=asm|JMP @A+DPTR}} || {{n/a|{{code|lang=asm|MOV A,#data}}}}
|-
! 8''y''
| {{code|lang=asm|SJMP offset}} (short jump)
| {{code|lang=asm|ANL C,bit}} || {{code|lang=asm|MOVC A,@A+PC}} || {{code|lang=asm|DIV AB}}
|-
! 9''y''
| {{code|lang=asm|MOV DPTR,#data16}}
| {{code|lang=asm|MOV bit,C}} || {{code|lang=asm|MOVC A,@A+DPTR}} || {{n/a|{{code|lang=asm|SUBB A,#data}}}}
|-
! A''y''
| {{code|lang=asm|ORL C,/bit}}
| {{code|lang=asm|MOV C,bit}} || {{code|lang=asm|INC DPTR}} || {{code|lang=asm|MUL AB}}
|-
! B''y''
| {{code|lang=asm|ANL C,/bit}}
| {{code|lang=asm|CPL bit}} || {{code|lang=asm|CPL C}} || {{n/a|{{code|lang=asm|CJNE A,#data,offset}}}}
|-
! C''y''
| {{code|lang=asm|PUSH address}}
| {{code|lang=asm|CLR bit}} || {{code|lang=asm|CLR C}} || {{code|lang=asm|SWAP A}}
|-
! D''y''
| {{code|lang=asm|POP address}}
| {{code|lang=asm|SETB bit}} || {{code|lang=asm|SETB C}} || {{code|lang=asm|DA A}} (decimal adjust)
|-
! E''y''
| {{code|lang=asm|MOVX A,@DPTR}}
| {{code|lang=asm|MOVX A,@R0}} || {{code|lang=asm|MOVX A,@R1}} || {{code|lang=asm|CLR A}}
|-
! F''y''
| {{code|lang=asm|MOVX @DPTR,A}}
| {{code|lang=asm|MOVX @R0,A}} || {{code|lang=asm|MOVX @R1,A}} || {{code|lang=asm|CPL A}}
|}

; 85: {{code|lang=asm|MOV address,address}} move directly between two IRAM or SFR registers.
; A5: ''Unused'' 
; B5: {{code|lang=asm|CJNE A,address,offset}} compare accumulator to an IRAM or SFR register, and jump to {{nowrap|PC + ''offset''}} if not equal.
; D6–7: {{code|lang=asm|XCHD A,@R0–1}} exchange low-order nibble of operands.

The {{code|lang=asm|SJMP}} (short jump) opcode takes a signed relative offset byte operand and transfers control there relative to the address of the following instruction. The {{code|lang=asm|AJMP}}/{{code|lang=asm|ACALL}} opcodes combine the three most significant bits of the opcode byte with the following byte to specify an 11-bit destination that is used to replace 11 bottom bits of the PC register (top 5 bits of PC register remain intact).  For larger addresses, the {{code|lang=asm|LJMP}} and {{code|lang=asm|LCALL}} instructions allow a 16-bit destination.

One of the reasons for the 8051's popularity is its range of operations on single bits.  Bits are always specified by absolute addresses; there is no register-indirect or indexed addressing.  Instructions that operate on single bits are:

* {{code|lang=asm|SETB bit}}, {{code|lang=asm|CLR bit}}, {{code|lang=asm|CPL bit}}: Set, clear, or complement the specified bit
* {{code|lang=asm|JB bit,offset}}: Jump if bit set
* {{code|lang=asm|JNB bit,offset}}: Jump if bit clear
* {{code|lang=asm|JBC bit,offset}}: Jump if bit set, and clear bit
* {{code|lang=asm|MOV C,bit}}, {{code|lang=asm|MOV bit,C}}: Move the specified bit to the carry bit, or vice versa
* {{code|lang=asm|ORL C,bit}}, {{code|lang=asm|ORL C,/bit}}: Or the bit (or its complement) to the carry bit
* {{code|lang=asm|ANL C,bit}}, {{code|lang=asm|ANL C,/bit}}: And the bit (or its complement) to the carry bit

A bit operand is written in the form {{code|address.number}}. Because the carry flag is bit 7 of the bit-addressable program status word, the {{code|lang=asm|SETB C}}, {{code|lang=asm|CLR C}} and {{code|lang=asm|CPL C}} instructions are shorter equivalents to {{code|lang=asm|SETB PSW.7}}, {{code|lang=asm|CLR PSW.7}} and {{code|lang=asm|CPL PSW.7}}.

== Programming ==
There are various [[high-level programming language]] compilers for the 8051. Several [[C (programming language)|C]] compilers are available for the 8051, most of which allow the programmer to specify where each variable should be stored in its six types of memory, and provide access to 8051-specific hardware features such as the multiple register banks and bit manipulation instructions. There are many commercial C compilers.<ref>
Han-Way Huang.
[https://books.google.com/books?id=PnXNNGG_jMMC "Embedded System Design with C8051"].
p. 238.
</ref> [[Small Device C Compiler]] (SDCC) is a popular open-source C compiler.<ref>
{{cite book |author=Lewin A. R. W. Edwards |url=https://archive.org/details/pdfy-MKFMCCNbqENoR3Ft |title=So, You Wanna be an Embedded Engineer: The Guide to Embedded Engineering, from Consultancy to the Corporate Ladder |date=2006 |page=51|isbn=978-0-7506-7953-4 }}
</ref>
Other high level languages such as [[C++]], [[Forth (programming language)|Forth]],<ref name="camelforth">
{{cite web |author=Bradford J. Rodriguez |url=http://www.camelforth.com/page.php?4 |title=CamelForth/8051}}
</ref><ref name="bradford">
{{cite web |author=Brad Rodriguez |url=http://www.bradrodriguez.com/papers/moving7.htm |title=Moving Forth Part 7: CamelForth for the 8051}}
</ref><ref>{{cite web |url=http://www.forth.com/embedded/swiftx-embedded-systems-development-tools.html?MCU=8051 |title=8051 SwiftX Forth development |archive-url=https://web.archive.org/web/20150924014750/http://www.forth.com/embedded/swiftx-embedded-systems-development-tools.html?MCU=8051 |archive-date=2015-09-24 |url-status=dead}}</ref><ref>{{cite web |url=http://www.mpeforth.com/xc7.htm |title=MPE VFX Forth 7 cross compilers |archive-url=https://web.archive.org/web/20141023215234/http://www.mpeforth.com/xc7.htm |archive-date=2014-10-23 |url-status=dead}}</ref>
[[BASIC]], [[Object Pascal]], [[Pascal (programming language)|Pascal]], [[PL/M]] and [[Modula-2]] are available for the 8051, but they are less widely used<ref>{{Cite web |last=Agarwal |first=Tarun |date=2014-09-16 |title=Detailed Explanation about 8051 Programming in Assembly Language |url=https://www.elprocus.com/8051-assembly-language-programming/ |access-date=2024-10-21 |website=ElProCus - Electronic Projects for Engineering Students |language=en-US}}</ref> than C and [[Assembly language|assembly]].

Because IRAM, XRAM, and PMEM (read only) all have an address 0, C compilers for the 8051 architecture provide compiler-specific [[Directive (programming)|pragmas]] or other extensions to indicate where a particular piece of data should be stored (i.e. constants in PMEM or variables needing fast access in IRAM). Since data could be in one of three memory spaces, a mechanism is usually provided to allow determining to which memory a pointer refers, either by constraining the pointer type to include the memory space or by storing metadata with the pointer.

== Related processors ==
[[File:INTEL8031AH.png|thumb|right|Intel 8031 microcontrollers]]
[[File:Intel D87C51-3183.jpg|thumb|right|Intel D87C51 microcontroller]]

Intel discontinued its MCS-51 product line in March 2007;<ref>{{cite web |last1=Ganssle |first1=Jack |title=Intel bows out, discontinues MCS-51 |date=2006-05-29 |url=http://www.embedded.com/electronics-blogs/break-points/4025678/Intel-bows-out |archive-url=https://web.archive.org/web/20170813011859/http://www.embedded.com/electronics-blogs/break-points/4025678/Intel-bows-out |archive-date=2017-08-13 |url-status=dead}}</ref><ref>{{cite web |title=MCS 51, MCS 251 and MCS 96 Microcontroller Product Lines, the Intel 186, Intel386 and Intel486 Processors Product Lines, and the i960 32 Bit RISC Processor, PCN 106013-01, Product Discontinuance, Reason for Revision: Add Key Milestone information and revise description of change |publisher=Intel |date=2006-05-02 |url=http://qdms.intel.com/dm/d.aspx/7C715FEC-C598-444E-9EFB-2750B98F7956/PCN106013-01.pdf}}</ref> however, there are plenty of enhanced 8051 products or [[silicon intellectual property]] added regularly from other vendors.

The 8051's predecessor, the [[8048]], was used in the keyboard of the first [[IBM PC]], where it converted keypresses into the serial data stream which is sent to the main unit of the computer. An Intel 8049 served a similar role in the [[Sinclair QL]]. The 8048 and derivatives are still used {{As of|2007|alt=today}} for basic model keyboards.

The '''8031''' was a reduced version of the original 8051 that had no internal program ROM. To use this chip, external ROM had to be added containing the program that the 8031 would fetch and execute. An 8051 chip could be sold as a ROM-less 8031, as the 8051's internal ROM is disabled by the normal state of the EA pin in an 8031-based design. A vendor might sell an 8051 as an 8031 for any number of reasons, such as faulty code in the 8051's ROM, or simply an oversupply of 8051s and undersupply of 8031s.

[[File:Intel P8044AH.jpg|thumb|Intel P8044AH microcontroller]]
The '''8044''' (as well as the ROM-less 8344 and the 8744 with EPROM) added an [[Synchronous Data Link Control|SDLC]] controller to the 8051 core (especially for [[Bitbus]] applications).<ref>{{cite web |url=https://www.hoeben.com/bitbus.info/Intel_8044AH_8344AH.pdf |title=8044AH/8344AH/8744AH High Performance 8-bit Microcontroller with On-Chip Serial Communication Controller |publisher=Intel |date=October 1994}}</ref>

The '''8052''' was an enhanced version of the original 8051 that featured 256&nbsp;bytes of internal RAM instead of 128&nbsp;bytes, 8&nbsp;KB of ROM instead of 4&nbsp;KB, and a third 16-bit timer.  Most modern 8051-compatible microcontrollers include these features.

The '''8032''' had these same features as the 8052 except it lacked internal ROM program memory.

The '''8751''' was an 8051 with 4&nbsp;KB EPROM instead of 4&nbsp;KB ROM.  They were identical except for the non-volatile memory type.  This part was available in a ceramic package with a clear [[quartz]] window over the top of the die so [[Ultraviolet#Electrical and electronics industry|UV light]] could be used to erase the [[EPROM]].  Related parts are: 8752 had 8&nbsp;KB EPROM, 8754 had 16&nbsp;KB EPROM, 8758 had 32&nbsp;KB EPROM.

The '''80C537''' (ROM-less) and '''80C517''' (8 KB ROM)  are [[CMOS]] versions, designed for the [[automotive industry]]. Enhancements mostly include new and enhanced peripherals. The 80C5x7 has fail-safe mechanisms, analog signal processing facilities, enhanced timer capabilities, and a 32-bit arithmetic peripheral. Other features include:

* 256-byte on-chip RAM
* 256 directly addressable bits
* External program and data memory expandable up to 64&nbsp;KB
* 8-bit A/D converter with 12 multiplexed inputs
* Arithmetic peripheral can perform 16×16→32-bit multiplication, 32/16→16-bit division, 32-bit shift and 32-bit normalize operations
* Eight data pointers instead of one for indirect addressing of program and external data memory
* Extended watchdog facilities
* Nine I/O ports
* Two full-duplex serial interfaces with individual baud rate generators
* Four priority level interrupt systems, 14 interrupt vectors
* Three power-saving modes

<gallery mode="packed" heights="150px" caption="Intel MCS-51 [[second source]]s">
File:Intel_D87C51_AMD.jpg|[[AMD]] D87C51
File:MBL8031AH.jpg|[[Fujitsu]] MBL8031AH
File:Ic-photo-MHS--S-80C31--(8031-MCU).png|MHS S-80C31
File:Ic-photo-OKI--M80C31F--(8031-MCU).JPG|[[Oki Electric Industry|OKI]] M80C31
File:Ic-photo-Philips--80C31BH-3 16P--(8031-MCU).png|[[Philips]] PCB80C31
File:Ic-photo-Signetics--SCN8031H--(8031-MCU).JPG|[[Signetics]] SCN8031
File:Ic-photo-Temic--TS80C32X2-MCB-(8032-MCU).png|Temic TS80C32X2
</gallery>

=== Derivative vendors ===
More than 20 independent manufacturers produce MCS-51 compatible processors. {{citation needed|date=July 2017}}

<gallery mode="packed" heights="150px" caption="Intel MCS-51 derived microcontrollers">
File:Atmel 89c2051 gfdl.jpg|[[Atmel]] [[Atmel AT89 series|AT89C2051]]
File:SAB-C515-LN.jpg|[[Infineon]] SAB-C515
File:EPROM-Microcontroller Philips 87C654.jpg|[[Philips]] S87C654
File:Ic-photo-Siemens--SAB-C501G-1RP-(MCU).png|[[Siemens]] SAB-C501
File:STC89C52.jpg|STC Micro STC89C52
</gallery>

Other ICs or IPs compatible with the MCS-51 have been developed by [[Analog Devices]],<ref>{{cite web|url=http://www.analog.com/static/imported-files/data_sheets/ADUC832.pdf|access-date=30 April 2023|website=analog.com|title=MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kB Flash MCU|archive-date=28 May 2014|archive-url=https://web.archive.org/web/20140528075220/http://www.analog.com/static/imported-files/data_sheets/ADUC832.pdf|url-status=dead}}</ref> Integral [[Minsk]],<ref name=integral>{{cite web
| title=Микроконтроллеры и супервизоры питания Серии 1880; 1881; 1842; 588; 1345; 5518АП1ТБМ
| trans-title=Microcontrollers and Power Supervisors Series 1880; 1881; 1842; 588; 1345; 5518AP1TBM
| publisher=OAO "Integral"
| place=Minsk
| url=http://integral.by/ru/products/mikrokontrollery-i-supervizory-pitaniya-serii-1880-1881-1842-588-1345-5518ap1tbm
| language=ru
| access-date=6 January 2017
| archive-date=1 January 2017
| archive-url=https://web.archive.org/web/20170101125139/http://integral.by/ru/products/mikrokontrollery-i-supervizory-pitaniya-serii-1880-1881-1842-588-1345-5518ap1tbm
| url-status=dead
}}</ref>
Kristall [[Kyiv]],<ref name=kristall5701>{{cite web
 |title=Однокристальные микро-эвм 
 |trans-title=Single-chip microcomputers 
 |publisher=Kristall 
 |place=Kyiv 
 |url=http://krystall.net.ua/ru/products/53.html 
 |archive-url=https://web.archive.org/web/20120530003614/http://krystall.net.ua/ru/products/53.html 
 |archive-date=30 May 2012 
 |language=ru 
 |access-date=5 January 2017 
 |url-status=dead 
}}</ref> and
NIIET [[Voronezh]].<ref name=niiet>{{cite web
| title=Микроконтроллеры
| trans-title=Microcontrollers
| publisher=OAO "NIIET"
| place=Voronezh
| url=http://niiet.ru/goods/chips/microcont
| language=ru
| access-date=22 August 2017
| archive-url=https://web.archive.org/web/20170822175635/http://niiet.ru/goods/chips/microcont
| archive-date=22 August 2017
| url-status=dead
}}</ref>

== Use as intellectual property ==
Today, 8051s are still available as discrete parts, but they are mostly used as [[silicon intellectual property]] cores.<ref>{{Cite web|url=https://technobyte.org/8051-not-old-still-popular-use-why/|title=Why do we have to use the 8051? Isn't it too old?|last=Hussaini|date=20 August 2019|website=Technobyte|access-date=5 July 2023}}</ref> Available in hardware description language source code (such as [[VHDL]] or [[Verilog]]) or [[FPGA]] [[netlist]] forms, these cores are typically integrated within embedded systems, in products ranging from [[USB flash drive]]s to washing machines to complex wireless communication [[System on a chip|systems on a chip]]. Designers use 8051 silicon IP cores, because of the smaller size, and lower power, compared to 32-bit processors like [[ARM Cortex-M|ARM Cortex-M series]], [[MIPS architecture|MIPS]] and BA22.{{Citation needed|date=July 2018}}

Subsequent 8051 core designs have increased performance while retaining compatibility with the original MCS 51 instruction set. The original Intel 8051 was a microcode engine using 12 clocked microcode cycles per machine cycle to minimize the number of NMOS logic gates consuming power in passive resistive pull-ups. Most instructions executed in one or two machine cycles. At the typical maximum clock frequency of 12&nbsp;MHz the original 8051 types execute one million single-cycle instructions, or 500,000 two-cycle instructions, per second. The change to CMOS using active P-channel FET pull-ups makes it possible to realize the core without microcode. Enhanced 8051 IP cores run at one clock cycle per machine cycle. With clock frequencies of up to 450&nbsp;MHz an 8051-compatible processor can execute up to 450 million instructions per second.

== MCUs based on 8051 ==
{{Expand section|date=June 2021}}
[[File:Apple TV, 1st generation - mainboard - Silicon Storage Technology 89V54RD2-3214.jpg|thumb|Silicon Storage Technology 89V54RD2]]

* ABOV: MC94F, MC95F, MC96F series
* Analog Devices (formerly Maxim Integrated, originally Dallas): DS80-series etc.<ref>{{Cite web|title=DS80C320 Datasheet and Product Info|url=https://www.analog.com/en/products/ds80c320.html|access-date=2025-02-12|website=Analog Devices}}</ref>
* [[Cypress PSoC]] [[Cypress PSoC#Series|CY8C3xxxx series]], which has a dedicated [[USB 2.0]] interface<ref>{{Cite web |last= |first= |title=PSoC 3 - Infineon Technologies |url=https://www.infineon.com/cms/en/product/microcontroller/legacy-microcontroller/legacy-8-bit-16-bit-microcontroller/psoc-3/ |url-status=live |archive-url=https://web.archive.org/web/20220921010844/https://www.infineon.com/cms/en/product/microcontroller/legacy-microcontroller/legacy-8-bit-16-bit-microcontroller/psoc-3/ |archive-date=2022-09-21 |access-date=2023-05-20 |website=[[Infineon]] |language=en}}</ref>
* Jin Rui (brand CACHIP): [[CA51Fx]] family 8-bit MCUs.<ref>{{Cite web|title=Documentation|url=http://www.cachip.com.cn/Products_table/2080527.html|language=zh}}</ref>
* Infineon: [[XC800]]
* Mentor Graphics: M8051EW etc. designed for Mentor by [[SYNTILL8]]<ref>{{Cite web|title=Syntill8 - Products|url=http://www.syntill8.com/products.html|access-date=2021-06-21|website=www.syntill8.com}}</ref>
* Megawin: 74, 82, 84, 86, 87, and 89 series
*Microchip (formerly Atmel): [[Atmel AT89 series|AT89C51, AT89S51]], AT83C5134, etc.<ref name=":1" />
* NXP: NXP700 and NXP900 series
* Siemens 8-bit: SAB 8035/8048, SAB 80512/80532, SAB 80513, SAB 8352-2/8352-5, SAB 80(C)515/80(C)535, SAB 83515, SAB 80(C)517/80(C)537, SAB 8051A/8031A, SAB 8052A/8032A, SAB 8052B/8032B, SAB80C52/80C32, SDA 30C164-2 (ROMless)<ref>{{Cite web |title=SDA30C164 Datasheet |url=https://www.semiee.com/file/backup/SIEMENS-SDA30C164.pdf |access-date=2022-05-15 |website=www.semiee.com |archive-date=2022-06-17 |archive-url=https://web.archive.org/web/20220617123749/https://www.semiee.com/file/backup/SIEMENS-SDA30C164.pdf |url-status=dead }}</ref>
* [[Silergy]] electricity metering [[System On Chip|SoC]]s: 71M6511, 71M6513, 71M6531, 71M6533, 71M6534, 71M6542, 71M6543<ref>{{cite web |title=Silergy Metering ICs |url=https://www.silergy.com/products/electricity_metering_ics |publisher=Silergy Corp. |access-date=12 May 2021}}</ref> Energy measurement [[System On Chip|SoC]]s: 78M6631, 78M6618, 78M6613, 78M6612<ref>{{cite web |title=Silergy Energy Measurement ICs |url=https://www.silergy.com/products/energy_measurement_ics |publisher=Silergy Corp. |access-date=12 May 2021}}</ref>
* Silicon Labs: C8051 series and EFM8 series<ref name=":0" />
* [[Silicon Storage Technology]]: FlashFlex51 MCU (SST89E52RD2, SST89E54RD2, SST89E58RD2, SST89E516RD2SST89V52RD2, SST89V54RD2, SST89V58RD2, SST89V516RD2)<ref>{{Cite web|url=https://www.datasheetq.com/datasheet-download/190246/1/SST/89V54RD2|title=89V54RD2 Datasheet PDF Download - Silicon Storage Technology|last=datasheetq.com|website=www.datasheetq.com|language=en|access-date=2020-01-18}}</ref>
* STC Micro: STC89C51RC, STC90C51RC, STC90C58AD, STC10F08XE, STC11F60XE, STC12C5410AD, STC12C5202AD, STC12C5A60S2, STC12C5628AD, STC15F100, STC15F204EA, STC15F2K60S2, STC15F4K60S2, STC15F101W, STC15F408AD, STC15W104, STC15W408S, STC15W201S, STC15W408AS, STC15W1K16S and STC15W4K56S4 series<ref>{{Cite web|url=http://www.stcmicro.com/stcmcu.html|title=STC Microcontroller---STCmicro Technology Co,.Ltd|website=www.stcmicro.com|access-date=2017-02-19}}</ref>
* Texas Instruments CC111x, CC24xx and CC25xx families of RF SoCs
* WCH ([[Nanjing Qinheng Microelectronics]]): CH551, CH552, CH554, CH546, CH547, CH548, CH558, CH559<ref>{{Cite web|title=site index - Nanjing Qinheng Microelectronics Co., Ltd.|url=http://wch-ic.com/|access-date=2021-06-21|website=wch-ic.com}}</ref>

== Digital signal processor (DSP) variants ==
Several variants with an additional 16-bit [[digital signal processor]] (DSP) (for example for [[MP3]] or [[Vorbis]] coding/decoding) with up to 675 million instructions per second (MIPS)<ref>{{Cite web |url=http://www.8052.com/news?NEWSID=61 |title=TI Delivers new low-cost, high-performance audio DSP for Home and Car w/ 8051 |access-date=2013-05-06 |archive-url=https://web.archive.org/web/20161113175939/http://www.8052.com/news?NEWSID=61 |archive-date=2016-11-13 |url-status=dead }}</ref> and integrated [[USB 2.0]] interface<ref>{{Cite web|url=http://www.keil.com/dd/docs/datashts/atmel/at85c51snd3.pdf|title=Atmel AT85C51SND3 Audio DSP Data Sheet with USB 2.0|accessdate=30 April 2023}}</ref> or as intellectual property<ref>{{Cite book|chapter=Integration of 8051 With DSP in Xilinx FPGA|first1=A.J.|last1=Salim|first2=M.|last2=Othman|first3=M.A. Mohd|last3=Ali|title=2006 IEEE International Conference on Semiconductor Electronics|date=October 5, 2006|pages=562–566|via=IEEE Xplore|doi=10.1109/SMELEC.2006.380694|isbn=0-7803-9730-4|s2cid=21616742}}</ref> exist.

== {{anchor|MCS-151}}Enhanced 8-bit binary compatible microcontroller: MCS-151 family ==
{{Expand section|date=May 2013}}
In 1996 Intel announced the MCS-151 family, an up to 6 times faster variant,<ref name="1+2-51" >{{Cite web|url=http://datasheets.chipdb.org/Intel/MCS51/151BACK.HTM|title=Intel MCS 151 and MCS 251 Microcontrollers|website=datasheets.chipdb.org}}</ref> that's fully binary and [[instruction set]] compatible with 8051. Unlike their 8051 MCS-151 is a pipelined CPU, with 16-bit internal code bus and is 6x the speed. The MCS-151 family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants.

== {{anchor|MCS-251}}8/16/32-bit binary compatible microcontroller: MCS-251 family ==
{{Expand section|date=May 2013}}
The 80251 8/16/32-bit microcontroller with 16&nbsp;MB ([[24-bit]]) address-space and 6 times faster instruction cycle was introduced by Intel in 1996.<ref name="1+2-51"/><ref>{{cite book |url=https://books.google.com/books?id=l6lveWkWqFoC&dq=intel+80251&pg=PA400 |title=The 8051 microcontroller |author=Kenneth J Ayala|date=2005 |publisher=Thomson Delmar Learning |isbn=978-1-4018-6158-2 }}</ref> It can perform as an 8-bit 8051, has 24-bit [[linear addressing]], an 8-bit ALU, 8-bit instructions, 16-bit instructions, a limited set of 32-bit instructions, 16 8-bit registers, 16 16-bit registers (8 16-bit registers which do not share space with any 8-bit registers, and 8 16-bit registers which contain 2 8-bit registers per 16-bit register), and 10 32-bit registers (2 dedicated 32-bit registers, and 8 32-bit registers which contain 2 16-bit registers per 32-bit register).<ref>{{cite web
|url=http://datasheets.chipdb.org/Intel/MCS51/DATASHTS/27262001.PDF|access-date=30 April 2023|website=chipdb.org|title=MCSÉ 251 Architecture Overview}}</ref>

It features extended instructions<ref>{{Cite web|url=http://pe2bz.philpem.me.uk/pdf%20on%20typenumber/A-C/C251.pdf|title=Temic TSC80251 Architecture}}</ref> – see also the programmer's guide<ref>{{Cite web|url=http://www.cs.unc.edu/~vicci/comp261/project/mcu/80251_prog_man.pdf|title=Atmel TSC80251 Programmers Guide|access-date=2013-05-06|archive-date=2016-03-04|archive-url=https://web.archive.org/web/20160304051710/http://www.cs.unc.edu/~vicci/comp261/project/mcu/80251_prog_man.pdf|url-status=dead}}</ref> – and later variants with higher performance,<ref>{{cite web |url=http://dcd.pl/workspace/documentation/lat/dq80251_ds.pdf |title=DQ80251 32bit Microcontroller |website=DCD}}</ref> also available as intellectual property (IP).<ref>{{cite web |url=http://www.evatronix.pl/products/pdf/r80251xc_datasheet.pdf |title=R80251XC 32bit Microcontroller |website=Evatronix}}{{dead link|date=October 2018}}</ref> It is 3-stage pipelined. The MCS-251 family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants from many manufacturers.

== See also ==
* [[DS80C390]]
* [[Hitachi HD44780]] - LCD controller with XRAM-compatible interface
* [[Intel PL/M-51]]
* [[Intel system development kit#Intel SDK-51|SDK-51 system design kit]]

== References ==
{{Reflist}}

== Further reading ==
;Books
* {{cite book |title=The 8051 Microcontroller: A Systems Approach |last1=Mazidi |last2=McKinlay |last3=Mazidi |at=648 pp. |year=2012 |publisher=Pearson |isbn=978-0-13-508044-3}}
* {{cite book |title=C and the 8051 |edition=4th |first=Thomas |last=Schultz |at=464 pp. |year=2008 |publisher=Thomas W. Schultz |isbn=978-0-9783995-0-4}}
* {{cite book |title=The 8051/8052 Microcontroller: Architecture, Assembly Language, and Hardware Interfacing |first=Craig |last=Steiner |at=348 pp. |year=2005 |publisher=Universal-Publishers |isbn=978-1-58112-459-0}}
* {{cite book |title=8051 Microcontrollers: Hardware, Software and Applications |last1=Calcutt |last2=Cowan |last3=Parchizadeh |at=329 pp. |year=2000 |publisher=Elsevier |isbn=978-0-340-67707-0}}
* {{cite book |title=The Microcontroller Idea Book: Circuits, Programs, and Applications featuring the 8052-BASIC Microcontroller |first=Jan |last=Axelson
|author-link=Jan Axelson |at=277 pp. |year=1994 |publisher=Lakeview research LLC |isbn=978-0-9650819-0-0}}
* {{cite book |last=Payne |first=William |title=Embedded Controller FORTH for the 8051 Family |orig-year=1990 |type=hardcover |date=December 19, 1990 |publisher=Academic Press |location=Boston |isbn=978-0-12-547570-9 |at=528 pp.}}

;Intel
* ''[http://datasheets.chipdb.org/Intel/MCS51/MANUALS/27238302.PDF MCS-51 Microcontroller Family User's Manual]''; Intel; 1994; publication number 121517.
* ''MCS-51 Macro Assembler User's Guide''; Intel; publication number 9800937.
* ''8-Bit Embedded Controllers''; Intel; 1991; publication number {{not a typo|270645-003}}.
* ''Microcontroller Handbook''; Intel; 1984; publication number {{not a typo|210918-002}}.
* ''[https://archive.org/details/bitsavers_intel80518liminaryArchitecturalSpecificationMay80_6120863/ 8051 Microcontroller Preliminary Architectural Specification and Functional Description]''; Intel; 44 pages; 1980.

;Misc
* {{cite web |title=HEX.DOC: EASM51 - HEX Format (elektor Assembler) |author-first=Werner |author-last=Hennig-Roleff |language=de |date=1993-02-01 |orig-date=1988 |version=1.04 |work=SIM51 |url=http://spot.fho-emden.de/ftp/micro/sim51_04.zip |access-date=2021-12-08 |url-status=live |archive-url=https://web.archive.org/web/20170811161238/http://spot.fho-emden.de/ftp/micro/sim51_04.zip |archive-date=2017-08-11}} [https://web.archive.org/web/20210806202253/https://www.dos4ever.com/8031board/SIM51D_BASIC.zip][https://web.archive.org/web/20210806202253/https://www.dos4ever.com/8031board/SIM51_06.zip] (Besides the [[elektor assembler hex format|EASM]] format, the HEX.DOC file discusses various hex file formats by [[Intel HEX|Intel]], [[SREC (file format)|Motorola]], [[Tektronix hex format|Tektronix]], [[MOS Technology file format|MOS Technology]] and [[elektor]].)

== External links ==
{{Commons category-inline}}
* [https://web.archive.org/web/20101123154437/http://ikalogic.com/tut_8051_1.php Complete tutorial for 8051 microcontrollers]
* [http://www.edsim51.com/ the source website for tutorials and simulator for 8051]
* [http://www.dnatechindia.com/Tutorial/8051-Tutorial.html Basic 8051 Interfacing Circuits]
* [http://www.oreganosystems.at/?page_id=96 Open source VHDL 8051 implementation (Oregano Systems)]

{{Intel controllers}}
{{8bitMCUs}}

{{Authority control}}

{{DEFAULTSORT:Intel Mcs-51}}
[[Category:Intel microcontrollers]]