Editing Intel i960

{{Short description|RISC-based microprocessor design}}
{{Use mdy dates|date=July 2011}}
{{Infobox CPU
| name        = Intel i960
| image       = KL_Intel_i960_PGA.jpg
| caption     = Intel i960HA microprocessor
| produced-start = April 6, 1988<ref>{{cite news |title=A New Family of Intel Chips |url=https://www.nytimes.com/1988/04/06/business/company-news-a-new-family-of-intel-chips.html |access-date=4 December 2023 |newspaper=New York Times |date=April 6, 1988}}</ref>
| produced-end = 2007<ref>{{cite news |last=Smith |first=Tony |title=Intel cashes in ancient chips |url=https://www.theregister.co.uk/2006/05/18/intel_cans_386_486_960_cpus/ |date=May 18, 2006 |website=[[The Register]] |access-date=January 24, 2020}}</ref>
| slowest     = 10  | slow-unit     = MHz
| fastest     = 100  | fast-unit     = MHz
| fsb-slowest =   | fsb-slow-unit = 
| fsb-fastest =   | fsb-fast-unit = 
| manuf1      = Intel
| arch        = 
| data-width = 32 bits (33 bits in Extended architecture)
| sock1       = 
| numcores    = 1}}

[[Intel]]'s '''i960''' (or '''80960''') is a [[RISC]]-based [[microprocessor]] design that became popular during the early 1990s as an [[embedded system|embedded]] [[microcontroller]]. It became a best-selling CPU in that segment, along with the competing [[AMD 29000]].<ref>{{cite web |last=Turley |first=Jim |title=Embedded Processors, Part One |url=https://www.pcmag.com/article2/0,2817,1156709,00.asp |date=January 11, 2002 |website=[[PC Magazine|PCMag.com]] |access-date=September 8, 2018 |archive-date=July 19, 2018 |archive-url=https://web.archive.org/web/20180719175530/https://www.pcmag.com/article2/0,2817,1156709,00.asp |url-status=dead }}</ref> In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with [[Digital Equipment Corporation|DEC]] whereby Intel received the rights to produce the [[StrongARM]] CPU. The processor continues to be used for a few military applications.

==Origin==
[[File:KL Intel i960 PLCC.jpg|thumb|upright|Intel N80960SA ([[Plastic leaded chip carrier|PLCC]] Package)]]
[[File:KL Intel i960 BGA.jpg|thumb|upright|Intel GC80960RD66 (BGA Package)]]
[[File:KL Intel i960 BGA 2.jpg|thumb|upright|Intel GC80960RN, sSpec: SL3YW, BGA Package]]
[[File:KL Intel i960 PQFP.jpg|thumb|upright|Intel FC80960HD66 (PQFP Package)]]

The i960 design was begun in response to the failure of Intel's [[Intel iAPX 432|iAPX 432]] design of the early 1980s. The iAPX 432 was intended to directly support high-level languages that supported [[tagged architecture|tagged]], [[memory protection|protected]], [[garbage collection (computer science)|garbage-collected]] memory—such as [[Ada (programming language)|Ada]] and [[Lisp (programming language)|Lisp]]—in hardware. Because of its instruction-set complexity, its multi-chip implementation, and design flaws, the iAPX 432 was very slow in comparison to other processors of its time.

In 1984, Intel and [[Siemens]] started a joint project, ultimately called [[BiiN]], to create a high-end, fault-tolerant, object-oriented computer system programmed entirely in Ada. Many of the original i432 team members joined this project, although a new lead architect, [[Glenford Myers]], was brought in from [[IBM]]. The intended market for the BiiN systems was high-reliability-computer users such as banks, industrial systems, and nuclear power plants.

Intel's major contribution to the BiiN system was a new processor design, influenced by the protected-memory concepts from the i432. The new design was to include a number of features to improve performance and avoid problems that had led to the i432's downfall. The first 960 processors entered the final stages of design, known as ''[[tape out|taping-out]]'', in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986.

The BiiN effort eventually failed, due to market forces, and the 960 was left without a use. Myers attempted to save the design by extracting several subsets of the full capability architecture created for the BiiN system. He tried to convince Intel management to market the i960 (then still known as the "P7") as a general-purpose processor, both in place of the [[Intel 80286]] and [[i386]] (which taped-out the same month as the first i960), as well as the emerging RISC market for [[Unix]] systems, including a pitch to [[Steve Jobs]] for use in the [[NeXT]] system. Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems.

The lead architect of i960{{clarify|reason=When did Pollack replace Myers as the lead architect?|date=November 2024}} was [[superscalar]]ity specialist [[Fred Pollack]] who was also the lead engineer of the [[Intel iAPX 432]] and the lead architect of the i686 chip, the [[Pentium Pro]].<ref>{{cite web |last=Dvorak |first=John C. |author-link=John C. Dvorak |title=Whatever Happened to The iAPX432 — Intel's Dream Chip |url=http://www.dvorak.org/blog/whatever-happened-to-the-intel-iapx432/ |date=2008 |website=Dvorak.org |access-date=September 8, 2018}}</ref>

==Architecture==
The i960 family features four distinct architectures, designed for upward binary compatibility:
<ref name="80960xa">{{cite web |title=80960XA Embedded 32-bit Microprocessor with 33rd Tag Bit to Support Object-Oriented Programming and Data Security |url=http://www.bitsavers.org/components/intel/i960/271159-001_80960XA_Advance_Information_Oct90.pdf |publisher=Intel}}</ref>
* '''Core''' architecture is a RISC-like core
* '''Numerics''' architecture adds floating point
* '''Protected''' architecture adds paged memory management, supervisor/user protection, string instructions, process scheduling, interprocess communication for the OS, and symmetric multiprocessing
* '''Extended''' architecture adds object protection and interprocess communication for applications

In the initial release, the 80960KA supported the Core architecture, the 80960KB supported the Numerics architecture, the 80960MC supported the Protected architecture, and the 80960XA supported the Extended architecture.

To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design. In the Extended architecture, the memory subsystem was 33-bits wide—to accommodate a 32-bit word and a "tag" bit to implement memory protection in hardware. In many ways, the i960 followed the original [[Berkeley RISC]] design, notably in its use of [[register window]]s, an implementation-specific number of caches for the per-subroutine registers that allowed for fast subroutine calls. The competing [[Stanford University]] design, [[Stanford MIPS|MIPS]], did not use this system, instead relying on the compiler to generate optimal subroutine call and return code. In common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no [[segmented memory|memory segmentation]], except for the Extended architecture, which could support up to 2<sup>26</sup> "objects", each up to 2<sup>32</sup> bytes in size.<ref>{{cite book|url=http://bitsavers.org/pdf/biin/BiiN_CPU_Architecture_Reference_Man_Jul88.pdf|title=BiiN CPU Architecture Reference Manual|date=July 1998|publisher=BiiN}}</ref> The i960 architecture also anticipated a [[superscalar]] implementation, with instructions being simultaneously dispatched to more than one unit within the processor.

==i960 variants==

===80960MC===
The i960MC included all of the features of the original BiiN system; but these were simply not mentioned in the specifications, leading some{{who|date=July 2018}} to wonder why the i960MC was so large and had so many pins - 53 out of 132<ref>{{Cite web |url=http://www.bitsavers.org/components/intel/i960/271080-006_80960MC_Advance_Information_Jan91.pdf |title=80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT |date=1990 |access-date=2023-04-05 |website=Intel |pages=24–29}}</ref> - labeled "no connect". Later iterations of the i960, like the 80960Jx series, have a more typical number of "do no connect" and use more power and ground pins and have additional I/O pins instead.<ref>{{Cite web |url=http://www.bitsavers.org/components/intel/i960/80960JA_Data_Sheet_Mar98.pdf |title=80960JA/JF/JD/JT 3.3 V EMBEDDED 32-BIT MICROPROCESSOR |date=March 1998 |access-date=2023-04-05 |website=Intel |pages=22–25}}</ref> However, these "no connect" pins are actually not connected internally and unrelated to the BiiN feature set - the silicon die inside does not have bond pads for them.<ref>{{Cite web |url=http://www.righto.com/2023/07/the-complex-history-of-intel-i960-risc.html |title=The complex history of the Intel i960 RISC processor |date=2023-07-01 |access-date=2023-07-01 |website= |last=Shirriff |first=Ken |quote=The original i960 chips (KA/KB/MC/XA) have a large number of pins that are not connected (marked NC on the datasheet) [...] checking the datasheets shows that all four chips have the same pinout; there are no pins connected only in the more advanced versions. Second, looking at the packaged chip (below) explains why so many pins are unconnected: much of the chip has no bond pads, so there is nothing to connect the pins to.}}</ref>

The 80960MC contains an on-chip [[memory management unit]] and supports [[Fault tolerance|fault tolerant systems]] in conjunction with Intel's M82965 Bus Extension Unit as well. Both chips meets [[MIL-STD-883|MIL-STD-883C]] standard. Both chips became available in the first quarter of 1989 with the price of US$2400 and US$1700 respectively. Extended temperature samples became available in August 1988 as well.<ref name="Lewnes, Ann 1988, page 2">Lewnes, Ann, "Intel's 80960 & 80376 Standouts in the 32-Bit Crowd", Intel Corporation, Microcomputer Solutions, July/August 1988, page 2</ref>

It contains 32 32-bit registers, a 512 byte instruction cache, a [[Call stack#Structure|stack frame cache]], a high speed 32-bit [[Direct memory access|multiplexed burst bus]], and an interrupt controller.<ref name="Ormsby, Jon 1988, page 9">Ormsby, Jon, Editor, "New Product Focus: Components: Intel Enters The World Of 32-Bit Embedded Control", Intel Corporation, Microcomputer Solutions, May/June 1988, page 9</ref> It also has 256 interrupt vectors and 32 levels of interrupt priority.<ref name="Lewnes, Ann 1988, page 2"/>

===80960XA===
The 80960XA is a military member of the i960 family, implementing the Extended architecture, a superset of the military 80960MC. It supports object-oriented programming with a 33rd tag bit in hardware, a [[Capability-based security|Capability]]. It supports the Joint Industrial Avionics Working Group (JIAWG) 32-bit ISA standard.<ref name="80960xa" />

===80960KA, 80960KB===
A version of the RISC core without memory management or an [[floating point unit|FPU]] became the i960KA, and the RISC core with an FPU became the i960KB. The versions were, however, identical internally—only the labeling was different. This meant the CPUs were much larger than necessary for the "actually supported" feature sets, and as a result, more expensive to manufacture than they needed to be.

These processors contain more than 350,000 transistors. These processors can perform around 7.5 [[VAX Unit of Performance|VAX]] [[Instructions per second#Millions of instructions per second (MIPS)|MIPS]]. The 80960KB version is compatible with [[IEEE 754]] standard and can perform up to 4&nbsp;[[Whetstone (benchmark)|MWIPS]]. Both processors are available in 16 and 20&nbsp;MHz using [[CHMOS|CHMOS-III]] technology. Both processors are packaged in [[Pin grid array|132-PGA]]. The 80960KA version is available for US$230 and the 80960KB version is available for US$390 in quantities of 100 respectively.<ref name="Ormsby, Jon 1988, page 9"/>

The i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations, which were without the complex memory sub-system.

===80960CA, 80960CF===
The {{vanchor|i960CA}} was announced in July 1989. It featured a newly designed superscalar RISC core and added an unusual addressable on-chip cache, but lacked an FPU and MMU, as it was intended for high-performance embedded applications. The i960CA is widely considered<ref>{{cite book |last1=Shen |first1=John Paul |last2=Lipasti |first2=Mikko H. |title=Modern Processor Design: Fundamentals of Superscalar Processors |date=2003 |publisher=McGraw Hill |isbn=0-07-282968-0 |page=328 |edition=Beta}}</ref> to have been the first single-chip [[superscalar]] RISC implementation. The C-series included only one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, and a branch instruction at the same time, and sustain two instructions per cycle under certain circumstances. The first versions released ran at 33&nbsp;MHz, and Intel promoted the chip as capable of 66 MIPS. The i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12, 1989.

Later, in May 1992, came the i960CF, which included a larger instruction cache (4 KB instead of 1 KB) and added 1 KB of data cache, but was still without an FPU or MMU.

===80960MX===
The 80960MX is a superscalar implementation of the Extended architecture, executing up to three instructions per clock execution for sustained performance of 25 VAX MIPS.<ref name="intel-military">{{cite book |title=Military and Special Products Handbook |date=1993 |publisher=Intel |pages=11-40 to 11-89 |chapter=i960 MX Processor}}</ref> It implemented the Joint Industrial Avionics Working Group (JIAWG) 32-bit ISA standard. It was originally packaged in a 348 lead ceramic pin grid array and later supplied as a bare die. The i960 MX supports object-oriented programming. A 33rd tag bit distinguished between a 32-bit data word and a 32-bit pointer to memory. This prohibited forged pointers to protected areas of memory.

===80960Jx===
The 80960Jx is a processor for embedded applications. It features a 32-bit multiplexed address/data bus, instruction and data cache, 1K on-chip RAM, interrupt controller, and two independent 32-bit timers. The 80960Jx's testability features included ONCE (on-circuit emulation) mode and boundary scan ([[JTAG]]).

===80960HA, 80960HD, 80960HT===
The 80960Hx processors offered upgraded performance from the Cx variants by offering clock multiplication, larger 16K instruction cache and 4k data cache, and a GMU (Guarded Memory Unit). The HD variant had an internal 2× clock multiplication while the HT version has a 3x clock multiplication, allowing increased performance without external bus speed changes.

===80960VH===
Announced in October 1998, the i960VH Embedded-PCI processor featured a 32-bit 33&nbsp;MHz [[PCI Local Bus|PCI]] bus and 100&nbsp;MHz i960JT processor core. The core also featured 16&nbsp;KB of instruction cache, 4&nbsp;KB of data cache, and 1&nbsp;KB of built-in RAM. Other core features included two 32-bit timers, programmable interrupt controller, [[I²C]] interface, and a two-channel DMA controller.

===80960Rx===
The 80960Rx processors were labeled as I/O Processors and included an implementation of the [[PCI Local Bus|PCI]] Bus (2.1 or 2.2 depending on the variant) as well as a 80960Jx core. These could be used on motherboards to implement on-board PCI device as well as on PCI expansion cards. The RM/RN/RS variants used a JT core with a 3x bus to core multiplication to achieve 100&nbsp;MHz internal clock speeds, while the RD variant used a JF core with 2× multiplication to achieve 66&nbsp;MHz. The RP variant had a JF core that ran at the 33&nbsp;MHz bus speed.

==Variant specifications==

{| class="wikitable"
|+ 5&nbsp;V Parts
!Model Number || Core Frequency || Bus Frequency || Multiplier || iCache || dCache || Voltage || Socket
|-
|80960MC || 20,25&nbsp;MHz || 20,25&nbsp;MHz || 1.0x || 0.5&nbsp;KByte || ''none'' || 5.0 V || PGA-132
|-
|80960SA || 10,12,16,20&nbsp;MHz || 10,12,16,20&nbsp;MHz || 1.0x || 0.5&nbsp;KByte || ''none'' || 5.0 V || 80-PQFP,84-PLCC
|-
|80960SB || 10,16&nbsp;MHz || 10,16&nbsp;MHz || 1.0x || 0.5&nbsp;KByte || ''none'' || 5.0 V || 80-PQFP,84-PLCC
|-
|80960KA || 10,20,25&nbsp;MHz || 10,20,25&nbsp;MHz || 1.0x || 0.5&nbsp;KByte || ''none'' || 5.0 V || 132-PQFP,132-PGA
|-
|80960KB || 16,20,25&nbsp;MHz || 16,20,25&nbsp;MHz || 1.0x || 0.5&nbsp;KByte || ''none'' || 5.0 V || 132-PQFP,132-PGA
|-
|80960CA || 16,25,33&nbsp;MHz || 16,25,33&nbsp;MHz || 1.0x || 1&nbsp;KByte || ''none'' || 5.0 V || 168-PGA,196-PQFP
|-
|80960CF || 25,33,40&nbsp;MHz || 25,33,40&nbsp;MHz || 1.0x || 4&nbsp;KByte || 1&nbsp;KByte || 5.0 V || 168-PGA,196-PQFP
|}

{| class="wikitable"
|+ 3.3&nbsp;V Parts
!Model Number || Core Frequency || Bus Frequency || Multiplier || iCache || dCache || Voltage || Socket
|-
|80960JA || 16,25,33&nbsp;MHz || 16,25,33&nbsp;MHz || 1.0x || {{0}}2&nbsp;KByte || 1&nbsp;KByte || 3.3 V || 132-PQFP,132-PGA
|-
|80960JF || 25,33&nbsp;MHz || 25,33&nbsp;MHz || 1.0x || {{0}}4&nbsp;KByte || 2&nbsp;KByte || 3.3 V || 132-PQFP,132-PGA
|-
|80960JD || 33,40,50,66&nbsp;MHz || 16,20,25,33&nbsp;MHz || 2.0x || {{0}}4&nbsp;KByte || 2&nbsp;KByte || 3.3 V || 132-PQFP,132-PGA
|-
|80960JS || 25,33&nbsp;MHz || 25,33&nbsp;MHz || 1.0x || 16&nbsp;KByte || 4&nbsp;KByte || 3.3 V || 132-PQFP,132-PGA,196-MPBGA
|-
|80960JC || 50,66&nbsp;MHz || 25,33&nbsp;MHz || 2.0x || 16&nbsp;KByte || 4&nbsp;KByte || 3.3 V || 132-PQFP,132-PGA,196-MPBGA
|-
|80960JT || 75,100&nbsp;MHz || 25,33&nbsp;MHz || 3.0x || 16&nbsp;KByte || 4&nbsp;KByte || 3.3 V || 132-PQFP,132-PGA,196-MPBGA
|-
|80960HA || 25,33,40&nbsp;MHz || 25,33,40&nbsp;MHz || 1.0x || 16&nbsp;KByte || 8&nbsp;KByte || 3.3 V || 168-PGA,208-PQ4
|-
|80960HD || 50,66,80&nbsp;MHz || 25,33,40&nbsp;MHz || 2.0x || 16&nbsp;KByte || 8&nbsp;KByte || 3.3 V || 168-PGA,208-PQ4
|-
|80960HT || 75&nbsp;MHz || 25&nbsp;MHz || 3.0x || 16&nbsp;KByte || 8&nbsp;KByte || 3.3 V || 168-PGA,208-PQ4
|}

{| class="wikitable"
|+ PCI I/O Processor Variants
!Model Number || Core Frequency || Bus Frequency || Multiplier || iCache || dCache || PCI Version || Voltage || Socket
|-
|80960RP || 33&nbsp;MHz || 33&nbsp;MHz || 1.0x || {{0}}4&nbsp;KB || 2&nbsp;KB || [[PCI Local Bus|PCI]] 2.1 || 3.3 V || 352-PBGA
|-
|80960RD || 66&nbsp;MHz || 33&nbsp;MHz || 2.0x || {{0}}4&nbsp;KB || 2&nbsp;KB || [[PCI Local Bus|PCI]] 2.1 ||3.3 V || 352-PBGA
|-
|80960VH || 100&nbsp;MHz || 33&nbsp;MHz || 3.0x || 16&nbsp;KB || 4&nbsp;KB || [[PCI Local Bus|PCI]] 2.1 ||3.3 V || 324-PBGA
|-
|80960RM/N || 100&nbsp;MHz || 33&nbsp;MHz || 3.0x || 16&nbsp;KB || 4&nbsp;KB || [[PCI Local Bus|PCI]] 2.1 ||3.3 V || 540-PBGA
|-
|80960RS || 100&nbsp;MHz || 33&nbsp;MHz || 3.0x || 16&nbsp;KB || 4&nbsp;KB || [[PCI Local Bus|PCI]] 2.2 ||3.3 V || 540-PBGA
|-
|80302/3 || 100&nbsp;MHz || 66&nbsp;MHz || 1.5x || 16&nbsp;KB || 4&nbsp;KB || [[PCI Local Bus|PCI]] 2.2 ||3.3 V || 540-PBGA
|}

<gallery caption="[[Die shots]]" mode="packed">
Intel 80960MX die.jpg|Intel 80960MX
Intel 80960KA die.JPG|Intel 80960KA
Intel 80960SA die.JPG|Intel 80960SA
Intel 80960CA die.JPG|Intel 80960CA
Intel A80960CF-25.jpg|Intel 80960CF
Intel 80960JA die.jpg|Intel 80960JA
Intel 80960HD die.JPG|Intel 80960HD
</gallery>

==End of development==
Intel attempted to bolster the i960 in the I/O device controller market with the [[I2O]] standard, but this had little success and the design work was eventually ended. By the mid-1990s its [[price/performance ratio]] had fallen behind competing chips of more recent design, and Intel never produced a reduced-power-consumption version that could be used in battery-powered systems.

In 1990, the i960 team was redirected to be the "second team" working in parallel on future [[Intel i386|i386]] implementations—specifically the P6 processor, which later became the [[Pentium Pro]]. The i960 project was given to another smaller development team, essentially ensuring the end of its developmental life.

==Current status==
[[File:Mylex DAC960PG PJ.jpg|thumb|[[Mylex]] [[SCSI]] [[RAID]] controller for [[PCI bus]] uses a i960]]
Some i960 I/O processors, such as the 80303, include a built-in hardware [[XOR]] engine for [[RAID]] algorithms.<ref>{{cite web |title=Intel 80960RM I/O Processor Data Sheet |url=https://datasheet.octopart.com/GC80960RM100SL3YZ-Intel-datasheet-144932.pdf}}.</ref> They are used as controllers for higher-end, [[RAID]]-capable, [[SCSI]]-disk-array, host-adapter cards as well as Digital Equipment/Compaq/HP's high-end SCSI and [[Digital Storage Systems Interconnect|DSSI]], and eventually [[Fibre Channel]] HSx-series, standalone RAID controllers.<ref>{{cite web|url=http://www.dectrader.com/on_platform-storageworks-seminar-by-kevin-schumacher-mark-difabio-op.html|title=On Platform Storageworks Seminar notes |archive-url=https://web.archive.org/web/20120425092415/http://www.dectrader.com/on_platform-storageworks-seminar-by-kevin-schumacher-mark-difabio-op.html |archive-date=April 25, 2012}}</ref><ref>{{cite press release |date=2000-01-19 |title=Intel Expands I/O Building Block Family To Include Intel Integrated RAID Design Kit, Software And Controller |url=https://www.intel.com/pressroom/archive/releases/2000/io011900.htm|url-status=live |location=SANTA CLARA, Calif. |publisher=[[Intel]] |archive-url=https://web.archive.org/web/20200829121403/https://www.intel.com/pressroom/archive/releases/2000/io011900.htm |archive-date=2020-08-29 |access-date=2020-08-29}}</ref>

An i960RS chip also powers [[Adaptec]]'s AAR-2400A controller, which uses four commodity [[parallel ATA]] drives to build an affordable [[RAID-5]] protected fault-tolerant storage system for small PC servers and workstations.

The i960 was also used in some [[Brocade Communications Systems|Brocade]] [[Fibre Channel]] switches to run [[Fabric OS]].

The i960 architecture is also used in [[slot machine]]s. Currently, they are found in [[International Game Technology|IGT]]'s Stepper S2000 family and i960 video family. It was also used as the main CPU of [[Sega]]'s famous [[Sega Model 2|Model 2]] series of arcade boards.

The [[Indian Air Force]]'s [[HAL Tejas]] light combat aircraft's MMR (multi-mode radar) is said to use the i960. The HAL Tejas was introduced into service in 2015.

The [[Indian Space Research Organisation]] (ISRO) is said to use the chip in its on-board computers in its launch vehicles.

The i960 processor is also used in [[Automatic Radar Plotting Aid]] (ARPA) interfacing boards in [[radar]]s from [[Kelvin Hughes]].

The chip was used on some [[HP X-Terminals]].

Some [[SATA]] RAID controllers use Intel's 80303 IOP (Intelligent I/O Processor), which integrates a PCI-to-PCI bridge, memory controller, and a 80960JT-100 CPU core.

The chip was used on the [[Alcatel-Lucent]] 1000 [[ADSL]] [[broadband]] modem.<ref>{{cite web |url=https://security.sdsc.edu/self-help/alcatel/1000ADSL.jpg |title=Image of the circuit board of an Alcatel 1000 ADSL modem |website=security.sdsc.edu |access-date=September 24, 2018}}</ref>

==References==
{{Reflist}}

==External links==
{{Commons category}}
* [http://developer.intel.com/design/i960/INDEX.HTM i960 homepage at Intel] {{Webarchive|url=https://web.archive.org/web/20120716184329/http://developer.intel.com/design/i960/INDEX.HTM |date=July 16, 2012 }}
* [http://www.cpu-collection.de/?l0=co&l1=Intel&l2=i960 i960 images and descriptions at cpu-collection.de]
* [http://www.cpushack.com/i960ID.html Intel i960 ID Guide]
* [http://bitsavers.org/pdf/biin/BiiN_CPU_Architecture_Reference_Man_Jul88.pdf BiiN CPU Architecture Reference Manual (describes the Extended instruction set)], authored by [[Randal L. Schwartz]]
* [http://bitsavers.org/components/intel/i960/ i960 manuals at Bitsavers]

{{Intel processors|discontinued}}
{{Intel controllers}}
{{RISC-based processor architectures}}

{{Authority control}}

{{DEFAULTSORT:Intel I960}}
[[Category:Intel microcontrollers]]
[[Category:Intel microprocessors|I960]]
[[Category:Superscalar microprocessors]]
[[Category:32-bit microprocessors]]