Editing Link register

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A '''link register''' (LR for short) is a [[processor register|register]] which holds the address to return to when a [[subroutine]] call completes. This is more efficient than the more traditional scheme of storing return addresses  on a [[call stack]], sometimes called a machine stack. The link register does not require the writes and reads of the memory containing the stack which can save a considerable percentage of execution time with repeated calls of small subroutines.

The [[IBM POWER architecture]], and its [[PowerPC]] and [[Power ISA]] successors, have a special-purpose link register, into which subroutine call instructions put the return address.

In some other instruction sets, such as the [[ARM architectures]],  [[SPARC]], and [[OpenRISC]], subroutine call instructions put the return address into a specific [[general-purpose register]], so that register is designated by the instruction set architecture as the link register. The ARMv7 architecture uses general-purpose register R14 as the link register,<ref>{{cite web |url=https://developer.arm.com/documentation/ddi0403/latest/ |title=ARMv7-M Architecture Reference Manual |publisher=[[ARM Holdings|ARM]] |access-date=24 August 2022}}</ref><ref name="ARMv7-AR-Ref">{{cite web |url=https://developer.arm.com/documentation/ddi0406/latest |title=ARMv7-A and ARMv7-R Architecture Reference Manual; Arm Holdings |publisher=arm.com |access-date=24 August 2022}}</ref> OpenRISC uses register r9,<ref>{{cite web | url=https://sourceware.org/binutils/docs/as.html#OpenRISC_002dDependent | access-date=25 August 2022 | title=Using as, section 9.33.1.2 (OPENRISC Dependent Features/Register Names)}}</ref> and SPARC uses "output register 7" or ''o7''.<ref name="RTEMS, 2000">{{cite web | url=http://www.engr.usask.ca/classes/EP/414/lab/pdf/sparc.pdf | title=RTEMS SPARC Applications Supplement | date=May 2000 | accessdate=2013-04-19 | archive-url=https://web.archive.org/web/20190108145535/http://www.engr.usask.ca/classes/EP/414/lab/pdf/sparc.pdf | archive-date=8 January 2019}}</ref>

In some others, such as [[PA-RISC]], [[RISC-V]], and the [[IBM System/360]] and its successors, including [[z/Architecture]], the subroutine call instruction can store the return address in any general-purpose register; a particular register is usually chosen, by convention, to be used as the link register.

Some architectures have two link registers: a standard "branch link register" for most subroutine calls, and a special "interrupt link register" for interrupts. One of these is ARCv2 ([[ARC (processor)|ARC]] processors using version 2 of the ARCompact architecture), which uses general-purpose-registers r29 for the interrupt link register and r31 for the branch link register.<ref name=as_registers>{{cite web | url=https://sourceware.org/binutils/docs/as.html#ARC_002dRegs | access-date=25 August 2022 | title=Using as, section 9.3.2.2 (ARC Dependent Features/Syntax/Register Names)}}</ref><ref>{{cite web | url=https://raw.githubusercontent.com/wiki/foss-for-synopsys-dwc-arc-processors/toolchain/files/ARCv2_ABI.pdf | title=ARC Synopsys DesignWare ARCv2 System V ABI Supplement | access-date=25 August 2022 | url-status=live | archive-url=https://web.archive.org/web/20220825110522/https://raw.githubusercontent.com/wiki/foss-for-synopsys-dwc-arc-processors/toolchain/files/ARCv2_ABI.pdf | archive-date=25 August 2022}}</ref> References to "the link register" on such platforms will be referring to the branch link register.

Earlier ARC processors based on the ARCompact and ARCtangent architectures had three link registers: two interrupt link registers (ILINK) and one branch link register (BLINK).<ref name=as_registers/><ref name=ARCompactRef>{{cite web | url=http://me.bios.io/images/d/dd/ARCompactISA_ProgrammersReference.pdf | url-status=live | archive-url=https://web.archive.org/web/20220609141641/http://me.bios.io/images/d/dd/ARCompactISA_ProgrammersReference.pdf | archive-date=9 June 2022 | access-date=25 August 2022 | title=ARCompact Instruction Set Architecture Programmer's Reference | date=April 2008}}</ref><ref>{{cite web | url=http://me.bios.io/images/c/c6/ARC4._Programmers_reference.pdf | archive-url=https://web.archive.org/web/20220308200731/http://me.bios.io/images/c/c6/ARC4._Programmers_reference.pdf | access-date=25 August 2022 | archive-date=8 March 2022 | url-status=live | title=ARCtangent-A4 Programmer's Reference | date=August 2002}}</ref><ref>{{cite web | url=https://www.synopsys.com/dw/ipdir.php?ds=arc-access-member-lauterbach | access-date=25 August 2022 | title=Lauterbach | archive-url=https://web.archive.org/web/20160501021859/https://www.synopsys.com/dw/ipdir.php?ds=arc-access-member-lauterbach | archive-date=1 May 2016 | url-status=live}}</ref> The two interrupt link registers were ILINK1 (for level 1 (low priority) maskable interrupts), and ILINK2 (for level 2 (mid priority) maskable interrupts). In these architectures, r29 was used as the level 1 interrupt link register, r30 as the level 2 interrupt link register, and r31 as the branch link register. ILINK1 and ILINK2 were not accessible in user mode on the ARC 700 processors.<ref name=ARCompactRef/>

The use of a link register, regardless of whether it is a dedicated register or a general-purpose register, allows for faster calls to [[leaf subroutine]]s. When the subroutine is non-leaf, passing the return address in a register can still result in generation of more efficient code for [[thunk]]s, e.g. for a subroutine whose sole purpose is to call another subroutine with arguments rearranged in some way. Other subroutines can benefit from the use of the link register because it can be saved in a batch with other callee-used registers—e.g. an ARM subroutine pushes registers 4-7 along with the link register, LR, by the single instruction
<code>STMDB SP!, {R4-R7, LR}</code> pipelining all memory writes required.

==References==
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[[Category:Digital registers]]

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