Editing MMX (instruction set)

{{Short description|Instruction set designed by Intel}}
{{About|the instruction set for Intel Pentium and Pentium II processors|the operating system that used the abbreviation name as the latest version|Windows 3.0}}

{{Use mdy dates|date=October 2018}}
[[File:PentiumMMX-presslogo.jpg|thumb|Pentium with MMX]]
'''MMX''' is a ''single instruction, multiple data'' ([[SIMD]]) [[instruction set architecture]] designed by [[Intel]], introduced on January 8, 1997<ref name=NYT.1997Jan09>{{cite news
 |author=<!-- Unstated: staff writer -->
 |date=January 9, 1997
 |title=Makers Unveil PCs With Intel's MMX Chip
 |url=https://archive.nytimes.com/www.nytimes.com/library/cyber/week/010997intel.html
 |work=[[The New York Times]]
 |quote=Intel's new multimedia extension technology, called MMX, ...
 |access-date=January 13, 2019
 |archive-date=January 13, 2019
 |archive-url=https://web.archive.org/web/20190113232320/https://archive.nytimes.com/www.nytimes.com/library/cyber/week/010997intel.html
 |url-status=live
 }}</ref><ref>{{cite news |last1=Ch |first1=Rajiv |author2=rasekaran |date=January 8, 1997 |title=Intel to unveil faster Pentium chip |url=https://www.washingtonpost.com/archive/business/1997/01/08/intel-to-unveil-faster-pentium-chip/9d6bdbd2-51b0-4a56-b24a-f4b1ee8b795e |newspaper=[[The Washington Post]] |access-date=January 13, 2019 |archive-date=January 14, 2019 |archive-url=https://web.archive.org/web/20190114153329/https://www.washingtonpost.com/archive/business/1997/01/08/intel-to-unveil-faster-pentium-chip/9d6bdbd2-51b0-4a56-b24a-f4b1ee8b795e/ |url-status=live }}</ref> with its [[Pentium]] [[P5 (microarchitecture)]] based line of [[microprocessor]]s, named "Pentium with MMX Technology".<ref>{{cite web |url=http://www.intel.com/design/intarch/mmx/mmx.htm |title=Embedded Pentium Processors with MMX Technology |website=Intel |access-date=July 28, 2007 |archive-date=August 11, 2010 |archive-url=https://web.archive.org/web/20100811005125/http://www.intel.com/design/intarch/mmx/mmx.htm |url-status=live }}</ref> It developed out of a similar unit introduced on the [[Intel i860]],<ref>{{cite journal
 |last1=Mittal
 |first1=Millind
 |last2=Peleg
 |first2=Alex
 |last3=Weiser
 |first3=Uri
 |date=1997
 |title=MMX Technology Architecture Overview
 |url=http://www.intel.com/content/dam/www/public/us/en/documents/research/1997-vol01-iss-3-intel-technology-journal.pdf
 |journal=Intel Technology Journal
 |volume=1
 |issue=3
 |access-date=October 29, 2015
 |archive-date=March 4, 2016
 |archive-url=https://web.archive.org/web/20160304111409/http://www.intel.com/content/dam/www/public/us/en/documents/research/1997-vol01-iss-3-intel-technology-journal.pdf
 |url-status=live
 }}</ref> and earlier the [[Intel i750]] video pixel processor. MMX is a [[processor supplementary capability]]  that is supported on [[IA-32]] processors by Intel and other vendors {{as of|1997|lc=y}}. AMD also added MMX instruction set in its [[AMD K6|K6]] processor.

''[[The New York Times]]'' described the initial push, including [[Super Bowl]] advertisements, as focused on "a new generation of glitzy multimedia products, including videophones and 3-D video games."<ref name=NYT.1997Jan24>{{cite news
 |last=Calem
 |first=Robert E.
 |date=January 24, 1997
 |title=Intel's MMX: The Technology Behind the Hoopla
 |url=https://archive.nytimes.com/www.nytimes.com/library/cyber/week/012497intel.html
 |work=The New York Times
 |access-date=January 13, 2019
 |archive-date=January 13, 2019
 |archive-url=https://web.archive.org/web/20190113232421/https://archive.nytimes.com/www.nytimes.com/library/cyber/week/012497intel.html
 |url-status=live
 }}</ref>

MMX has subsequently been extended by several programs by Intel and others: [[3DNow!]], [[Streaming SIMD Extensions]] (SSE), and ongoing revisions of [[Advanced Vector Extensions]] (AVX).

==Overview==
===Naming===
MMX is officially a meaningless [[initialism]]<ref name=NW.97>{{cite magazine
 |last=Tanaka
 |first=Jennifer
 |date=February 16, 1997
 |title=A new chip off the block
 |url=https://www.newsweek.com/new-chip-block-175014
 |magazine=[[Newsweek]]
 |quote="the name, which doesn't stand for anything"
 |access-date=August 31, 2019
 |archive-date=August 31, 2019
 |archive-url=https://web.archive.org/web/20190831140255/https://www.newsweek.com/new-chip-block-175014
 |url-status=live
 }}</ref> [[trademark]]ed by Intel;<ref>{{Cite web|url=http://www.intel.com/content/www/us/en/trademarks/mmx.html|title=Intel &#124; Data Center Solutions, IoT, and PC Innovation|access-date=December 17, 2013|archive-date=December 17, 2013|archive-url=https://web.archive.org/web/20131217230027/http://www.intel.com/content/www/us/en/trademarks/mmx.html|url-status=live}}</ref> unofficially, the initials have been variously explained as standing for 
* ''MultiMedia eXtension'',<ref name=NYT.1997Jan09/> or 
* ''Matrix Math eXtension''.<ref>{{cite book |last1=Zhang |first1=Peng |title=Advanced Industrial Control Technology |date=1 January 2010 |publisher=William Andrew Publishing |location=(12) MMX technology |isbn=978-1-4377-7807-6 |pages=155–214 |chapter-url=https://www.sciencedirect.com/science/article/abs/pii/B9781437778076100051 |access-date=2 June 2024 |chapter=CHAPTER 5 - Microprocessors}}</ref>

[[Advanced Micro Devices]] (AMD), during one of its many court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions".{{cn|date=October 2022}} Since an [[initialism]] cannot be trademarked,{{cn|date=October 2022}} this was an attempt to invalidate Intel's trademark. In 1995, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, and with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name.<ref name=NYT.1997Apr22>{{cite news
 |date=April 22, 1997
 |title=Intel and Advance Micro agree on chip trademark
 |url=https://www.nytimes.com/1997/04/22/business/intel-and-advance-micro-agree-on-chip-trademark.html
 |work=[[The New York Times]]
 |access-date=January 13, 2019
 |archive-date=January 13, 2019
 |archive-url=https://web.archive.org/web/20190113232336/https://www.nytimes.com/1997/04/22/business/intel-and-advance-micro-agree-on-chip-trademark.html
 |url-status=live
 }}</ref>

===Technical details===
[[File:Pentium II.jpg|thumb|Pentium II processor with MMX technology]]
MMX defines eight [[processor register]]s, named MM0 through MM7, and operations that operate on them. Each register is 64 bits wide and can be used to hold either 64-bit [[integer]]s, or multiple smaller integers in a "packed" format: one instruction can then be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once.<ref name="MMXARCH">{{cite journal |last=Pfeiffer |first=Joseph J. Jr. |year=1997 |url=https://www.cs.nmsu.edu/~pfeiffer/classes/473/notes/micro.pdf |journal=Intel Technology Journal |title=MMX Microarchitecture of Pentium Processors With MMX Technology and Pentium II Microprocessors |access-date=September 1, 2017 |url-status=dead |archive-url=https://web.archive.org/web/20110112073044/http://www.cs.nmsu.edu/~pfeiffer/classes/473/notes/micro.pdf |archive-date=January 12, 2011}}</ref>

MMX provides only integer operations. When originally developed, for the [[Intel i860]], the use of integer math made sense (both 2D and 3D calculations required it), but as graphics cards that did much of this became common, integer [[SIMD]] in the CPU became somewhat redundant for graphical applications.{{Citation needed|date=January 2016}} Alternatively, the [[saturation arithmetic]] operations in MMX could{{vague|date=January 2016}} significantly speed up some [[digital signal processing]] applications.{{Citation needed|date=January 2016}}

To avoid compatibility problems with the [[context switch]] mechanisms in existing operating systems, the MMX registers are aliases for the existing [[x87]] [[floating-point unit]] (FPU) registers, which context switches would already save and restore. Unlike the x87 registers, which behave like a [[Stack (abstract data type)|stack]], the MMX registers are each directly addressable (random access).

Any operation involving the floating-point stack might also affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating-point and SIMD operations in the same program.<ref name="conte">{{cite conference |last1=Conte |first1=G. |last2=Tommesani |first2=S. |last3=Zanichelli |first3=F. |year=2000 |title=The long and winding road to high-performance image processing with MMX/SSE |conference=Proceedings of IEEE International Workshop on Computer Architectures for Machine Perception |url=https://air.unipr.it/retrieve/handle/11381/2297671/6288/camp2000.pdf |archive-url=https://web.archive.org/web/20160128221609/https://air.unipr.it/retrieve/handle/11381/2297671/6288/camp2000.pdf |url-status=dead |archive-date=2016-01-28}}</ref> To maximize performance, software often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.

Each 64-bit MMX register corresponds to the [[Significand|mantissa]] part of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, and these bits are all set to ones, making them ''Not a Number'' ([[NaN]]) data types, or infinities in the floating-point representation. This can be used by software to decide whether a given register's content is intended as floating-point or SIMD data.

===Software support===
Software support for MMX developed slowly.<ref name=NYT.1997Jan24/> [[Intel C++ Compiler|Intel's C Compiler]] and related development tools obtained [[intrinsic function|intrinsics]] for invoking MMX instructions and Intel released [[Library (computing)|libraries]] of common vectorized algorithms using MMX. Both Intel and [[Metrowerks]] attempted [[automatic vectorization]] in their compilers, but the operations in the [[C (programming language)|C]] programming language mapped poorly onto the MMX instruction set and custom algorithms as of 2000 typically still had to be written in [[assembly language]].{{r|conte}}

==Successors==
AMD, a competing [[x86]] microprocessor vendor, enhanced Intel's MMX with their own [[3DNow!]] instruction set. 3DNow is best known for adding single-precision (32-bit) floating-point support to the SIMD instruction-set, among other integer and more general enhancements.

Following MMX, Intel's next major x86 extension was the [[Streaming SIMD Extensions]] (SSE), introduced with the [[Pentium III]] family<ref name=WP.99>{{cite news |last=Kay |first=Alan S. |date=February 26, 1999 |title=Pentium III: Buy the Numbers? |url=https://www.washingtonpost.com/archive/business/technology/1999/02/26/pentium-iii-buy-the-numbers/b449fa0b-071a-41f7-a623-4781a3409a62/ |newspaper=[[The Washington Post]] |access-date=January 13, 2019 |archive-date=April 15, 2019 |archive-url=https://web.archive.org/web/20190415153149/https://www.washingtonpost.com/archive/business/technology/1999/02/26/pentium-iii-buy-the-numbers/b449fa0b-071a-41f7-a623-4781a3409a62/ |url-status=live }}</ref> in 1999,<ref>{{cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist_micro/hof/ |website=Intel Museum |url-status=dead |archive-url=https://web.archive.org/web/20080406154333/http://www.intel.com/museum/online/hist_micro/hof/ |archive-date=2008-04-06
}}</ref> roughly a year after AMD's 3DNow! was introduced.

SSE addressed the core shortcomings of MMX (inability to mix integer-SIMD ops with any floating-point ops) by creating a new 128-bit wide register file (XMM0–XMM7) and new SIMD instructions for it. Like 3DNow!, SSE focused exclusively on single-precision floating-point operations (32-bit); integer SIMD operations were still performed using the MMX register and instruction set. However, the new XMM register-file allowed SSE SIMD-operations to be freely mixed with either MMX or x87 FPU ops.

''Streaming SIMD Extensions 2'' ([[SSE2]]), introduced with the [[Pentium 4]], further extended the x86 SIMD instruction set with integer (8/16/32 bit) and double-precision floating-point data support for the XMM register file. SSE2 also allowed the MMX ''operation codes'' ([[opcode]]s) to use XMM register operands, extended to even wider YMM and ZMM registers by later SSE revisions.

== MMX in embedded applications ==
Intel's and [[Marvell Technology Group]]'s [[XScale]] microprocessor core starting with PXA270 include an [[SIMD]] [[instruction set architecture]] extension to the [[ARM architecture]] core named ''Intel Wireless MMX Technology'' (iwMMXt) which functions are similar to those of the [[IA-32]] MMX extension.<ref>{{cite web | url=https://www.intel.com/pressroom/archive/releases/2002/20020910net.htm | title= 	Intel Brings MMX™ Technology To Intel® Personal Internet Client Architecture-Based Wireless Devices  | access-date=28 July 2022}}</ref><ref>{{cite web | url=https://www.intel.com/pressroom/archive/releases/2004/20040412net.htm | title=Intel Delivers Next-Generation Processors Specifically Designed For Cell Phones And Wireless PDAs | access-date=28 July 2022 | url-status=live | archive-url=https://web.archive.org/web/20120102010704/https://www.intel.com/pressroom/archive/releases/2004/20040412net.htm | archive-date=2 January 2012 }}</ref><ref>{{cite web | url=https://www.eetimes.com/worlds-smallest-pxa270-embedded-cpu-card/ | title=World's smallest PXA270 embedded CPU card? | date=15 September 2004 | access-date=28 July 2022 | website=[[EE Times]]}}</ref> It provides arithmetic and logic operations on 64-bit integer numbers, in which the software may choose to instead perform two 32-bit, four 16-bit or eight 8-bit operations in one instruction. The extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA.{{Citation needed|date=July 2022}}

Later versions of Marvell's ARM processors support both ''Wireless MMX'' (WMMX) and ''Wireless MMX2'' (WMMX2) opcodes.

== See also ==
* [[Extended MMX]]
* [[AltiVec]] - equivalent on [[PowerPC]] architecture

==References==
{{Reflist}}

== External links ==
* [https://software.intel.com/sites/landingpage/IntrinsicsGuide/ Intel Intrinsics Guide]
* [http://www.intel.com/design/archives/Processors/mmx/ Intel Pentium Processor with MMX Technology Documentation]
* [https://web.archive.org/web/20121008000143/http://download.intel.com/support/processors/pentiumii/sb/24319002.pdf IA Software Developer's Manual, Vol 1 (PDF)], see chapter 8 for MMX programming

{{Intel technology}}
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[[Category:Computer-related introductions in 1997]]
[[Category:SIMD computing]]
[[Category:X86 instructions]]