Editing MOS Technology 6502

{{Short description|8-bit microprocessor from 1975}}

{{Infobox CPU
|name         = MOS Technology 6502
|image        = MOS 6502AD 4585 top.jpg
|caption      = 6502 processor in a [[Dual in-line package|DIP-40]] plastic package. The four-digit [[date code]] indicates it was made in the 45th week (November 4–10) of 1985.
|produced-start={{Start date and age|1975}}
|produced-end = 
|slowest      = 1 |slow-unit=MHz
|fastest      = 3 |fast-unit=MHz
|manuf1=[[MOS Technology]], [[Rockwell International|Rockwell]], [[Synertek]]
|arch         = MOS 6502
|transistors  = 3,510,<ref>{{cite web |title=The MOS 6502 and the Best Layout Guy in the World |publisher=swtch.com |date=2011-01-03 |access-date=2014-08-09 |url=http://research.swtch.com/6502 |archive-date=2014-09-08 |archive-url=https://web.archive.org/web/20140908121520/http://research.swtch.com/6502 |url-status=live}}</ref> 3,218<ref>{{cite web |title=MOnSter6502 A complete, working discrete transistors (i.e. not integrated all on a single chip) replica of the classic MOS 6502 microprocessor |publisher=monster6502.com |date=2017 |access-date=2017-05-01 |url=http://monster6502.com/ |archive-date=2017-05-12 |archive-url=https://web.archive.org/web/20170512051122/http://monster6502.com/ |url-status=live }}</ref>
|numinstructions = 56 (55 originally)
|data-width   = [[8-bit computing|8 bits]]
|address-width=[[16-bit computing|16 bits]]
|pack1=40-pin [[Dual in-line package|DIP]]
|predecessor  = {{Plainlist|
*[[Motorola 6800]]
*MOS 6501}}
|successor    = {{Plainlist|
*[[MOS Technology 6510|MOS 6510]]
*[[WDC 65C02]]
*[[WDC 65C816]]}}
}}

The '''MOS Technology 6502''' (typically pronounced "sixty-five-oh-two" or "six-five-oh-two")<ref name="Mensch interview">{{cite interview |url=https://exhibits.stanford.edu/silicongenesis/catalog/kb642ng6104 |title=Interview with William Mensch |date=October 9, 1995 |medium=Web video |publisher=[[Silicon Genesis Project]], Stanford University Libraries |location=Atherton, California |subject=William Mensch |interviewer=Rob Walker |access-date=December 22, 2023 |archive-date=March 4, 2016 |archive-url=https://web.archive.org/web/20160304091031/http://silicongenesis.stanford.edu/transcripts/mensch.htm |url-status=live }} William Mensch and the moderator both pronounce the 6502 microprocessor as ''"sixty-five-oh-two"''.</ref> is an [[8-bit computing|8-bit]] [[microprocessor]] that was designed by a small team led by [[Chuck Peddle]] for [[MOS Technology]]. The design team had formerly worked at [[Motorola]] on the [[Motorola 6800]] project; the 6502 is essentially a simplified, less expensive and faster version of that design.

When it was introduced in 1975, the 6502 was the least expensive microprocessor on the market by a considerable margin. It initially sold for less than one-sixth the cost of competing designs from larger companies, such as the 6800 or [[Intel 8080]]. Its introduction caused rapid decreases in pricing across the entire processor market. Along with the [[Zilog Z80]], it sparked a series of projects that resulted in the [[home computer]] [[microcomputer revolution|revolution]] of the early 1980s.

[[Home video game console]]s and home computers of the 1970s through the early 1990s, such as the [[Atari 2600]], [[Atari 8-bit computers]], [[Apple II]], [[Nintendo Entertainment System]], [[Commodore 64]], [[Atari Lynx]], [[BBC Micro]] and others, use the 6502 or variations of the basic design. Soon after the 6502's introduction, MOS Technology was purchased outright by [[Commodore International]], who continued to sell the microprocessor and licenses to other manufacturers. In the early days of the 6502, it was [[second source|second-sourced]] by [[Rockwell International|Rockwell]] and [[Synertek]], and later licensed to other companies.

In 1981, the [[Western Design Center]] started development of a [[CMOS]] version, the [[WDC 65C02|65C02]]. This continues to be widely used in [[embedded system]]s, with estimated production volumes in the hundreds of millions.<ref>{{Cite web|url=http://www.westerndesigncenter.com/wdc/|title=Western Design Center (WDC) Home of 65xx Microprocessor Technology|website=www.westerndesigncenter.com|access-date=2019-04-08|archive-date=2019-04-08|archive-url=https://web.archive.org/web/20190408025716/http://www.westerndesigncenter.com/wdc/|url-status=live}}</ref>

==History and use==

===Conception===
The origins of the 6502 chip date back to 1960, after the [[Soviet Union]] launched the first artificial Earth satellite – the [[Sputnik 1]]. During this time, Peddle worked at [[General Electric]] as an engineer-in-training, designing tests and systems for missiles and spaceships. As he advanced into his engineering career, he found room-sized computers to be a flawed model of centralized intelligence, and instead, considered distributing it locally. However, General Electric sold its computer division to [[Honeywell]] in 1970, liquidating the entire section he worked on.<ref name="Guston">{{cite book|last1=Guston|first1=David H.|title=Encyclopedia of Nanoscience and Society|date=2010|publisher=Sage Publications|page=272|url=https://books.google.com/books?id=vyp1AwAAQBAJ&pg=PA272|access-date=May 5, 2017|isbn=9781452266176|archive-date=January 20, 2021|archive-url=https://web.archive.org/web/20210120190132/https://books.google.com/books?id=vyp1AwAAQBAJ&pg=PA272|url-status=live}}</ref> Undeterred, Peddle took this severance and started his own company in 1972 to make intelligent terminals for word-processing.<ref name=Byte>{{cite web |url=http://www.commodore.ca/gallery/magazines/misc/chuck_peddle-byte-november_1982_sm.pdf |title=Chuck Peddle Byte Interview |publisher=[[Byte (magazine)|Byte]]}}</ref><ref name="LowSpec">{{cite video|url=https://m.youtube.com/watch?v=lP2ZBp9O0mk|date=April 29, 2022|title=The First LowSpec Processor|author=LowSpecGamer|work=[[YouTube]]|access-date=March 5, 2025}}</ref>

Shortly after, Peddle suddenly found himself in a technological struggle; even though electronics were evolving at the time, it was still ridiculously complex to run the system he conceived. His idea required a microprocessor that would be capable of running programs. However, he was far from the first to realize many companies were competing on the same technology for the same reason, including Motorola.<ref name="LowSpec"/>

===Origins at Motorola===
[[File:Motorola 6800 proto board.jpg|thumb|Motorola 6800 demonstration board built by Chuck Peddle and John Buchanan in 1974]]

The 6502 was designed by many of the same engineers that had designed the [[Motorola 6800]] microprocessor family.<ref name="MD Dec 1975 6502 Law Suit">{{Cite journal |title=Motorola Sues MOS Technology |journal=Microcomputer Digest |volume=2 |issue=6 |page=11 |publisher=Microcomputer Associates |location=Cupertino CA |date=December 1975 |url=http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n06_Dec75.pdf |archive-url=https://web.archive.org/web/20090704150106/http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n06_Dec75.pdf |url-status=dead |archive-date=July 4, 2009}}</ref> Motorola started the 6800 microprocessor project in 1971 with Tom Bennett as the main architect. Motorola's engineers could run analog and digital simulations on an [[IBM System/370|IBM 370-165]] mainframe computer.<ref name="MOS Modeling">{{Cite journal |last=Jenkins |first=Francis |author2=Lane, E. |author3=Lattin, W. |author4=Richardson, W. |title=MOS-device modeling for computer implementation |journal=IEEE Transactions on Circuit Theory| volume=20 |issue=6 |pages=649–658 |publisher=IEEE |date=November 1973 |issn=0018-9324 |doi=10.1109/tct.1973.1083758}} All of the authors were with Motorola's Semiconductor Products Division.</ref> The chip layout began in late 1972, the first 6800 chips were fabricated in February 1974 and the full family was officially released in November 1974.<ref name="MC6800 March 1974">{{Cite journal |title=Motorola joins microprocessor race with 8-bit entry |journal=Electronics |volume=47 |issue=5 |pages=29–30 |publisher=McGraw-Hill |location=New York |date=March 7, 1974}}</ref><ref>Motorola 6800 Oral History (2008), p. 9</ref> 

John Buchanan was the designer of the 6800 chip<ref name="Buchanan 3942047">{{Cite patent|number=US3942047A|title=MOS DC Voltage booster circuit|gdate=1976-03-02|invent1=Buchanan|inventor1-first=John K.|url=https://patents.google.com/patent/US3942047A/en}} {{Webarchive|url=https://web.archive.org/web/20240213150624/https://patents.google.com/patent/US3942047A/en |date=2024-02-13 }}</ref><ref name="Buchanan 3987418">{{Cite patent|number=US3987418A|title=Chip topography for MOS integrated circuitry microprocessor chip|gdate=1976-10-19|invent1=Buchanan|inventor1-first=John K.|url=https://patents.google.com/patent/US3987418A/en}} {{Webarchive|url=https://web.archive.org/web/20240213150626/https://patents.google.com/patent/US3987418A/en |date=2024-02-13 }}</ref> and Rod Orgill, who later did the 6501, assisted Buchanan with circuit analyses and chip layout.<ref>Motorola 6800 Oral History (2008), p. 8</ref> [[Bill Mensch]] joined Motorola in June 1971 after graduating from the University of Arizona (at age 26).<ref>Mensch Oral History (1995) Mensch earned an Associate degree from Temple University in 1966 and then worked at Philco Ford as an electronics technician before attending the University of Arizona.</ref> His first assignment was helping define the peripheral ICs for the 6800 family and later he was the principal designer of the 6820 [[Peripheral Interface Adapter]] (PIA).<ref name="Mensch 3968478">{{Cite patent|number=US3968478A|title=Chip topography for MOS interface circuit|gdate=1976-07-06|invent1=Jr|inventor1-first=William D. Mensch|url=https://patents.google.com/patent/US3968478A/en}} {{Webarchive|url=https://web.archive.org/web/20240213150625/https://patents.google.com/patent/US3968478A/en |date=2024-02-13 }}</ref> Bennett hired [[Chuck Peddle]] in 1973 to do architectural support work on the 6800 family products already in progress.<ref name="EDN Oct 27 1988">{{cite journal |last=Donohue |first=James F.| title=The microprocessor first two decades: The way it was |journal=EDN |volume=33 |issue=22A |pages=18–32 |publisher=Cahners Publishing |date=October 27, 1988 |issn=0012-7515}} Page 30. Bennett already was at work on what became the 6800. "He hired me," Peddle says of Bennett, "to do the architectural support work for the product he'd already started." … Peddle says. "Motorola tried to kill it several times. Without Bennett, the 6800 would not have happened, and a lot of the industry would not have happened, either."</ref> He contributed in many areas, including the design of the 6850 ACIA (serial interface).<ref name="Peddle 3968478">{{Cite patent|number=US3975712A|title=Asynchronous communication interface adaptor|gdate=1976-08-17|invent1=Hepworth|invent2=Means|invent3=Peddle|inventor1-first=Edward C.|inventor2-first=Rodney J.|inventor3-first=Charles I.|url=https://patents.google.com/patent/US3975712A/en}} {{Webarchive|url=https://web.archive.org/web/20240213150626/https://patents.google.com/patent/US3975712A/en |date=2024-02-13 }}</ref>

Motorola's target customers were established electronics companies such as [[Hewlett-Packard]], [[Tektronix]], [[TRW Inc.|TRW]], and [[Chrysler]].<ref name="M6800 TRW HP RUSCO">{{Cite journal |last=Motorola |title=They stay out front with Motorola's M6800 Family |journal=Electronics |volume=49 |issue=16 |page=51 |publisher=McGraw-Hill |date=August 5, 1976 |url=http://commons.wikimedia.org/wiki/File:Motorola_MC6800_microprocessor_ad_August_1976.jpg |access-date=June 4, 2012 |archive-date=January 10, 2014 |archive-url=https://web.archive.org/web/20140110190436/http://commons.wikimedia.org/wiki/File:Motorola_MC6800_microprocessor_ad_August_1976.jpg |url-status=live}} Advertisement showing three embedded applications from TRW, HP and RUSCO.</ref> In May 1972, Motorola's engineers began visiting select customers and sharing the details of their proposed 8-bit microprocessor system with ROM, RAM, parallel and serial interfaces.<ref>Motorola 6800 Oral History (2008), p. 89</ref> In early 1974, they provided engineering samples of the chips so that customers could prototype their designs. Motorola's "total product family" strategy did not focus on the price of the microprocessor, but on reducing the customer's total design cost. They offered development software on a timeshare computer, the "EXORciser" debugging system, onsite training and field application engineer support.<ref name="Electronics Jan 1975">{{Cite journal |title=It's the total product family |journal=Electronics |volume=48 |issue=1 |page=37 |url=http://commons.wikimedia.org/wiki/File:Motorola_6800_Total_Product_Family_1975.jpg |publisher=McGraw Hill |location=New York |date=January 9, 1975 |access-date=June 4, 2012 |archive-date=November 11, 2012 |archive-url=https://web.archive.org/web/20121111004455/http://commons.wikimedia.org/wiki/File:Motorola_6800_Total_Product_Family_1975.jpg |url-status=live}} Motorola advertisement emphasizing their complete set of peripheral chips and development tools. This shortened the customer's product design cycle.</ref><ref>Motorola 6800 Oral History (2008) p. 18</ref> Both Intel and Motorola had initially announced a {{US$|360}} price for a single microprocessor.<ref name="MC6850 1975">{{Cite journal |title=Motorola microprocessor set is 1 MHz n-MOS |journal=Control Engineering |volume=21 |issue=11 |page=11 |date=November 1974}} MC6800 microprocessor price was $360. The MC6850 asynchronous communications interface adaptor (ACIA) was slated for first quarter 1975 introduction.</ref><ref name="Intel $360">{{cite book |editor-first=Glynnis Thompson |editor-last=Kaye |title=A Revolution in Progress: A History to Date of Intel |publisher=Intel Corporation |year=1984 |page=14 |url=http://www.intel.com/Assets/PDF/General/15yrs.pdf |id=Order number:231295 |url-status=dead |access-date=30 December 2016 |archive-url=https://web.archive.org/web/20121023005651/http://www.intel.com/Assets/PDF/General/15yrs.pdf |archive-date=23 October 2012}} "Shima implemented the 8080 in about a year and the new device was introduced in April 1974 for $360."</ref> The actual price for production quantities was much less. Motorola offered a design kit containing the 6800 with six support chips for {{US$|300}}.<ref name="Electronics April 17, 1975">{{Cite journal |title=Motorola mounts M6800 drive |journal=Electronics |volume=48 |issue=8 |page=25 |publisher=McGraw-Hill |location=New York |date=April 17, 1975}} "Distributors are being stocked with the M6800 family, and the division is also offering an introductory kit that includes the family's six initial parts, plus applications and programming manuals, for $300."</ref>

Peddle, who would accompany the salespeople on customer visits, found that customers were put off by the high cost of the microprocessor chips.{{sfn|Interview|2014|loc=52:30}} At the same time, these visits invariably resulted in the engineers he presented to producing lists of required instructions that were much smaller than "all these fancy instructions" that had been included in the 6800.{{sfn|Interview|2014|loc=54:45}} Peddle and other team members started outlining the design of an improved feature, reduced-size microprocessor. At that time, Motorola's new semiconductor fabrication facility in [[Austin, Texas]], was having difficulty producing MOS chips, and mid-1974 was the beginning of a year-long recession in the semiconductor industry. Also, many of the [[Mesa, Arizona]] employees were displeased with the upcoming relocation to Austin.<ref>Bagnall (2010), p. 11. Peddle's new offer came at an opportune time for the 6800 developers. "They didn't want to go to Austin, Texas," explains Mensch.</ref>

Motorola's Semiconductor Products Division management showed no interest in Peddle's low-cost microprocessor proposal. Eventually, Peddle was given an official letter telling him to stop working on the system.{{sfn|Interview|2014|loc=54:40}} Peddle responded to the order by informing Motorola that the letter represented an official declaration of "project abandonment", and as such, the intellectual property he had developed to that point was now his.{{sfn|Interview|2014|loc=55:50}} In a November 1975 interview, Motorola's Chairman, Robert Galvin, ultimately agreed that Peddle's concept was a good one and that the division missed an opportunity, "We did not choose the right leaders in the Semiconductor Products division." The division was reorganized and the management replaced. The new group vice president John Welty said, "The semiconductor sales organization lost its sensitivity to customer needs and couldn't make speedy decisions."<ref name="Electronics Nov 13 1975">{{Cite journal |last=Waller |first=Larry |title=Motorola seeks to end skid |journal=Electronics |volume=48 |issue=23 |pages=96–98 |publisher=McGraw-Hill |location=New York |date=November 13, 1975}} Summary: Semiconductor Products split into two parts, integrated circuits and discrete components. Semiconductor losses for the last four quarters exceeded $30 million. The sales organization lost its sensitivity to customer needs, "delays in responding to price cuts meant that customers bought elsewhere." Technical problems plagued IC production. The troubles are "not in design, but in chip and die yields." Problems have been solved. The MC6800 microprocessor "arrived in November 1974."</ref>

===MOS Technology===
[[File:MOS Technology ad April 26 1973.jpg|thumb|A 1973 MOS Technology advertisement highlighting their custom integrated circuit capabilities]]
[[File:6501chip.jpg|thumb|MOS Technology MCS6501, in white ceramic package, made in late August 1975]]
Peddle began looking outside Motorola for a source of funding for this new project. He initially approached [[Mostek]] CEO [[L. J. Sevin]], but was declined. Sevin later admitted this was because he was afraid Motorola would sue them.{{sfn|Interview|2014|loc=56:30}}

While Peddle was visiting [[Ford Motor Company]] on one of his sales trips, Bob Johnson, later head of Ford's engine automation division, mentioned that their former colleague John Paivinen had moved to [[General Instrument]] and taught himself semiconductor design.{{sfn|Interview|2014|loc=55:00}} Paivinen then formed [[MOS Technology]] in [[Valley Forge, Pennsylvania]] in 1969 with two other executives from General Instrument, Mort Jaffe and Don McLaughlin. [[Allen-Bradley]], a supplier of electronic components and industrial controls, acquired a majority interest in 1970.<ref>Bagnall (2010), p. 13.</ref> The company designed and fabricated custom ICs for customers and had developed a line of calculator chips.<ref name="MOS Technology ad Nov 1974">{{Cite journal |last=MOS Technology |title=The First Single Chip Scientific Calculator Arrays. |journal=Electronics |volume=47 |issue=23 |pages=90–91 |publisher=McGraw-Hill |date=November 14, 1974 |url=http://commons.wikimedia.org/wiki/File:MOS_Technology_Calculator_Chip_Ad_1974.jpg |access-date=June 4, 2012 |archive-date=January 10, 2014 |archive-url=https://web.archive.org/web/20140110192747/http://commons.wikimedia.org/wiki/File:MOS_Technology_Calculator_Chip_Ad_1974.jpg |url-status=live}}</ref>

After the Mostek efforts fell through, Peddle approached Paivinen, who "immediately got it".{{sfn|Interview|2014|loc=57:00}} On 19 August 1974, Chuck Peddle, Bill Mensch, Rod Orgill, Harry Bawcom, Ray Hirt, Terry Holdt, and Wil Mathys left Motorola to join MOS. Mike Janes joined later. Of the seventeen chip designers and layout people on the 6800 team, eight left. The goal of the team was to design and produce a low-cost microprocessor for embedded applications and to target as wide as possible a customer base. This would be possible only if the microprocessor was low cost, and the team set the price goal for volume purchases at {{US$|long=no|5}}.{{sfn|Interview|2014|loc=58:30}} Mensch later stated the goal was not the processor price itself, but to create a set of chips that could sell at {{US$|long=no|20}} to compete with the recently introduced [[Intel 4040]] that sold for {{US$|long=no|29}} in a similar complete chipset.<ref>{{cite magazine |magazine=IEEE Spectrum |url=https://spectrum.ieee.org/q-a-with-co-creator-of-the-6502-processor |title=Q&A With Co-Creator of the 6502 Processor |first=Stephen |last=Cass |date=16 September 2021 |access-date=20 September 2021 |archive-date=20 September 2021 |archive-url=https://web.archive.org/web/20210920212955/https://spectrum.ieee.org/q-a-with-co-creator-of-the-6502-processor |url-status=live}}</ref>

Chips are produced by printing multiple copies of the chip design on the surface of a [[wafer (electronics)|wafer]], a thin disk of highly pure silicon. Smaller chips can be printed in greater numbers on the same wafer, decreasing their relative price. Additionally, wafers always include some number of tiny physical defects that are scattered across the surface. Any chip printed in that location will fail and has to be discarded. Smaller chips mean any single copy is less likely to be printed on a defect. For both of these reasons, the cost of the final product is strongly dependent on the size of the chip design.<ref>{{cite web |url=https://www.anandtech.com/show/8223/an-introduction-to-semiconductor-physics-technology-and-industry/3 |website=Anandtech |title=An Introduction to Semiconductor Physics, Technology, and Industry |first=Joshua |last=Ho |date=9 October 2014 |access-date=24 February 2020 |archive-date=24 February 2020 |archive-url=https://web.archive.org/web/20200224143352/https://www.anandtech.com/show/8223/an-introduction-to-semiconductor-physics-technology-and-industry/3 |url-status=live}}</ref>

The original 6800 chips were intended to be {{Convert|180|×|180|mil|lk=in}}, but layout was completed at {{Convert|212|×|212|mil}}, or an area of {{val|29.0|u=mm2}}.<ref>Motorola 6800 Oral History (2008), p. 10.</ref> For the new design, the cost goal demanded a size goal of {{Convert|153|×|168|mil}}, or an area of {{val|16.6|u=mm2}}.{{sfn|Cushman|1975|p=40}} Several new techniques would be needed to hit this goal.

===Moving to NMOS===
Two significant advances arrived in the market just as the 6502 was being designed that provided significant cost reductions. The first was the move to [[depletion-load NMOS]]. The 6800 used an early [[NMOS logic|NMOS]] process, enhancement mode, that required three supply voltages. One of the 6800's headlining features was an onboard [[voltage doubler]] that allowed a single +5&nbsp;V supply be used for +5, −5 and +12&nbsp;V internally, as opposed to other chips of the era like the [[Intel 8080]] that required three separate supply pins.<ref>{{cite web |url=http://www.cpu-world.com/info/Pinouts/8080.html |website=CPU World |title=8080A microprocessor – DIP 40 package |access-date=2020-02-24 |archive-date=2020-09-15 |archive-url=https://web.archive.org/web/20200915164812/http://www.cpu-world.com/info/Pinouts/8080.html |url-status=live}}</ref> While this feature reduced the complexity of the power supply and pin layout, it still required separate power line to the various gates on the chip, driving up complexity and size. By moving to the new depletion-load design, a single +5&nbsp;V supply was all that was needed, eliminating all of this complexity.{{sfn|Cushman|1975|p=38}}

A further advantage was that depletion-load designs used less power while switching, thus running cooler and allowing higher operating speeds. Another practical offshoot is that the clock signal for earlier CPUs had to be strong enough to survive all the dissipation as it traveled through the circuits, which almost always required a separate external chip that could supply a powerful signal. With the reduced power requirements of depletion-load design, the clock could be moved onto the chip, simplifying the overall computer design. These changes greatly reduced complexity and the cost of implementing a complete system.{{sfn|Cushman|1975|p=38}}

A wider change taking place in the industry was the introduction of [[projection mask]]ing. Previously, chips were patterned onto the surface of the wafer by placing a [[photomask|mask]] on the surface of the wafer and then shining a bright light on it. The masks often picked up tiny bits of dirt or [[photoresist]] as they were lifted off the chip, causing flaws in those locations on any subsequent masking. With complex designs like CPUs, 5 or 6 such masking steps would be used, and the chance that at least one of these steps would introduce a flaw was very high. In most cases, 90% of such designs were flawed, resulting in a 10% yield. The price of the working examples had to cover the production cost of the 90% that were thrown away.<ref name=milestone>{{cite web |url=https://spectrum.ieee.org/moores-law-milestones |title=Moore's Law Milestones |website=IEEE |date=30 April 2015 |access-date=2020-02-24 |archive-date=2020-02-24 |archive-url=https://web.archive.org/web/20200224213400/https://spectrum.ieee.org/tech-history/silicon-revolution/moores-law-milestones |url-status=live}}</ref>

In 1973, [[Perkin-Elmer]] introduced the [[Micralign]] system, which projected an image of the mask on the wafer instead of requiring direct contact. Masks no longer picked up dirt from the wafers and lasted on the order of 100,000 uses rather than 10. This eliminated step-to-step failures and the high flaw rates formerly seen on complex designs. Yields on CPUs immediately jumped from 10% to 60 or 70%. This meant the price of the CPU declined roughly the same amount and the microprocessor suddenly became a commodity device.<ref name=milestone/>

MOS Technology's existing fabrication lines were based on the older [[PMOS logic|PMOS]] technology, they had not yet begun to work with [[NMOS logic|NMOS]] when the team arrived. Paivinen promised to have an NMOS line up and running in time to begin the production of the new CPU. He delivered on the promise, the new line was ready by June 1975.<ref>Bagnall (2010), p. 19: "Paivinen promised Peddle he would have the n-channel process ready. He was true to his word."</ref>

===Design notes===
Chuck Peddle, Rod Orgill, and Wil Mathys designed the initial architecture of the new processors. A September 1975 article in ''[[EDN (magazine)|EDN]]'' magazine gives this summary of the design:{{sfn|Cushman|1975|p=36}}
<blockquote>
The MOS Technology 650X family represents a conscious attempt of eight former Motorola employees who worked on the development of the 6800 system to put out a part that would replace and outperform the 6800, yet undersell it. With the benefit of hindsight gained on the 6800 project, the MOS Technology team headed by Chuck Peddle, made the following architectural changes in the Motorola CPU…
</blockquote>

The main change in terms of chip size was the elimination of the [[tri-state driver]]s from the address bus outputs. A three-state bus has states for ''1'', ''0'' and ''high impedance''. The last state is used to allow other devices to access the bus, and is typically used for [[multiprocessing]], or more commonly in these roles, for [[direct memory access]] (DMA). While useful, this feature is expensive in terms of on-chip circuitry. The 6502 simply removed this feature, in keeping with its design as an inexpensive controller being used for specific tasks and communicating with simple devices. Peddle suggested that anyone who required this style of access could implement it with a [[Multiplexer#List of ICs which provide multiplexing|74158]].{{sfn|Cushman|1975|p=41}}{{efn|One example of such a design was the [[Atari 8-bit computers]], which use DMA to share memory between the 6502 and the ANTIC video chip. This was implemented with a single flip-flop, which was later built into custom ''Sally'' versions of the 6502 used in these machines. The flip flop enabled a pair of 74LS244 bus drivers that could isolate the 6502's address bus when DMA was required.<ref>{{cite book |title=Games vs. Hardware. The History of PC video games: The 80's |first=John |last=Purcaru |date=2014 |page=317}}</ref>}}

The next major difference was to simplify the registers. To start with, one of the two [[Accumulator (computing)|accumulators]] was removed. General-purpose registers like accumulators have to be accessed by many parts of the instruction decoder, and thus require significant amounts of wiring to move data to and from their storage. Two accumulators makes many coding tasks easier but costs the chip design itself significant complexity.{{sfn|Cushman|1975|p=36}} Further savings were made by reducing the [[stack register]] from 16 to 8 bits, meaning that the stack could only be 256 bytes long, which was enough for its intended role as a microcontroller.{{sfn|Cushman|1975|p=36}}{{failed verification|date=January 2023}}

The 16-bit IX [[index register]] was split in two, becoming X and Y. More importantly, the style of access changed. In the 6800, IX held a 16-bit address which was offset by an 8-bit number stored with the instruction and added to the address. In the 6502 (and most other contemporary designs), the 16-bit base address was stored in the instruction, and the 8-bit X or Y was added to it.{{sfn|Cushman|1975|p=41}}

Finally, the instruction set was simplified, simplifying the decoder and control logic. Of the original 72 instructions in the 6800, 56 were implemented. Among those removed were instructions that operated between the 6800's two accumulators, and several branch instructions inspired by the [[PDP-11]].{{sfn|Cushman|1975|p=41}}

The chip's high-level design had to be turned into drawings of transistors and interconnects. At MOS Technology, the layout was a very manual process done with colored pencils and [[vellum paper]]. The layout consisted of thousands of polygon shapes on six different drawings; one for each layer of the fabrication process. Given the size limits, the entire chip design had to be constantly considered. Mensch and Paivinen worked on the [[instruction decoder]]{{sfn|Interview|2014|loc=1:01:00}} while Mensch, Peddle and Orgill worked on the ALU and registers. A further advance, developed at a party, was a way to share some of the internal wiring to allow the ALU to be reduced in size.{{sfn|Interview|2014|loc=1:02:00}}

Despite their best efforts, the final design ended up being larger than the original target. The first 6502 chips were {{convert|168|×|183|mil}}, for an area of {{val|19.8|u=mm2}}. The original version of the processor had no rotate right (ROR) capability, so the instruction was omitted from the original documentation. The next iteration of the design shrank the chip and added the rotate right capability, and ROR was included in revised documentation.<ref name="ROR">[[:File:MCS650x Instruction Set.jpg]]</ref>{{efn|Since the OP code still did something in the original version of the processor, just not a correct ROR instruction, this caused a persistent myth that the original 6502 had a bug in its ROR instruction.<ref>{{Cite web|url=https://www.pagetable.com/?p=406|title=Measuring the ROR Bug in the Early MOS 6502 – pagetable.com|access-date=2023-02-25|archive-date=2023-03-21|archive-url=https://web.archive.org/web/20230321144032/https://www.pagetable.com/?p=406|url-status=live}}</ref><ref>{{cite web | url=https://www.applefritter.com/content/how-test-ceramic-6502-ror-bug | title=How to test a ceramic 6502 for the ROR bug? &#124; Applefritter | access-date=2023-02-25 | archive-date=2023-02-25 | archive-url=https://web.archive.org/web/20230225154458/https://www.applefritter.com/content/how-test-ceramic-6502-ror-bug | url-status=live }}</ref><ref>{{cite web | url=https://www.youtube.com/watch?v=Uk_QC1eU0Fg | title=The 6502 Rotate Right Myth | website=[[YouTube]] | access-date=2023-02-25 | archive-date=2023-02-25 | archive-url=https://web.archive.org/web/20230225154447/https://www.youtube.com/watch?v=Uk_QC1eU0Fg | url-status=live }}</ref>}}

===Introducing the 6501 and 6502===
[[File:MOS 6501 6502 Ad Sept 1975.jpg|thumb|Introductory advertisement for the MOS Technology MCS6501 and MCS6502 microprocessors]]

MOS would introduce two microprocessors based on the same underlying design: the 6501 would plug into the same socket as the Motorola 6800, while the 6502 re-arranged the pinout to support an on-chip clock oscillator. Both would work with other support chips designed for the 6800. They would not run 6800 software because they had a different instruction set, different registers, and mostly different addressing modes.<ref name="Mensch interview" /> Rod Orgill was responsible for the 6501 design; he had assisted John Buchanan at Motorola on the 6800. Bill Mensch did the 6502; he was the designer of the 6820 PIA at Motorola. Harry Bawcom, Mike Janes and Sydney-Anne Holt helped with the layout.

MOS Technology's microprocessor introduction was different from the traditional months-long product launch. The first run of a new integrated circuit is normally used for internal testing and shared with select customers as [[engineering sample]]s. These chips often have minor design defects that will be corrected before production begins. Chuck Peddle's goal was to sell the first run 6501 and 6502 chips to the attendees at the [[Western Electronics Show and Convention|WESCON]] trade show in San Francisco beginning on September 16, 1975. Peddle was a very effective spokesman and the MOS Technology microprocessors were extensively covered in the trade press. One of the earliest was a full-page story on the MCS6501 and MCS6502 microprocessors in the July 24, 1975 issue of ''Electronics'' magazine.<ref name="Electronics July 24, 1975">{{Cite journal |title=Microprocessor line offers 4, 8, 16 bits |journal=Electronics |volume=48 |issue=15 |page=118 |publisher=McGraw-Hill |location=New York |date=July 24, 1975}} The article covers the 6501 and 6502 plus the 28-pin versions that would only address 4K of memory. It also covered future devices such as "a design that Peddle calls a pseudo 16".</ref> Stories also ran in ''[[EE Times]]'' (August 24, 1975),<ref name="6502 EE Times 1975">{{Cite journal |last=Sugarman |first=Robert |title=Does the Country Need A Good {{US$|long=no|20}} Microprocessor? |journal=EE Times |page=25 |publisher=CMP Publications |location=Manhasset, New York |date=25 August 1975 |url=http://www.commodore.ca/gallery/magazines/misc/mos_605x_team_eetimes_august_1975.pdf |access-date=5 February 2008 |archive-url=https://web.archive.org/web/20070203105724/http://www.commodore.ca/gallery/magazines/misc/mos_605x_team_eetimes_august_1975.pdf |archive-date=3 February 2007 |url-status=dead}}</ref> ''EDN'' (September 20, 1975), ''Electronic News'' (November 3, 1975), ''Byte'' (November 1975)<ref name="Byte Nov 1975 6502">{{Cite journal |last=Fylstra |first=Daniel |author-link=Dan Fylstra |title=Son of Motorola (or the {{US$|long=no|20}} CPU Chip) |journal=Byte |volume=1 |issue=3 |pages=56–62 |publisher=Green Publishing |location=Peterborough, NH |date=November 1975}} Comparison of the 6502 and the 6800 microprocessors. Author visited MOS Technology in August 1975.</ref> and ''Microcomputer Digest'' (November 1975).<ref name="3rd Gen Micro">{{cite journal |title=3rd Generation Microprocessor |journal=Microcomputer Digest |volume=2 |issue=2 |pages=1–3 |publisher=[[Microcomputer Associates, Incorporated|Microcomputer Associates]] |location=Cupertino, CA |date=August 1975 |url=http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n02_Aug75.pdf |access-date=2009-11-27 |archive-date=2009-07-04 |archive-url=https://web.archive.org/web/20090704150052/http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v02n02_Aug75.pdf |url-status=dead}}</ref> Advertisements for the 6501 appeared in several publications the first week of August 1975. The 6501 would be for sale at WESCON for {{US$|long=no|20}} each.<ref name="Electronics Aug 7 1975">{{Cite journal |title=MOS 6501 Microprocessor beats 'em all |journal=Electronics |volume=48 |issue=16 |pages=60–61 |publisher=McGraw-Hill |location=New York |date=August 7, 1975}}</ref> In September 1975, the advertisements included both the 6501 and the 6502 microprocessors. The 6502 would cost only {{US$|long=no|25}} ({{Inflation|US|25|1975|fmt=eq|r=0}}).<ref name="6502 Computer Sep 1975">{{Cite journal |title=MOS 6502 the second of a low cost high performance microprocessor family |journal=Computer |volume=8 |issue=9 |pages=38–39 |publisher=IEEE Computer Society |date=September 1975 |url=http://commons.wikimedia.org/wiki/File:MOS_6501_6502_Ad_Sept_1975.jpg |doi=10.1109/C-M.1975.219074 |access-date=2012-06-04 |archive-date=2021-02-24 |archive-url=https://web.archive.org/web/20210224154043/https://commons.wikimedia.org/wiki/File:MOS_6501_6502_Ad_Sept_1975.jpg |url-status=live|url-access=subscription }}</ref>

When MOS Technology arrived at Wescon, they found that exhibitors were not permitted to sell anything on the show floor. They rented the MacArthur Suite at the [[Westin St. Francis|St. Francis Hotel]] and directed customers there to purchase the processors. At the suite, the processors were stored in large jars to imply that the chips were in production and readily available. The customers did not know the bottom half of each jar contained non-functional chips.<ref>Bagnall (2010), pp. 33–35.</ref> The chips were {{US$|long=no|20}} and {{US$|long=no|25}} while the documentation package was an additional {{US$|long=no|10}}. Users were encouraged to make [[photocopies]] of the documents, an inexpensive way for MOS Technology to distribute product information. The preliminary data sheets listed just 55 instructions and excluded the Rotate Right (ROR) instruction, which was not supported on these early chips. The reviews in ''Byte'' and ''EDN'' noted the lack of the ROR instruction. The next revision of the layout fixed this problem and the May 1976 datasheet listed 56 instructions. Peddle wanted every interested engineer and hobbyist to have access to the chips and documentation, whereas other semiconductor companies only wanted to deal with "serious" customers. For example, [[Signetics]] was introducing the [[Signetics 2650|2650]] microprocessor and its advertisements asked readers to write for information on their company letterhead.<ref name="Signetics 2650 Oct 1975">{{Cite journal |last=Signetics |title=Easiest-to-use microprocessor |journal=Electronics |volume=48 |issue=22 |pages=114–115 |publisher=McGraw-Hill |date=October 30, 1975 |url=https://commons.wikimedia.org/wiki/File:Signetics_2650_microprocessor_October_1975.jpg |access-date=November 20, 2015 |archive-date=November 20, 2015 |archive-url=https://web.archive.org/web/20151120204902/https://commons.wikimedia.org/wiki/File:Signetics_2650_microprocessor_October_1975.jpg |url-status=live}}</ref><!--[[User:Kvng/RTH]]-->

===Motorola lawsuit===
[[File:MCS6500 Datasheet May 1976 cover.jpg|thumb|upright|The May 1976 datasheet omitted the 6501 microprocessor that was in the [[:File:MCS650X Datasheet Aug 1975 cover.jpg|August 1975]] version.]]
The 6501/6502 introduction in print and at Wescon was an enormous success. The downside was that the extensive press coverage got Motorola's attention. In October 1975, Motorola reduced the price of a single 6800 microprocessor from {{US$|long=no|175}} to {{US$|long=no|69}}. The {{US$|long=no|300}} system design kit was reduced to {{US$|long=no|150}} and it now came with a printed circuit board.<ref name="MC6800 price reduction">{{Cite journal |last=Motorola |title=All this and unbundled {{US$|long=no|69}} microprocessor |journal=Electronics |volume=48 |issue=22 |page=11 |publisher=McGraw-Hill |date=October 30, 1975 |url=http://commons.wikimedia.org/wiki/File:Motorola_MC6800_microprocessor_ad_1975.jpg |access-date=August 8, 2010 |archive-date=December 15, 2011 |archive-url=https://web.archive.org/web/20111215093452/http://commons.wikimedia.org/wiki/File:Motorola_MC6800_microprocessor_ad_1975.jpg |url-status=live}} The quantity one price for the MC6800 was reduced from {{US$|long=no|175}} to {{US$|long=no|69}}. The previous price for 50 to 99 units was {{US$|long=no|125}}.</ref> On November 3, 1975, Motorola sought an injunction in Federal Court to stop MOS Technology from making and selling microprocessor products. They also filed a lawsuit claiming patent infringement and misappropriation of trade secrets. Motorola claimed that seven former employees joined MOS Technology to create that company's microprocessor products.<ref name="Electronics Nov 13 1975 2">{{Cite journal |last=Waller |first=Larry |title=News briefs: Motorola seeks to stop microprocessor foe |journal=Electronics |volume=48 |issue=23 |page=38 |publisher=McGraw-Hill |location=New York |date=November 13, 1975}}"Motorola said last week it would seek an immediate injunction to stop MOS Technology Inc., Norristown, Pa., from making and selling microprocessor products, including its MCS6500." (This issue was published on November 7.)</ref>

Motorola was a billion-dollar company with a plausible case and expensive lawyers. On October 30, 1974, Motorola had filed numerous patent applications on the microprocessor family and was granted twenty-five patents. The first was in June 1976 and the second was to Bill Mensch on July 6, 1976, for the 6820 PIA chip layout. These patents covered the 6800 bus and how the peripheral chips interfaced with the microprocessor.<ref>Motorola was awarded the following US Patents on the 6800 microprocessor family: 3962682, 3968478, 3975712, 3979730, 3979732, 3987418, 4003028, 4004281, 4004283, 4006457, 4010448, 4016546, 4020472, 4030079, 4032896, 4037204, 4040035, 4069510, 4071887, 4086627, 4087855, 4090236, 4145751, 4218740, 4263650.</ref> Motorola began making transistors in 1950 and had a portfolio of semiconductor patents. Allen-Bradley decided not to fight this case and sold their interest in MOS Technology back to the founders. Four of the former Motorola engineers were named in the suit: Chuck Peddle, Will Mathys, Bill Mensch and Rod Orgill. All were named inventors in the 6800 patent applications. During the discovery process, Motorola found that one engineer, Mike Janes, had ignored Peddle's instructions and brought his 6800 design documents to MOS Technology.<ref>Bagnall (2010), p. 53–54. "He [Mike Janes] had all his original work from the 6800 and hid it from Motorola…</ref> In March 1976, the now independent MOS Technology was running out of money and had to settle the case. They agreed to drop the 6501 processor, pay Motorola {{US$|long=no|200}},000 and return the documents that Motorola contended were confidential. Both companies agreed to [[Cross-licensing|cross-license]] microprocessor patents.<ref name="Electronics April 1, 1976">{{Cite journal |title=Motorola, MOS Technology settle patent suit |journal=Electronics |volume=49 |issue=7 |page=39 |publisher=McGraw-Hill |location=New York |date=April 1, 1975}} "MOS Technology Inc. of Norristown, Pa. has agreed to withdraw its MCS6501 microprocessor from the market and to pay Motorola Inc. {{US$|long=no|200000}} ..." "MOS Technology and eight former Motorola employees have given back, under court order documents that Motorola contends are confidential." "…both companies have agreed to a cross license relating to patents in the microprocessor field."</ref> That May, Motorola dropped the price of a single 6800 microprocessor to {{US$|long=no|35}}. By November, [[Commodore International|Commodore]] had acquired MOS Technology.<ref>Bagnall (2010), pp. 55-56</ref><ref name="Mini-Micro Nov 1976">{{cite journal |title=Mergers and Acquisitions |journal=Mini-Micro Systems |volume=9 |issue=11 |page=19 |publisher=Cahners |date=November 1976}}" Commodore International … is buying MOS Technology (Norristown, PA). This saves the six-year-old semiconductor house from impending disaster."</ref>

===Computers and games===
With legal troubles behind them, MOS was still left with the problem of getting developers to try their processor, prompting Chuck Peddle to design the MDT-650 ("microcomputer development terminal") [[single-board computer]]. Another group inside the company designed the [[KIM-1]], which was sold semi-complete and could be turned into a usable system with the addition of a 3rd party [[computer terminal]] and [[compact cassette]] drive. While it sold well to its intended market, the company found the KIM-1 also sold well to hobbyists and tinkerers. The related Rockwell [[AIM-65]] control, training, and development system also did well. The software in the AIM 65 was based on that in the MDT. Another roughly similar product was the Synertek [[SYM-1]].

One of the first "public" uses for the design was the [[Apple I]] [[microcomputer]], introduced in 1976. The 6502 was next used in the [[Commodore PET]] and [[Apple II]],<ref name="zdnet wouldbe">{{cite news |url=http://www.zdnet.co.uk/news/infrastructure/2010/12/04/intels-victims-eight-would-be-giant-killers-40091045/6/ |archive-url=https://archive.today/20130505145002/http://www.zdnet.co.uk/news/infrastructure/2010/12/04/intels-victims-eight-would-be-giant-killers-40091045/6/ |url-status=dead |archive-date=May 5, 2013 |title=Intel's victims: Eight would-be giant killers |work=[[ZDNet]] |date=December 4, 2010 |access-date=March 7, 2012 |author=Goodwins, Rupert}}</ref> both released in 1977. It was later used in the [[Atari 8-bit computers]], [[Acorn Atom]], [[BBC Micro]],<ref name="zdnet wouldbe"/> [[VIC-20]] and other designs both for home computers and business, such as [[Ohio Scientific]] and [[Oric computers]]. The [[MOS Technology 6510|6510]], a direct successor of the 6502 with a digital I/O port and a [[Tri-state buffer|tri-state]] address bus, was the [[Central processing unit|CPU]] utilized in the best-selling<ref name="Reimer1">{{cite web
|url=http://www.jeremyreimer.com/total_share.html
|title=Personal Computer Market Share: 1975-2004
|last=Reimer
|first=Jeremy
|access-date=2009-07-17
|archive-url=https://web.archive.org/web/20120606052317/http://jeremyreimer.com/postman/node/329
|archive-date=6 June 2012
}}</ref><ref name="PageTable">{{cite web|url=http://www.pagetable.com/?p=547 |title=How many Commodore 64 computers were sold? |access-date=2011-02-01 |url-status=dead |archive-url=https://web.archive.org/web/20160306232450/http://www.pagetable.com/?p=547 |archive-date=2016-03-06}}</ref> [[Commodore 64]] home computer.

Another important use of the 6500 family was in video games. The first to make use of the processor design was the 1977 Atari VCS, later renamed the [[Atari 2600]]. The VCS used a 6502 variant named the [[MOS Technology 6507|6507]], which had fewer pins, so it could address only 8&nbsp;[[kilobyte|KB]] of memory. Millions of the Atari consoles would be sold, each with a MOS processor. Another significant use was by the [[Nintendo Entertainment System]] and Famicom. The 6502 used in the NES was a [[second source]] version by [[Ricoh]], a partial [[system on a chip]], that lacked the [[binary-coded decimal]] mode but added 22 memory-mapped registers and on-die hardware for sound generation, joypad reading, and [[Sprite (computer graphics)|sprite]] list [[Direct memory access|DMA]]. Called [[Ricoh 2A03|2A03]] in [[NTSC]] consoles and [[2A07]] in [[PAL]] consoles (the difference being the [[Frequency divider#Digital|clock frequency divider]] ratio and a lookup table for audio sample rates), this processor was produced exclusively for [[Nintendo]].

6502 or variants were used in all of Commodore's [[floppy disk]] [[disk drive|drives]] for all of their 8-bit computers, from the PET line through the Commodore 128D, including the Commodore 64. 8-inch PET drives had two 6502 processors. Atari used the same 6507 used in the Atari VCS for its [[Atari 810|810]] and [[Atari 1050|1050]] disk drives used for all of their 8-bit computer line, from the 400/800 through the XEGS.

In the 1980s, a popular electronics magazine Elektor/Elektuur used the processor in its microprocessor development board [[Elektor Junior Computer|Junior Computer]].

The CMOS successor to the 6502, the [[WDC 65C02]], also saw use in home computers and video game consoles. Apple used it in the Apple II line starting with the [[Apple IIc]] and later variants of the [[Apple IIe]] and also offered a kit to upgrade older IIe systems with the new processor.<ref>{{Cite web |title=Apple IIe Enhancement Kit - Peripheral - Computing History |url=https://www.computinghistory.org.uk/det/54659/Apple-IIe-Enhancement-Kit/ |access-date=2023-10-23 |website=www.computinghistory.org.uk |archive-date=2020-08-08 |archive-url=https://web.archive.org/web/20200808233600/http://www.computinghistory.org.uk/det/54659/Apple-IIe-Enhancement-Kit/ |url-status=live }}</ref> The [[Hudson Soft HuC6280]] chip used in the [[TurboGrafx-16]] was based on a 65C02 core. The [[Atari Lynx]] used a custom chip named "Mikey"<ref>{{Cite web |title=4. CPU/ROM |url=https://www.monlynx.de/lynx/lynx4.html |access-date=2023-10-23 |website=www.monlynx.de |archive-date=2023-09-20 |archive-url=https://web.archive.org/web/20230920125949/http://www.monlynx.de/lynx/lynx4.html |url-status=live }}</ref> designed by [[Epyx]] which included a VLSI VL65NC02 licensed cell. The G65SC12 by [[GTE Microcircuits]] (renamed California Micro Devices) variant was used in the [[BBC Master]]. Some models of the BBC Master also included an additional G65SC102 co-processor.

<gallery class="center" caption="Home computers and video game consoles using the 6502 or its variants">
File:Acorn atom zx1.jpg|[[Acorn Atom]]
File:Acorn Electron 4x3.jpg|[[Acorn Electron]]
File:CopsonApple1 2k cropped.jpg|[[Apple I]]
File:Apple II tranparent 800.png|[[Apple II]]
File:Apple IIe.jpg|[[Apple IIe]]
File:Atari-2600-Console.jpg|[[Atari 2600]]
File:Atari-5200-4-Port-wController-L.jpg|[[Atari 5200]]
File:Atari-7800-Console-Set.jpg|[[Atari 7800]]
File:Atari-800-Computer-FL.jpg|[[Atari 8-bit computers|Atari 800]]
File:Atari-Lynx-I-Handheld.jpg|[[Atari Lynx]]
File:Acorn BBC Master Series.jpg|[[BBC Master]]
File:STM Systems Baby! 1 computer.jpg|[[Baby! 1]]
File:BBC Micro Front Restored.jpg|[[BBC Micro]]
File:Commodore 2001 Series-IMG 0448b.jpg|[[Commodore PET]]
File:Commodore-VIC-20-FL.jpg|[[VIC-20|Commodore VIC-20]]
File:Commodore-64-Computer-FL.jpg|[[Commodore 64]]
File:Commodore-128.jpg|[[Commodore 128]]
File:Nintendo-Famicom-Console-Set-FL.jpg|[[Nintendo Entertainment System|Family Computer (Famicom)]]
File:NES-Console-Set.jpg|[[Nintendo Entertainment System]]
File:OSI Challenger 4P.jpg|[[Ohio Scientific|Ohio Scientific Challenger 4P]]
File:Orao-IMG 7278.jpg|[[Orao (computer)|Orao]]
File:Oric1.jpg|[[Oric-1]]
File:Oric Atmos 01a.jpg|[[Oric Atmos]]
File:TurboGrafx16-Console-Set.jpg|[[TurboGrafx-16]]
</gallery>

==Technical description==
[[Image:MOS 6502 die.jpg|right|thumb|6502 processor die. The regular section at the top is the instruction decoding ROM, the seemingly random section in the center is the control logic, and at the bottom are the registers (right) and the ALU (left). The data bus connections are along the lower right, and the address bus along the bottom and lower left.{{sfn|Cushman|1975|p=40}}]]
[[Image:MOS6502.svg|right|thumb|215px|6502 pin configuration (40-pin [[Dual in-line package|DIP]])]]
<div class="floatright" style="border: 1px solid #a2a9b1;background-color: #f8f9fa;padding:0.2em;font-size:88%">
{{center|'''MOS 6502 registers'''}}
{| style="font-size:88%;border-spacing: 1px;"
|- style="text-align:center;"
| style="width:10px"| <sup>1</sup><sub>5</sub>
| style="width:10px"| <sup>1</sup><sub>4</sub>
| style="width:10px"| <sup>1</sup><sub>3</sub>
| style="width:10px"| <sup>1</sup><sub>2</sub>
| style="width:10px"| <sup>1</sup><sub>1</sub>
| style="width:10px"| <sup>1</sup><sub>0</sub>
| style="width:10px"| <sub>9</sub>
| style="width:10px"| <sub>8</sub>
| style="width:10px"| <sub>7</sub>
| style="width:10px"| <sub>6</sub>
| style="width:10px"| <sub>5</sub>
| style="width:10px"| <sub>4</sub>
| style="width:10px"| <sub>3</sub>
| style="width:10px"| <sub>2</sub>
| style="width:10px"| <sub>1</sub>
| style="width:10px"| <sub>0</sub>
| style="width:auto;" | ''(bit position)''
|-
|colspan="17" | '''Main registers'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="8"| &nbsp;
| style="text-align:center;" colspan="8"| A
| style="width:auto; background:white; color:black;"| [[Accumulator (computing)|'''A'''ccumulator]]
|- 
|colspan="17" | '''[[Index registers]]'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="8"| &nbsp;
| style="text-align:center;" colspan="8"| X
| style="background:white; color:black;"| '''X''' index
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="8"| &nbsp;
| style="text-align:center;" colspan="8"| Y
| style="background:white; color:black;"| '''Y''' index
|- style="background:silver;color:black"
| style="text-align:center; background:#DDDDDD"| 0
| style="text-align:center; background:#DDDDDD"| 0
| style="text-align:center; background:#DDDDDD"| 0
| style="text-align:center; background:#DDDDDD"| 0
| style="text-align:center; background:#DDDDDD"| 0
| style="text-align:center; background:#DDDDDD"| 0
| style="text-align:center; background:#DDDDDD"| 0
| style="text-align:center; background:#DDDDDD"| 1
| style="text-align:center;" colspan="8"| S
| style="background:white; color:black;"| [[Stack pointer|'''S'''tack pointer]]
|-
|colspan="17" | '''[[Program counter]]'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| PC
| style="background:white; color:black;"| [[Program counter|'''P'''rogram '''C'''ounter]]
|-
|colspan="17" | '''[[Status register]]'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="8" | 
| style="text-align:center;"| [[Sign flag|N]]
| style="text-align:center;"| [[Overflow flag|V]]
| style="text-align:center;"| -
| style="text-align:center;"| [[#BRK Flag|B]]
| style="text-align:center;"| [[Binary-coded decimal|D]]
| style="text-align:center;"| [[Interrupt flag|I]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" |[[Status register|'''P'''rocessor flags]]
|} 
</div>

The 6502 is a [[little-endian]] [[8-bit computing|8-bit]] processor with a [[16-bit computing|16-bit]] [[address bus]]. The original versions were fabricated using an {{nowrap|8 µm}}<ref name="Corder 1999">{{cite web |last=Corder |first=Mike |title=Big Things in Small Packages |work=Pioneers' Progress with picoJava Technology |publisher=Sun Microelectronics |date=Spring 1999 |url=http://www.sun.com/microelectronics/picoJava/pioneers/vol3/licensee-jCan.html |url-status=dead |archive-url=https://web.archive.org/web/20060312110759/http://www.sun.com/microelectronics/picoJava/pioneers/vol3/licensee-jCan.html |archive-date=2006-03-12 |quote=The first 6502 was fabricated with 8 micron technology, ran at one megahertz and had a maximum memory of 64k.| access-date=April 23, 2012}}</ref> process technology chip with a [[Die (integrated circuit)|die size]] of {{Convert|153|×|168|mil|abbr=on|order=flip}}, for a total area of {{val|16.6|u=mm2}}.{{sfn|Cushman|1975|p=40}}

The internal logic runs at the same speed as the external clock rate. It featured a simple pipeline; on each cycle, the processor fetches one byte from memory and processes another. This means that any single instruction can take as few as two cycles to complete, depending on the number of operands that instruction uses. For comparison, the [[Zilog Z80]] required two cycles to fetch memory, and the minimum instruction time was four cycles. Thus, despite the lower clock speeds compared to competing designs, typically in the neighborhood of 1 to {{val|2|ul=MHz}}, the 6502's performance was competitive with CPUs using significantly faster clocks. This is partly due to a simple state machine implemented by [[Combinational logic|combinational (clockless) logic]] to a greater extent than in many other designs; the two-phase clock (supplying two synchronizations per cycle) could thereby control the machine cycle directly.

This design also led to one useful design note of the 6502, and the 6800 before it. Because the chip only accessed memory during a certain part of the clock cycle, and this duration was indicated by the φ2-low clock-out pin, other chips in a system could access memory during those times when the 6502 was off the bus. This was sometimes known as "hidden access". This technique was widely used by computer systems; they would use memory capable of access at 2&nbsp;MHz, and then run the CPU at 1&nbsp;MHz. This guaranteed that the CPU and video hardware could interleave their accesses, with a total performance matching that of the memory device. Because this access was every other cycle, there was no need to signal the CPU to avoid using the bus, making this sort of access easy to implement without any bus logic.
<ref>{{cite web |url=https://retrocomputing.stackexchange.com/questions/12718/how-to-implement-bus-sharing-dma-on-a-6502-system |title=How to implement bus sharing / DMA on a 6502 system |access-date=2020-09-30 |archive-date=2020-08-15 |archive-url=https://web.archive.org/web/20200815134410/https://retrocomputing.stackexchange.com/questions/12718/how-to-implement-bus-sharing-dma-on-a-6502-system |url-status=live}}</ref> When faster memories became available in the 1980s, newer machines could use this same technique while running at higher clock rates, the [[BBC Micro]] used newer RAM that allowed its CPU to run at 2&nbsp;MHz while still using the same bus sharing techniques.

Like most simple CPUs of the era, the dynamic [[NMOS logic|NMOS]] 6502 chip is not sequenced by [[microcode]] but decoded directly using a dedicated [[Programmable logic array|PLA]]. The decoder occupied about 15% of the chip area. This compares to later microcode-based designs like the [[Motorola 68000]], where the microcode ROM and decoder engine represented about a third of the gates in the system.

===Registers===
Like its precursor, the 6800, the 6502 has very few [[processor register|registers]]. They include<ref>{{Cite book |title=MOS MICROCOMPUTERS PROGRAMMING MANUAL |date=January 1976 |publisher=MOS TECHNOLOGY, INC. |chapter=PROGRAMMING MODEL MCS650X}}</ref>

* <code>A</code> = 8-bit [[accumulator (computing)|accumulator]] register
* <code>P</code> = 7-bit<ref>{{cite book |last=Anderson |first=J.S. |date=2012-08-21 |title=Microprocessor Technology |url=https://books.google.com/books?id=VKjkUsCV4moC&pg=PA153 |publisher=[[Routledge]] |page=153 |isbn=9781136078057}}</ref> processor [[status register]]
** <code>n</code> = [[Negative flag|Negative]]
** <code>v</code> = [[Overflow flag|Overflow]]
** <code>b</code> = Break (only in stack values, not in hardware<ref>{{Cite web |title=Status flags |url=https://www.nesdev.org/wiki/Status_flags |access-date=2024-06-11 |website=NESdev Wiki |language=en}}</ref>)
** <code>d</code> = [[Binary-coded decimal|Decimal]]
** <code>i</code> = [[Interrupt]] disable
** <code>z</code> = [[Zero flag|Zero]]
** <code>c</code> = [[Carry flag|Carry]]
* <code>PC</code> = 16-bit [[program counter]]
* <code>S</code> = 8-bit [[stack (abstract data type)|stack pointer]]
* <code>X</code> = 8-bit [[index register]]
* <code>Y</code> = 8-bit index register

This compares to a contemporaneous competitor, the [[Intel 8080]], which likewise has one 8-bit accumulator and a 16-bit program counter, but has six more general-purpose 8-bit registers (which can be combined into three 16-bit pointers) and a larger 16-bit stack pointer.<ref>{{cite web |title=8080A/8080A-1/8080A-2 8-Bit N Channel Microprocessor |url=http://www.elektronikjk.com/technika_komputerowa/CPU/Intel_8080A.pdf |publisher=Intel |access-date=November 16, 2021 |archive-date=November 15, 2021 |archive-url=https://web.archive.org/web/20211115165927/http://www.elektronikjk.com/technika_komputerowa/CPU/Intel_8080A.pdf |url-status=live }}</ref>

In order to make up somewhat for the lack of registers, the 6502 includes a ''[[zero page]]'' addressing mode that uses one address byte in the instruction instead of the two needed to address the full {{val|64|u=KB}} of memory. This provides fast access to the first {{val|256|u=bytes}} of RAM by using shorter instructions. For instance, an instruction to add a value from memory to the value in the accumulator would normally be three bytes, one for the instruction and two for the 16-bit address. Using the zero page reduces this to an 8-bit address, reducing the total instruction length to two bytes, and thus improving instruction performance.

The stack address space is [[Wiktionary:Hardwired|hardwired]] to memory page <code>$01</code>, i.e. the address range <code>$0100</code>–<code>$01FF</code> (<code>256</code>–<code>511</code>). Software access to the stack is done via four implied addressing mode instructions, whose functions are to push or pop (pull) the accumulator or the processor status register. The same stack is also used for subroutine calls via the JSR (jump to subroutine) and RTS (return from subroutine) instructions and for [[interrupt]] handling.

===Addressing===
The chip uses the index and stack registers effectively with several [[addressing mode]]s, including a fast "direct page" or "zero page" mode, similar to that found on the [[PDP-8]], that accesses memory locations from addresses 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address){{mdash}}code for the 6502 uses the zero page much as code for other processors would use registers. On some 6502-based microcomputers with an operating system, the [[operating system]] uses most of zero page, leaving only a handful of locations for the user.

Addressing modes also include ''implied'' (1-byte instructions); ''absolute'' (3 bytes); ''indexed absolute'' (3 bytes); ''indexed zero-page'' (2 bytes); ''relative'' (2 bytes); ''accumulator'' (1); ''indirect,x'' and ''indirect,y'' (2); and ''immediate'' (2). Absolute mode is a general-purpose mode. Branch instructions use a signed 8-bit offset relative to the instruction after the branch; the numerical range −128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode operates on the accumulator register and does not need any [[operand]] data. Immediate mode uses an 8-bit [[literal (computer programming)|literal]] operand.

===Indirect addressing===
The indirect modes are useful for [[Array (data type)|array]] processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register is added to a 16-bit base address read from zero page, which is located by a single byte following the opcode. The Y register is therefore an ''index'' register in the sense that it is used to hold an actual ''index'' (as opposed to the X register in the 6800, where a base address was directly stored and to which an immediate offset could be added). Incrementing the index register to walk the array byte-wise takes only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation is found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acts as a set of up to 128 additional (though very slow) address registers.

The 6502 is capable of performing addition and subtraction in binary or [[binary-coded decimal]]. Placing the CPU into BCD mode with the <code>SED</code> (set D flag) instruction results in decimal arithmetic, in which <code>$99 + $01</code> would result in <var>$00</var> and the carry (C) flag being set. In binary mode (<code>CLD</code>, clear D flag), the same operation would result in <var>$9A</var> and the carry flag being cleared. Other than [[Atari BASIC]], BCD mode was seldom used in home-computer applications.

See the [[wikibooks:Computer Programming/Hello world#Accumulator + index register machine: MOS Technology 6502, CBM KERNEL, MOS assembler syntax|Hello world!]] article for a simple but characteristic example of 6502 [[assembly language]].

===Instructions and opcodes===
6502 instruction [[opcode|operation code]]s (''opcodes'') are 8&nbsp;bits long and have the general form AAABBBCC, where AAA and CC define the opcode, and BBB defines the addressing mode.<ref name=ii>{{cite web |url=http://nparker.llx.com/a2/opcodes.html |title=The 6502/65C02/65C816 Instruction Set Decoded |first=Neil |last=Parker |website=Neil Parker's Apple II page |access-date=2019-07-16 |archive-date=2019-07-16 |archive-url=https://web.archive.org/web/20190716023057/http://nparker.llx.com/a2/opcodes.html |url-status=live}}</ref> For example, the <code>ORA</code> instruction performs a bitwise OR on the bits in the accumulator with another value. The instruction opcode is of the form 000bbb01, where bbb may be 010 for an immediate mode value (constant), 001 for zero-page fixed address, 011 for an absolute address, and so on.<ref name=ii/> This pattern is not universal, as there are exceptions, but it allows opcode values to be easily converted to assembly mnemonics for the majority of instructions, handling the edge cases with special-purpose code.<ref name=ii/>

Of the 256 possible opcodes available using an 8-bit pattern, the original 6502 uses 151 of them, organized into 56 instructions with (possibly) multiple [[addressing mode]]s. Depending on the instruction and addressing mode, the opcode may require zero, one or two additional bytes for operands. Hence 6502 machine instructions vary in length from one to three bytes.<ref>[http://www.masswerk.at/6502/6502_instruction_set.html 6502 Instruction Set] {{Webarchive|url=https://web.archive.org/web/20180508053805/http://www.masswerk.at/6502/6502_instruction_set.html |date=2018-05-08}}.</ref><ref>[http://www.6502.org/tutorials/6502opcodes.html NMOS 6502 Opcodes]. {{Webarchive|url=https://web.archive.org/web/20160114001557/http://www.6502.org/tutorials/6502opcodes.html |date=2016-01-14}}.</ref> The operand is stored in the 6502's customary [[endianness|little-endian format]].

Each CPU machine instruction takes up a certain number of clock cycles, usually equal to the number of memory accesses. For example, the absolute indexing mode of the ORA instruction takes 4 clock cycles; 3 cycles to read the instruction and 1 cycle to read the value of the absolute address. If no memory is accessed, the number of clock cycles is two. The minimum clock cycles for any instruction is two. When using indexed addressing, if the result crosses a page boundary an extra clock cycle is added. Also, when a zero page address is used in indexing mode (e.g. zp,X) an extra clock cycle is added.

The [[WDC 65C816|65C816]], the 16-bit [[CMOS]] descendant of the 6502, also supports 24-bit addressing, which results in instructions being assembled with three-byte operands, also arranged in little-endian format.

The remaining 105 opcodes are undefined. In the original design, instructions where the low-order 4&nbsp;bits (''nibble'') were 3, 7, B or F were not used, providing room for future expansion. Likewise, the $x2 column had only a single entry, <code>LDX #''constant''</code>. The remaining 25 empty slots were distributed. Some of the empty slots were used in the 65C02 to provide both new instructions and variations on existing ones with new addressing modes. The $xF instructions were initially left free to allow 3rd-party vendors to add their own instructions, but later versions of the 65C02 standardized a set of [[bit manipulation]] instructions developed by [[Rockwell Semiconductor]].

===Assembly language===
A 6502 [[assembly language]] statement consists of a three-character instruction [[mnemonic]], followed by any [[operand]]s. Instructions that do not take a separate operand but target a single register based on the addressing mode combine the target register in the instruction mnemonic, so the assembler uses <code>INX</code> as opposed to <code>INC X</code> to increment the X register.

===Instruction table===
{| class="wikitable collapsible collapsed"
!colspan=13| Opcode matrix for the 6502 instruction set 
|-
|colspan=13| Addressing modes: {{font color||#e0e0e0|'''''A'''''}} – accumulator, {{font color||#99ff99|'''''#'''''}} – immediate, {{font color||#ffe0e0|'''''zpg'''''}} – zero page, {{font color||#e0ffff|'''''abs'''''}} – absolute, {{font color||#ffc299|'''''ind'''''}} – indirect, '''''X''''' – indexed by X register, '''''Y''''' – indexed by Y register, {{font color||#ffffe0|'''''rel'''''}} – relative
|-
!rowspan=2| High nibble ||colspan=12| Low nibble
|- 
! 0||  1||  2||  4||  5||  6||  8||  9||  A||  C||  D||  E
|- 
! 0
| bgcolor=#e0e0e0|BRK
| bgcolor=#ffc299|ORA (''ind'',X)
| 
| 
| bgcolor=#ffe0e0|ORA ''zpg''
| bgcolor=#ffe0e0|ASL ''zpg''
| bgcolor=#e0e0e0|PHP
| bgcolor=#99ff99|ORA #
| bgcolor=#e0e0e0|ASL A
| 
| bgcolor=#e0ffff|ORA ''abs''
| bgcolor=#e0ffff|ASL ''abs''
|- 
! 1
| bgcolor=#ffffe0|BPL ''rel''
| bgcolor=#ffc299|ORA (''ind''),Y
| 
| 
| bgcolor=#ffe0e0|ORA ''zpg'',X
| bgcolor=#ffe0e0|ASL ''zpg'',X
| bgcolor=#e0e0e0|CLC
| bgcolor=#e0ffff|ORA ''abs'',Y
| 
| 
| bgcolor=#e0ffff|ORA ''abs'',X
| bgcolor=#e0ffff|ASL ''abs'',X
|- 
! 2
| bgcolor=#e0ffff|JSR ''abs''
| bgcolor=#ffc299|AND (''ind'',X)
| 
| bgcolor=#ffe0e0|BIT ''zpg''
| bgcolor=#ffe0e0|AND ''zpg''
| bgcolor=#ffe0e0|ROL ''zpg''
| bgcolor=#e0e0e0|PLP
| bgcolor=#99ff99|AND #
| bgcolor=#e0e0e0|ROL A
| bgcolor=#e0ffff|BIT ''abs''
| bgcolor=#e0ffff|AND ''abs''
| bgcolor=#e0ffff|ROL ''abs''
|- 
! 3
| bgcolor=#ffffe0|BMI ''rel''
| bgcolor=#ffc299|AND (''ind''),Y
| 
| 
| bgcolor=#ffe0e0|AND ''zpg'',X
| bgcolor=#ffe0e0|ROL ''zpg'',X
| bgcolor=#e0e0e0|SEC
| bgcolor=#e0ffff|AND ''abs'',Y
| 
| 
| bgcolor=#e0ffff|AND ''abs'',X
| bgcolor=#e0ffff|ROL ''abs'',X
|- 
! 4
| bgcolor=#e0e0e0|RTI
| bgcolor=#ffc299|EOR (''ind'',X)
| 
| 
| bgcolor=#ffe0e0|EOR ''zpg''
| bgcolor=#ffe0e0|LSR ''zpg''
| bgcolor=#e0e0e0|PHA
| bgcolor=#99ff99|EOR #
| bgcolor=#e0e0e0|LSR A
| bgcolor=#e0ffff|JMP ''abs''
| bgcolor=#e0ffff|EOR ''abs''
| bgcolor=#e0ffff|LSR ''abs''
|- 
! 5
| bgcolor=#ffffe0|BVC ''rel''
| bgcolor=#ffc299|EOR (''ind''),Y
| 
| 
| bgcolor=#ffe0e0|EOR ''zpg'',X
| bgcolor=#ffe0e0|LSR ''zpg'',X
| bgcolor=#e0e0e0|CLI
| bgcolor=#e0ffff|EOR ''abs'',Y
| 
| 
| bgcolor=#e0ffff|EOR ''abs'',X
| bgcolor=#e0ffff|LSR ''abs'',X
|- 
! 6
| bgcolor=#e0e0e0|RTS
| bgcolor=#ffc299|ADC (''ind'',X)
| 
| 
| bgcolor=#ffe0e0|ADC ''zpg''
| bgcolor=#ffe0e0|ROR ''zpg''
| bgcolor=#e0e0e0|PLA
| bgcolor=#99ff99|ADC #
| bgcolor=#e0e0e0|ROR A
| bgcolor=#ffc299|JMP (''ind'')
| bgcolor=#e0ffff|ADC ''abs''
| bgcolor=#e0ffff|ROR ''abs''
|- 
! 7
| bgcolor=#ffffe0|BVS ''rel''
| bgcolor=#ffc299|ADC (''ind''),Y
| 
| 
| bgcolor=#ffe0e0|ADC ''zpg'',X
| bgcolor=#ffe0e0|ROR ''zpg'',X
| bgcolor=#e0e0e0|SEI
| bgcolor=#e0ffff|ADC ''abs'',Y
| 
| 
| bgcolor=#e0ffff|ADC ''abs'',X
| bgcolor=#e0ffff|ROR ''abs'',X
|- 
! 8
| 
| bgcolor=#ffc299|STA (''ind'',X)
| 
| bgcolor=#ffe0e0|STY ''zpg''
| bgcolor=#ffe0e0|STA ''zpg''
| bgcolor=#ffe0e0|STX ''zpg''
| bgcolor=#e0e0e0|DEY
| 
| bgcolor=#e0e0e0|TXA
| bgcolor=#e0ffff|STY ''abs''
| bgcolor=#e0ffff|STA ''abs''
| bgcolor=#e0ffff|STX ''abs''
|- 
! 9
| bgcolor=#ffffe0|BCC ''rel''
| bgcolor=#ffc299|STA (''ind''),Y
| 
| bgcolor=#ffe0e0|STY ''zpg'',X
| bgcolor=#ffe0e0|STA ''zpg'',X
| bgcolor=#ffe0e0|STX ''zpg'',Y
| bgcolor=#e0e0e0|TYA
| bgcolor=#e0ffff|STA ''abs'',Y
| bgcolor=#e0e0e0|TXS
| 
| bgcolor=#e0ffff|STA ''abs'',X
| 
|- 
! A
| bgcolor=#99ff99|LDY #
| bgcolor=#ffc299|LDA (''ind'',X)
| bgcolor=#99ff99|LDX #
| bgcolor=#ffe0e0|LDY ''zpg''
| bgcolor=#ffe0e0|LDA ''zpg''
| bgcolor=#ffe0e0|LDX ''zpg''
| bgcolor=#e0e0e0|TAY
| bgcolor=#99ff99|LDA #
| bgcolor=#e0e0e0|TAX
| bgcolor=#e0ffff|LDY ''abs''
| bgcolor=#e0ffff|LDA ''abs''
| bgcolor=#e0ffff|LDX ''abs''
|- 
! B
| bgcolor=#ffffe0|BCS ''rel''
| bgcolor=#ffc299|LDA (''ind''),Y
| 
| bgcolor=#ffe0e0|LDY ''zpg'',X
| bgcolor=#ffe0e0|LDA ''zpg'',X
| bgcolor=#ffe0e0|LDX ''zpg'',Y
| bgcolor=#e0e0e0|CLV
| bgcolor=#e0ffff|LDA ''abs'',Y
| bgcolor=#e0e0e0|TSX
| bgcolor=#e0ffff|LDY ''abs'',X
| bgcolor=#e0ffff|LDA ''abs'',X
| bgcolor=#e0ffff|LDX ''abs'',Y
|- 
! C
| bgcolor=#99ff99|CPY #
| bgcolor=#ffc299|CMP (''ind'',X)
| 
| bgcolor=#ffe0e0|CPY ''zpg''
| bgcolor=#ffe0e0|CMP ''zpg''
| bgcolor=#ffe0e0|DEC ''zpg''
| bgcolor=#e0e0e0|INY
| bgcolor=#99ff99|CMP #
| bgcolor=#e0e0e0|DEX
| bgcolor=#e0ffff|CPY ''abs''
| bgcolor=#e0ffff|CMP ''abs''
| bgcolor=#e0ffff|DEC ''abs''
|- 
! D
| bgcolor=#ffffe0|BNE ''rel''
| bgcolor=#ffc299|CMP (''ind''),Y
| 
| 
| bgcolor=#ffe0e0|CMP ''zpg'',X
| bgcolor=#ffe0e0|DEC ''zpg'',X
| bgcolor=#e0e0e0| CLD
| bgcolor=#e0ffff|CMP ''abs'',Y
| 
| 
| bgcolor=#e0ffff|CMP ''abs'',X
| bgcolor=#e0ffff|DEC ''abs'',X
|- 
! E
| bgcolor=#99ff99|CPX #
| bgcolor=#ffc299|SBC (''ind'',X)
| 
| bgcolor=#ffe0e0|CPX ''zpg''
| bgcolor=#ffe0e0|SBC ''zpg''
| bgcolor=#ffe0e0|INC ''zpg''
| bgcolor=#e0e0e0|INX
| bgcolor=#99ff99|SBC #
| bgcolor=#e0e0e0|NOP
| bgcolor=#e0ffff|CPX ''abs''
| bgcolor=#e0ffff|SBC ''abs''
| bgcolor=#e0ffff|INC ''abs''
|- 
! F
| bgcolor=#ffffe0|BEQ ''rel''
| bgcolor=#ffc299|SBC (''ind''),Y
| 
| 
| bgcolor=#ffe0e0|SBC ''zpg'',X
| bgcolor=#ffe0e0|INC ''zpg'',X
| bgcolor=#e0e0e0|SED
| bgcolor=#e0ffff|SBC ''abs'',Y
| 
| 
| bgcolor=#e0ffff|SBC ''abs'',X
| bgcolor=#e0ffff|INC ''abs'',X
|-
|colspan=13|Blank opcodes (e.g., '''F2''') and all opcodes whose low nibbles are '''3''', '''7''', '''B''' and '''F''' are undefined in the 6502 instruction set.
|}

===Example code===
The following 6502 [[assembly language]] [[source code]] is for a subroutine named <code>TOLOWER</code>, which copies a [[null-terminated string|null-terminated]] [[string (computer science)|character string]] from one location to another, converting upper-case letter characters to lower-case letters. The string being copied is the "source", and the string into which the converted source is stored is the "destination".
<!-- NOTE: This is not intended to be optimized code, but to illustrate the variety of instructions available on the CPU. -->

<!-- NOTE: Now it is optimized. :) Best to post examples that reflect good programming style & efficiency, rather than examples that are obfuscated in an effort to use the maximum number of different instructions. Also, please avoid using non-standard assembler syntax in 6502 programming examples, e.g., a pseudo-op such as DW, which is not supported by all assemblers. The MOS Technology standard exists for a reason. -->
{|
| style="vertical-align:top;"|
<pre>











0080
 
0080  00 04
0082  00 05
 
0600
 
0600  A0 00
 
0602  B1 80
0604  F0 11
 
0606  C9 41
0608  90 06
 
060A  C9 5B
060C  B0 02
 
060E  09 20
 
0610  91 82
0612  C8   
0613  D0 ED
 
 
 
 
0615  38   
0616  60
 
0617  91 82
0619  18   
061A  60
 
061B       
</pre>
|
<syntaxhighlight lang="ca65" highlight="19">
; TOLOWER:
;
;   Convert a null-terminated character string to all lower case.
;   Maximum string length is 255 characters, plus the null term-
;   inator.
;
; Parameters:
;
;   SRC – Source string address
;   DST – Destination string address
;
        ORG $0080
;
SRC     .WORD $0400     ;source string pointer
DST     .WORD $0500     ;destination string pointer
;
        ORG $0600       ;execution start address
;
TOLOWER LDY #$00        ;starting index
;
LOOP    LDA (SRC),Y     ;get from source string
        BEQ DONE        ;end of string
;
        CMP #'A'        ;if lower than UC alphabet...
        BCC SKIP        ;copy unchanged
;
        CMP #'Z'+1      ;if greater than UC alphabet...
        BCS SKIP        ;copy unchanged
;
        ORA #%00100000  ;convert to lower case
;
SKIP    STA (DST),Y     ;store to destination string
        INY             ;bump index
        BNE LOOP        ;next character
;
; NOTE: If Y wraps the destination string will be left in an undefined
;  state. We set carry to indicate this to the calling function.
;
        SEC             ;report string too long error &...
        RTS             ;return to caller
;
DONE    STA (DST),Y     ;terminate destination string
        CLC             ;report conversion completed &...
        RTS             ;return to caller
;
        .END
</syntaxhighlight>
|}

==Detailed behavior==
[[Image:BreakNES MOS 6502.jpg|right|thumb|6502 processor die with drawn-in NMOS transistors and labels hinting at the functionality of the 6502's components]]
{{See also|Interrupts in 65xx processors}}
The processor's [[non-maskable interrupt]] (NMI) input is [[Interrupt#Edge-triggered|edge sensitive]], which means that the interrupt is triggered by the falling edge of the signal rather than its level. The implication of this feature is that a [[wired-OR]] interrupt circuit is not readily supported. However, this also prevents nested NMI interrupts from occurring until the hardware makes the NMI input inactive again, often under control of the NMI [[interrupt handler]].

The simultaneous assertion of the NMI and [[Interrupt request|IRQ]] (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will almost immediately respond to IRQ, as IRQ is [[Interrupt#Level-triggered|level sensitive]]. Thus a sort of built-in interrupt priority was established in the 6502 design. (The first opcode of the NMI handler is executed before the IRQ is detected again.)

{{anchor|BRK Flag}}The B flag is set by the 6502's periodically sampling its NMI edge detector's output and its IRQ input. The IRQ signal being driven low is only recognized though if IRQs are not masked by the I flag. If in this way a NMI request or (maskable) IRQ is detected the B flag is set to zero and causes the processor to execute the BRK instruction next instead of executing the next instruction based on the program counter.<ref>{{Cite book |url=https://github.com/emu-russia/breaks/releases/download/6502-book-revB5/Breaking_6502_Eng_B5.pdf |title=Breaking NES Book – 6502 Core |date=2022-06-24 |edition=B5 |pages=61–62 |quote=The arrival of any interrupt is reflected on flag B, the output of which (B_OUT) forces the processor to execute a BRK instruction ... |access-date=2023-12-24 |archive-date=2024-04-12 |archive-url=https://web.archive.org/web/20240412044616/https://github.com/emu-russia/breaks/releases/download/6502-book-revB5/Breaking_6502_Eng_B5.pdf |url-status=live }}</ref><ref>{{Cite web|title=6502 BRK and B bit|url=http://visual6502.org/wiki/index.php?title=6502_BRK_and_B_bit|url-status=dead|access-date=2021-05-15|website=VisualChips|archive-date=2021-04-05|archive-url=https://web.archive.org/web/20210405071302/http://visual6502.org/wiki/index.php?title=6502_BRK_and_B_bit}}</ref>

The BRK instruction then pushes the processor status onto the stack, with the B flag bit set to zero. At the end of its execution the BRK instruction resets the B flag's value to one. This is the only way the B flag can be modified. If an instruction other than the BRK instruction pushes the B flag onto the stack as part of the processor status<ref>{{Cite web|title=FLAGS|url=https://github.com/ogamespec/breaks/blob/master/Docs/6502/6502_circuitlab/flags.png|access-date=2021-05-15|website=ogamespec|quote=B_OUT; INTERNAL DATA BUS (DB)}}</ref> the B flag always has the value one.

A high-to-low transition on the SO input pin will set the processor's overflow status bit. This can be used for fast response to external hardware. For example, a high-speed [[Polling (computer science)|polling]] device driver can poll the hardware once in only three cycles using a Branch-on-oVerflow-Clear (<code>BVC</code>) instruction that branches to itself until overflow is set by an SO falling transition. The [[Commodore 1541]] and other [[Commodore International|Commodore]] [[floppy disk]] drives use this technique to detect when the [[serialization|serializer]] is ready to transfer another byte of disk data. The system hardware and software design must ensure that an SO will not occur during arithmetic processing and disrupt calculations.

==Variations and derivatives {{anchor|variants|Variants}}==
The 6502 was the most prolific variant of the 65xx series family from [[MOS Technology]].

The 6501 and 6502 have 40-pin [[dual inline package|DIP]] packages; the 6503, 6504, 6505, and 6507 are 28-pin DIP versions, for reduced chip and circuit board cost. In all of the 28-pin versions, the pin count is reduced by leaving off some of the high-order address pins and various combinations of function pins, making those functions unavailable.

{| class="wikitable" style="text-align: center; width: 500px;"
|+ Pinout differences
|-
! Pin || 6800 !! 6501 !! 6502
|-
| 2 || Halt || Ready || Ready
|-
| 3 || ∅1 (in) ||∅1 (in) || ∅1 (out)
|-
| 5 || Valid memory address || Valid memory address || N.C.
|-
| 7 || Bus available || Bus available || SYNC
|-
| 36 || Data bus enable || Data bus enable || N.C.
|-
| 37 || ∅2 (in) || ∅2 (in) || ∅0 (in)
|-
| 38 || N.C. || N.C. || Set overflow flag
|-
| 39 || Three-state control || N.C. || ∅2 (out)
|}

Typically, the 12 pins omitted to reduce the pin count from 40 to 28 are the three [[not connected]] (NC) pins, one of the two Vss pins, one of the clock pins, the SYNC pin, the set overflow (SO) pin, either the maskable interrupt or the non-maskable interrupt (NMI), and the four most-significant address lines (A12&ndash;A15).  The omission of four address pins reduces the external addressability to 4&nbsp;KB (from the 64&nbsp;KB of the 6502), though the internal PC register and all effective address calculations remain [[16-bit computing|16-bit]].

The [[MOS Technology 6507|6507]] omits both interrupt pins in order to include address line A12, providing 8 KB of external addressability but no interrupt capability.  The 6507 was used in the popular [[Atari 2600]] video game console, the design of which divides the 8 KB memory space in half, allocating the lower half to the console's internal RAM and peripherals, and the upper half to the Game Cartridge, so Atari 2600 cartridges have a 4 KB address limit (and the same capacity limit unless the cartridge contains [[bank switching]] circuitry).

One popular 6502-based computer, the [[Commodore 64]], used a modified 6502 CPU, the [[MOS Technology 6510|6510]]. Unlike the 6503&ndash;6505 and 6507, the 6510 is a 40-pin chip that adds internal hardware: a 6-bit parallel I/O port mapped to addresses 0000 and 0001. The [[MOS Technology 6508|6508]] is another chip that, like the 6510, adds internal hardware: 256 bytes of [[Static random-access memory|SRAM]] and an 8-bit I/O port similar to those featured by the 6510. Though these chips do not have reduced pin counts compared to the 6502, they need new pins for the added parallel I/O port.  In this case, no address lines are among the removed pins.

{| class="wikitable sortable"
|+ Variations
|-
! Company
! Model
! Description
|-
| 
| data-sort-value="6502"|6502
| A 1&nbsp;MHz chip used in ''[[KIM-1]]'' and other single board computers in the mid-1970s.
|-
| 
| data-sort-value="6502A"|6502A
| A 1.5&nbsp;MHz chip used in ''[[Asteroids Deluxe]]'' and at 2&nbsp;MHz in the [[BBC Micro]]
|-
| 
| data-sort-value="6502B"|6502B 
| Version of the 6502 capable of running at a maximum speed of 3&nbsp;MHz instead of 2&nbsp;MHz. The B was used in both the [[Apple III]] and early [[Atari 8-bit computers]], each running at ~1.8&nbsp;MHz.{{efn|name=ntsc|reference=More precisely these systems internally divide an [[NTSC]] [[colorburst crystal]] yielding {{frac|315|176}}&nbsp;Mhz = 1.78977{{overbar|27}}&nbsp;MHz}}
|-
| 
| data-sort-value="6502C"|6502C
| The “official” 6502C was a version of the original 6502 able to run at up to 4&nbsp;MHz.

Not to be confused with SALLY, a custom 6502 designed for Atari (and sometimes referred to by them as "6502C"<ref name='am_sally'/>) nor with the similarly named [[65C02]].
|-
| 
| data-sort-value="SALLY"|SALLY, C014806, "6502C"
| {{anchor|sally}}Custom 6502 variant designed for Atari, used in later [[Atari 8-bit computers]] and [[Atari 5200]] and [[Atari 7800]] consoles.

Has a HALT signal on pin 35 and the R/W signal on pin 36 (these pins are not connected (N/C) on a standard 6502). Pulling HALT low latches the clock, pausing the processor. This was used to allow the video circuitry direct memory access (DMA).<ref>{{Cite book|title=ATARI 1200 XL HOME COMPUTER FIELD SERVICE MANUAL|publisher=ATARI|date=February 1983|chapter=6502 (modified) CPU Microprocessor}}</ref>

Although sometimes referred to as "6502C" in Atari documentation, this is not the same as the ''official'' 6502C and the chip itself is never marked as such.<ref name='am_sally'>{{cite web|url=http://www.atarimania.com/faq-atari-400-800-xl-xe-what-are-sally-antic-ctia-gtia-fgtia-pokey-and-freddie_14.html|title=FAQ 400 800 XL XE: What are SALLY, ANTIC, CTIA/GTIA/FGTIA, POKEY, and FREDDIE?|quote=named SALLY by Atari engineers, but [support documents call it] "6502 (Modified)", "6502 Modified", "Custom 6502", or "6502C". [..] SALLY 6502 chips are never marked "6502C" but, other than the UMC UM6502I, always [marked] C014806. [..] [Other] chips marked "6502C" [..] are NOT the Atari "6502C" but [standard 6502] certified for 4MHz|archiveurl=https://web.archive.org/web/20200719024918/http://www.atarimania.com/faq-atari-400-800-xl-xe-what-are-sally-antic-ctia-gtia-fgtia-pokey-and-freddie_14.html|archivedate=19 July 2020}}</ref>

|-
|-
| MOS
| data-sort-value="6503"|[[MOS Technology 6503|6503]]
| Reduced memory addressing capability (4 KB) and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA">1982 MOS Technology Data Catalog (PDF obtained from bitsavers.org)</ref>
|-
| MOS
| data-sort-value="6504"|[[MOS Technology 6504|6504]]
| Reduced memory addressing capability (8 KB), no NMI, and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/>
|-
| MOS
| data-sort-value="6505"|[[MOS Technology 6505|6505]]
| Reduced memory addressing capability (4 KB) and no NMI, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/>
|-
| MOS
| data-sort-value="6506"|[[MOS Technology 6505|6506]]
| Reduced memory addressing capability (4 KB), no NMI, and no RDY input, but all 3 clock pins of the 6502 (i.e. a 2-phase output clock), in a 28-pin DIP package (with the SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/>
|-
| MOS
| data-sort-value="6507"|[[MOS Technology 6507|6507]]
| Reduced memory addressing capability (8 KB) and no interrupts, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/> This chip was used in the [[Atari 2600]] video game system.
|-
| MOS
| data-sort-value="6508"|[[MOS Technology 6508|6508]]
| Has a built-in 8-bit input/output port and 256 bytes of internal static RAM.
|-
| MOS
| data-sort-value="6509"|[[MOS Technology 6509|6509]]
| Can address up to 1&nbsp;MB of RAM as 16 banks of 64&nbsp;KB and was used in the Commodore [[CBM-II]] series.
|-
| MOS
| data-sort-value="6510"|[[MOS Technology 6510|6510]]
| Has a built-in 6-bit programmable input/output port and was used in the [[Commodore 64]]. The 8500 is effectively an HMOS version of the 6510, and replaced it in later versions of the C64.
|-
| MOS
| data-sort-value="6512"|[[MOS Technology 6512|6512]]<br/>[[MOS Technology 6513|6513]]<br/>[[MOS Technology 6514|6514]]<br/>[[MOS Technology 6515|6515]]
| The MOS Technology 6512, 6513, 6514, and 6515 each rely on an external clock, instead of using an internal clock generator like the 650x (e.g. 6502). This was used to advantage in some designs where the clocks could be run asymmetrically, increasing overall CPU performance.

The 6512 is a 6502 with a 2-phase clock input for an external clock oscillator, instead of an on-board clock oscillator.<ref name="ReferenceA"/> The 6513, 6514 and 6515 are similarly equivalent to (respectively) a 6503, 6504 and 6505 with the same 2-phase clock input.<ref name="ReferenceA"/>

The 6512 was used in the [[BBC Micro|BBC Micro B+64]].
|-
| Ricoh
| data-sort-value="RP2A03"|[[Ricoh 2A03|RP2A03]]<br/>RP2A07
| Unlicensed 6502 variants running at ~1.8&nbsp;MHz{{efn|name=ntsc}} including an audio processing unit but lacking the BCD mode, used in the [[Nintendo Entertainment System]].
|-
| MOS
| data-sort-value="6591"|[[MOS Technology 6591|6591]]<br/>6592
| [[System on a chip]] designs that utilize a complete [[Atari 2600]] in a 48-pin DIP package.<ref>{{Cite web |url=https://atariage.com/forums/topic/241219-a2600-clone-6591-chip-pinout/?tab=comments#comment-3291842 |title=AtariAge: A2600 clone, 6591 chip pinout |date=3 August 2015 |access-date=2019-07-22 |archive-date=2020-08-05 |archive-url=https://web.archive.org/web/20200805060921/https://atariage.com/forums/topic/241219-a2600-clone-6591-chip-pinout/?tab=comments#comment-3291842 |url-status=live}}</ref><ref>{{Cite web |url=https://hackaday.com/2012/04/07/the-teensiest-atari-2600-ever/ |title=Hackaday: The teensiest Atari 2600 ever |date=7 April 2012 |access-date=2019-07-22 |archive-date=2019-07-22 |archive-url=https://web.archive.org/web/20190722203421/https://hackaday.com/2012/04/07/the-teensiest-atari-2600-ever/ |url-status=live}}</ref>
|-
| WDC
| data-sort-value="65C02"|[[65C02]]
| [[CMOS]] version of the NMOS 6502 that was designed by [[Bill Mensch]] of the [[Western Design Center]] (WDC), featuring reduced power consumption, support for much higher clock speeds, new instructions, new addressing modes for some existing instructions, and correction of NMOS errata, such as the <code>JMP ($xxFF)</code> bug.
|-
| data-sort-value="MOS Technology"|CSG, MOS
| data-sort-value="65CE02"|[[CSG 65CE02|65CE02]]
| CMOS variant developed by the [[Commodore Semiconductor Group]] (CSG), formerly MOS Technology.  The 65CE02 provides a further enhanced instruction set from the 65C02, featuring a third indexing register (Z), base page register, 16-bit stack and faster program execution with the minimal instruction timing reduced from 2 to 1 clock cycles.
|-
| Rockwell
| data-sort-value="R6511Q"|R6511Q<br/><br/>R6500/11, R6500/12, R6500/15 "''One-Chip Microcomputers''"
| Enhanced versions of the 6502-based processor, also including individual bit manipulation operations (RMB, SMB, BBR and BBS), on-chip 192-byte zero-page RAM, [[UART]], etc.<ref>{{cite web
|title=Rockwell R6511Q
|url=http://www.cpu-world.com/CPUs/6500/Rockwell-R6511Q.html
|access-date=30 Apr 2020
|archive-date=15 September 2020
|archive-url=https://web.archive.org/web/20200915151513/http://www.cpu-world.com/CPUs/6500/Rockwell-R6511Q.html
|url-status=live
}}</ref><ref>{{cite web
|title=Rockwell R6500/11, R6500/12 and R6500/15 One-Chip Microcomputers
|url=https://datasheetspdf.com/pdf-file/1338410/Rockwell/R6500-11/1
|date=7 Jun 1987
|access-date=30 Apr 2020
|archive-date=4 August 2020
|archive-url=https://web.archive.org/web/20200804041549/https://datasheetspdf.com/pdf-file/1338410/Rockwell/R6500-11/1
|url-status=live
}}</ref>
|-
| Rockwell
| R65F11<br/>R65F12
| The Rockwell R65F11 (introduced in 1983) and the later R65F12 are enhanced versions of the 6502-based processor, also including individual bit manipulation operations (RMB, SMB, BBR and BBS), on-chip zero-page RAM, on-chip [[Forth (programming language)|Forth]] kernel ROM, a UART, etc.<ref>Randy M. Dumse.
"The R65F11 and F68K Single-Chip Forth Computers".
[http://www.forth.org/bournemouth/jfar/vol2/no1/article1.pdf]{{dead link|date=May 2017|bot=InternetArchiveBot|fix-attempted=yes}}
[http://soton.mpeforth.com/flag/jfar/vol2/no1/article1.pdf] {{Webarchive|url=https://web.archive.org/web/20141202144044/http://soton.mpeforth.com/flag/jfar/vol2/no1/article1.pdf|date=2014-12-02}}
1984.</ref><ref>
Ed Schmauch.
[http://www.forth.org/bournemouth/jfar/vol4/no2/article48.pdf "A Computerized Corrosion Monitoring System"]{{dead link|date=May 2017 |bot=InternetArchiveBot |fix-attempted=yes}}.
1986.
</ref><ref>Lawrence P. Forsley.
[https://books.google.com/books?id=Yx8YAQAAMAAJ "Embedded systems: 1990 Rochester Forth Conference: June 12 – 16th, 1990 University of Rochester"] {{Webarchive|url=https://web.archive.org/web/20150325214054/http://books.google.com/books?id=Yx8YAQAAMAAJ |date=2015-03-25}}.
p. 51.</ref><ref>Rockwell.
[http://www.smallestplcoftheworld.org/RSC-FORTH_User's_Manual.pdf "RSC-Forth User's Manual"] {{Webarchive|url=https://web.archive.org/web/20131207015149/http://smallestplcoftheworld.org/RSC-FORTH_User%27s_Manual.pdf |date=2013-12-07}}.
1983.</ref><ref>{{cite web
|title=Rockwell R65F11 R65F12 Forth Based Microcomputers
|url=http://archive.6502.org/datasheets/rockwell_r65f11_r65f12_forth_microcomputers.pdf
|date=June 1987
|access-date=28 Apr 2020
|archive-date=4 August 2020
|archive-url=https://web.archive.org/web/20200804035007/http://archive.6502.org/datasheets/rockwell_r65f11_r65f12_forth_microcomputers.pdf
|url-status=live
}}</ref>
|-
| GTE
| data-sort-value="G65SC12"|G65SC12
| Drop in 6502 CMOS variant without individual bit manipulation operations (RMB, SMB, BBR and BBS).<ref>{{cite book |first=Rodnay |last=Zaks |title=Programming the 6502 |page=348}}</ref>  This was used in the [[BBC Master]].
|-
| GTE
| data-sort-value="G65SC102"|G65SC102 
| Software compatible with the 6502, but has a slightly different pinout and oscillator circuit. The [[BBC Master]] Turbo included the 4&nbsp;MHz version of this CPU on a coprocessor card, which could also be bought separately and added to the Master 128.
|-
| Rockwell
| R65C00<br/>R65C21<br/>R65C29
| The R65C00, R65C21, and R65C29 have two enhanced CMOS 6502s in a single chip, and the R65C00 and R65C21 additionally contained 2&nbsp;KB of mask-programmable ROM.<ref>{{cite web |url=http://www.datasheetarchive.com/dl/Scans-055/DSAIH000103824.pdf |title=Arquivo.pt |access-date=2014-10-26 |url-status=dead |archive-url=http://arquivo.pt/wayback/20160515111805/http%3A//www.datasheetarchive.com/dl/Scans%2D055/DSAIH000103824.pdf |archive-date=2016-05-15}}</ref><ref>{{cite web|url=https://archive.org/details/bitsavers_rockwelldaDataBook_80778847|title=rockwell :: dataBooks :: 1985 Rockwell Data Book|via=Internet Archive}}</ref>
|-
| 
| data-sort-value="CM630"|{{anchor|CM630}}CM630
| A 1&nbsp;MHz [[Eastern Bloc]] clone of the 6502 and was used in the [[Pravetz computers|Pravetz]] 8A and 8C, Bulgarian clones of the [[Apple II]].<ref name="hcm-easteurope">{{cite web |title=East-European Home-Computer: Bulgaria |url=http://www.homecomputer.de/pages/easteurope_bu.html |website=HCM: Home Computer Museum |access-date=3 October 2020 |archive-date=1 July 2006 |archive-url=https://web.archive.org/web/20060701041245/http://www.homecomputer.de/pages/easteurope_bu.html |url-status=live}}</ref>
|-
| MOS
| data-sort-value="7501"|[[MOS Technology 7501|7501]]<br/>[[MOS Technology 8501|8501]]
| 6510 (an enhanced 6502) variants, introduced in 1984.<ref name="auto">http://plus4world.powweb.com/hardware/MOS_75018501 {{Webarchive|url=https://web.archive.org/web/20200220065417/http://plus4world.powweb.com/hardware/MOS_75018501 |date=2020-02-20}} Hardware – MOS 7501/8501</ref> They extended the number of I/O port pins from 6 to 7, but omitted pins for non-maskable interrupt and clock output.<ref>https://ist.uwaterloo.ca/~schepers/MJK/7501.html {{Webarchive|url=https://web.archive.org/web/20210719064313/https://ist.uwaterloo.ca/~schepers/MJK/7501.html |date=2021-07-19}}  CPU 7501 / 8501</ref> Used in Commodore's [[Commodore 16|C-16]], [[Commodore 16|C-116]] and [[Commodore Plus/4|Plus/4]] computers. The main difference between 7501 and 8501 CPUs is that the 7501 was manufactured with the [[HMOS]]-1 process and the 8501 with HMOS-2.<ref name="auto"/>
|-
| MOS
| data-sort-value="8500"|[[MOS Technology 8500|8500]]
| Introduced in 1985 as an [[HMOS]] version of the 6510 (which is in turn based on the 6502). Other than the process modification, the 8500 is virtually identical to the [[NMOS logic|NMOS]] version of the 6510. It replaced the 6510 in later versions of the [[Commodore 64]].
|-
| MOS
| data-sort-value="8502"|[[MOS Technology 8502|8502]]
| Designed by MOS Technology and used in the [[Commodore 128]]. Based on the MOS 6510 used in the Commodore 64, the 8502 was able run at double clock rate of the 6510.<ref name="CBM128SM">''Service Manual C-128/C128D Computer'', Commodore Business Machines, PN-314001-08, November 1987</ref> The 8502 family also includes the MOS 7501, 8500 and 8501.
|-
| Hudson Soft
| data-sort-value="HuC6280"|[[Hudson Soft HuC6280|HuC6280]]
| Japanese video game company [[Hudson Soft]]'s improved version of the WDC 65C02. Manufactured for them by [[Seiko Epson]] and [[NEC]] for the [[SuperGrafx]]. The most notable product using the HuC6280 is NEC's TurboGrafx-16 video game console.
|-
| [[VLSI Technology|VLSI]]
| data-sort-value="VL65NC02"|VL65NC02<ref>{{Cite book |url=http://archive.org/details/1988_VTI_ASIC |title=IC Datasheet: 1988 VTI ASIC |pages=225–238 |chapter=VL65NC02}}</ref>
| VLSI licensed 65C02 variant was included in the [[Atari Lynx]]'s main system IC named Mikey.
|}

===16-bit derivatives===
The Western Design Center designed and, {{as of|2025|lc=on}}, still produces the [[WDC 65C816]]S processor, a 16-bit, static-core successor to the [[65C02]]. The W65C816S is a newer variant of the 65C816, which is the core of the [[Apple IIGS]] computer and is the basis of the [[Ricoh 5A22]] processor that powers the [[Super Nintendo Entertainment System]]. The W65C816S incorporates minor improvements over the 65C816 that make the newer chip not an exact hardware-compatible replacement for the earlier one. Among these improvements was conversion to a static core, which makes it possible to stop the clock in either phase without the registers losing data. Available through electronics distributors, as of March 2020, the W65C816S is officially rated for 14&nbsp;MHz operation.

The Western Design Center also designed and produced the [[WDC 65C816|65C802]], which was a 65C816 core with a 64-kilobyte address space in a 65(C)02 pin-compatible package. The 65C802 could be retrofitted to a 6502 board and would function as a 65C02 on power-up, operating in "emulation mode." As with the 65C816, a two-instruction sequence would switch the 65C802 to "native mode" operation, exposing its 16-bit [[accumulator (computing)|accumulator]] and [[index register]]s, and other 65C816 features. The 65C802 was not widely used and production ended.

==Bugs and quirks==
The 6502 had several [[hardware bug|bugs]] and quirks, which had to be accounted for when programming it:

* The earliest revisions of the 6502, such as those shipped with some [[KIM-1]] computers, did not have a [[circular shift|ROR]] (rotate right memory or accumulator) instruction. In these chips, the operation of the opcode that was later assigned to ROR is effectively an ASL (arithmetic shift left) instruction that does not affect the carry bit in the status register. Initially, MOS intentionally excluded ROR from the instruction set, deeming it not of enough value to justify its costs.  In reaction to many customer inquirires, MOS promised in the second edition of the MCS6500 Programming Manual (document no. 6500-50A) that ROR would appear in 6502 chips starting in 1976.<ref name="ROR" />{{efn|Eric Schlaepfer, who built a transistorized replica of the 6502 at monster6502.com, argues in his Youtube video "The 6502 Rotate Right Myth" (by TubeTimeUS) that according to Chuck Peddle and Bill Mensch there was no ROR bug. Instead, the instruction was not implemented at all as it was deemed unnecessary. Schlaepfer then compares screenshots from the early revision to later revisions of the 6502 and proves that the ROR instruction was not present in either the instruction decoding, wiring, or execution parts of the chip.}} The vast majority of 6502 chips in existence today do feature the ROR instruction; these include all those CPUs originally installed in popular fully-assembled microcomputers such as the Apple II and Commodore 64 lines, all of which were manufactured after 1976.
* The [[NMOS logic|NMOS]] 6502 family has a variety of [[illegal opcode|undocumented instructions]], which vary from one chip manufacturer to another. The 6502 instruction decoding is implemented in a [[hardwired control|hardwired]] logic array (similar to a [[programmable logic array]]) that is only defined for 151 of the 256 available [[opcode]]s. The remaining 105 trigger strange and occasionally hard-to-predict actions, such as crashing the processor, performing two valid instructions consecutively, performing strange mixtures of two instructions, or simply doing nothing at all. Some hardware designers used the undefined opcodes to extend the 6502 instruction set by detecting when a certain undefined opcode is fetched and performing an extension operation externally to the processor while substituting a neutral (NOP-like) opcode to the 6502 in order to make it idle while the external hardware handles the extension operation.  Also, some programmers utilized this feature to extend the 6502 instruction set by providing functionality for the unimplemented opcodes with specially written software intercepted at the BRK instruction's 0xFFFE vector.<ref>{{cite magazine |last=Moser |first=Carl W. |title=Add a Trap Vector for Unimplemented 6502 Opcodes |magazine=Dr. Dobb's Journal of Computer Calisthenics and Orthodontia |issue=31 |page=32 |url=http://archive.6502.org/publications/dr_dobbs_journal/dr_dobbs_journal_vol_04.pdf |date=January 1979 |location=Menlo Park, California |access-date=2017-01-07 |archive-date=2016-06-11 |archive-url=https://web.archive.org/web/20160611125516/http://archive.6502.org/publications/dr_dobbs_journal/dr_dobbs_journal_vol_04.pdf |url-status=live}}</ref><ref>{{cite magazine |last=Harrod |first=Dennette A. |title=The 6502 Gets Microprogrammable Instructions |magazine=BYTE |volume=5 |issue=10 |page=282 |url=https://archive.org/details/byte-magazine-1980-10 |date=October 1980 |location=Peterborough, New Hampshire |access-date=2017-01-07}}</ref> All of the undefined opcodes have been replaced with [[NOP (code)|NOP]] instructions in the [[65C02]], an enhanced [[CMOS]] version of the 6502, although with varying byte sizes and execution times. (Some of them actually perform memory read operations but then ignore the data.) In the [[WDC 65C816|65C802/65C816]], all 256 opcodes perform defined operations.
* The 6502's [[indirect branch|memory indirect jump]] instruction, <code>JMP (&lt;address>)</code>, has a nonintuitive limitation which many users consider a defect. If <var>&lt;address></var> is [[hexadecimal|hex]] <var>xxFF</var> (i.e., any word ending in <var>FF</var>), the processor will not jump to the address stored in <var>xxFF</var> and <code>xxFF+1</code> as expected, but rather the one defined by <var>xxFF</var> and <var>xx00</var> (for example, <code>JMP ($10FF)</code> would jump to the address stored in 10FF and 1000, instead of the one stored in 10FF and 1100). This can be avoided simply by not placing any indirect jump target address across a page boundary, and the MOS Technology MCS6500 Programming Manual gives reason to believe that this was the intention of the designers of the 6502, in order to save space on the chip that would have been used to implement the more complex behavior of conditionally adding 1 clock cycle to propagate the carry when necessary. This ostensible defect continued through the entire NMOS line but was corrected in the CMOS derivatives.
* The NMOS 6502 indexed addressing across page boundaries will do an extra read of an invalid address in the page of the base address (to which the index is added). This characteristic may cause random issues by accessing hardware that acts on a read, such as clearing timer or IRQ flags, sending an I/O handshake, etc. The extra read can be predicted and managed to avoid such problems, but only with special care in both hardware and software design.  This flaw continued through the entire NMOS line but was corrected in the CMOS derivatives, in which the processor does an extra read of the last instruction byte.
* The 6502 [[read–modify–write]] instructions perform one read and two write cycles. First, the unmodified data that was read is written back, and then the modified data is written. This characteristic may cause issues by twice accessing hardware that acts on a write. This anomaly continued through the full NMOS line but was fixed in the CMOS derivatives, in which the processor does two reads and one write cycle. [[Defensive programming]] practice will generally avoid this problem by not executing read/modify/write instructions on hardware registers.
* The N (result negative), V (sign bit overflow) and Z (result zero) [[status register|status flags]] are generally meaningless when performing arithmetic operations while the processor is in [[binary-coded decimal|BCD]] mode, as these flags are undefined in decimal mode and have been empirically shown to reflect the binary, not BCD, result. This limitation was removed in the CMOS derivatives, at the cost of one added clock cycle for an ADC or SBC instruction in decimal mode (except on the 65C816). Therefore, this feature may be used to distinguish a CMOS processor from an NMOS version (by relying on the undocumented behavior of the NMOS version).<ref>{{cite web |url=http://www.s-direktnet.de/homepages/k_nadj/cputest.html |archive-url=https://web.archive.org/web/20080102014138/http://www.s-direktnet.de/homepages/k_nadj/cputest.html |title=65c02, 6502, 65816 ??? CPU sells but who's buying... |date=19 June 1997 |author=Draco |archive-date=2 January 2008 |url-status=dead}}</ref>
* If the 6502 happens to be in BCD mode when a hardware interrupt occurs, it will not revert to binary mode. This characteristic could result in obscure bugs in the interrupt service routine (ISR) if it fails to clear BCD mode before performing any arithmetic operations. The 6502 programming manual thus requires each ISR to reset or set the D flag if it uses the ADC or SBC instruction, but occasionally a human programmer may mistakenly omit to do this, causing a bug. For example, the [[Commodore 64]]'s [[KERNAL]] did not correctly handle this processor characteristic, requiring that [[interrupt request|IRQ]]s be disabled or re-vectored during BCD math operations. This issue was addressed in the CMOS derivatives also, by making reset and all interrupts automatically reset the D flag. (The change has the one disadvantage that it makes a [rare] program that operates continuously in decimal mode slightly longer and slower, as now every ISR must ''set'' the D flag before executing ADC or SBC.)
* The 6502 instruction set includes BRK (opcode $00), which is technically a [[software interrupt]] (similar in spirit to the SWI mnemonic of the [[Motorola 6800]] and [[ARM architecture family|ARM]] processors). BRK is most often used to interrupt program execution and start a [[Machine code monitor|machine language monitor]] for testing and debugging during software development. BRK could also be used to route program execution using a simple jump table (analogous to the manner in which the [[Intel 8086]] and derivatives handle software interrupts by number). However, if a maskable [[hardware interrupt]] occurs when the processor is fetching a BRK instruction, the NMOS version of the processor will fail to execute BRK and instead proceed as if only the hardware interrupt had occurred. This fault&mdash;an unequivocal hardware bug&mdash;was corrected in the CMOS implementation of the processor, which first calls the ISR for the hardware interrupt and then executes the BRK instruction.
* When executing JSR (jump to subroutine) and RTS (return from subroutine) instructions, the return address pushed to the stack by JSR is that of the last byte of the JSR operand (that is, the most significant byte of the subroutine address), rather than the address of the following instruction. This is because the actual copy (from [[program counter]] to [[stack (abstract data type)|stack]] and then conversely) takes place before the automatic increment of the program counter that occurs at the end of every instruction.<ref>{{cite book |chapter-url=http://www.atariarchives.org/roots/chapter_6.php |title=Atari Roots – A Guide To Atari Assembly Language |chapter=6 |first=Mark |last=Andrews |year=1984 |publisher=Datamost, Incorporated |isbn=0-88190-171-7 |access-date=2008-06-14 |archive-date=2008-04-24 |archive-url=https://web.archive.org/web/20080424093352/http://www.atariarchives.org/roots/chapter_6.php |url-status=live}}</ref> This characteristic would go unnoticed unless the code examined the return address in order to retrieve parameters in the code stream (a 6502 programming idiom documented in the ''ProDOS 8 Technical Reference Manual''). It remains a characteristic of 6502 derivatives to this day. The original MCS6500 Programming Manual points it out and explains the reason: it saves one clock cycle in the JSR by not incrementing the PC before pushing it, while in the RET instruction, the deferred increment of the pulled PC is overlapped with other steps and adds no clock cycle.  As designed, a JSR and RET take 12 clock cycles total; if the JSR pushed the incremented PC, the call and return would take 13 clock cycles.
* The read access of the CPU can be delayed by setting the RDY pin to low temporarily. However, during write access, which can take up to three consecutive clock cycles for a BRK instruction, the CPU will stop only in the next read cycle.<ref>{{Cite book |title=6500 Series Hardware Manual; 2nd Ed |publisher= MOS Technology, INC. |date=January 1976 |chapter=1.4.1.2.8 RDY--Ready (p.37)}}</ref> This quirk was corrected in the CMOS derivatives and also in the 6510 and its variants.

==See also==
* [[Comparison of assemblers#6502 assemblers|List of 6502 assemblers]]
* [[List of home computers by category#MOS Technology 6502|MOS Technology 6502-based home computers]]
* [[Transistor count]]
* [[Apple II accelerators]]
* [[cc65]] – 6502 macro assembler and C compiler

==Notes==
{{Notelist}}

==References==
===Citations===
{{Reflist}}

===Bibliography===
* {{Cite interview
 |title=Oral History of Chuck Peddle
 |last=Peddle
 |first=Chuck
 |interviewer=Doug Fairbairn and Stephen Diamond
 |date=12 June 2014
 |url=https://www.youtube.com/watch?v=enHF9lMseP8
 |archive-url=https://ghostarchive.org/varchive/youtube/20211118/enHF9lMseP8 |archive-date=2021-11-18 |url-status=live |ref=CITEREFInterview2014
}}{{cbignore}}
* {{cite book
 |last=Bagnall |first=Brian
 |title=Commodore, a company on the edge
 |publisher=Variant Press
 |edition=2nd |year=2010
 |location=Winnipeg, Manitoba
 |isbn=978-0-9738649-6-0}}
* {{cite interview
 |title=Motorola 6800 Oral History Panel
 |url=https://archive.computerhistory.org/resources/access/text/2015/06/102702020-05-01-acc.pdf
 |last1=Bennett
 |first1=Thomas
 |last2=Ekiss
 |first2=John
 |last3=Lattin
 |first3=William (Bill)
 |last4=Lavell
 |first4=Jeff
 |date=28 March 2008
 |interviewer=David Laws
 |access-date=2021-01-30
 |archive-date=2021-04-13
 |archive-url=https://web.archive.org/web/20210413223530/https://archive.computerhistory.org/resources/access/text/2015/06/102702020-05-01-acc.pdf
 |url-status=live
 }}
* {{Cite journal
 |last=Cushman |first=Robert H.
 |author-link=Robert H. Cushman
 |title=2-1/2 Generation μP's -$10 Parts That Perform Like Low-End Mini's
 |journal=EDN
 |volume=20 |issue=17
 |pages=36–42
 |publisher=Cahners Publishing
 |location=Boston
 |date=September 20, 1975
 |url=http://www.swtpc.com/mholley/Microprocessors/EDN_Sep_20_1975_6502.pdf
 |archive-url=https://web.archive.org/web/20160424050556/http://www.swtpc.com/mholley/Microprocessors/EDN_Sep_20_1975_6502.pdf
 |archive-date=24 April 2016
}}
*[https://web.archive.org/web/20120508024231/http://silicongenesis.stanford.edu/complete_listing.html Interview with William Mensch] Stanford and the Silicon Valley Project, October 9, 1995. [https://web.archive.org/web/20160304091031/http://silicongenesis.stanford.edu/transcripts/mensch.htm Transcript]

==Further reading==
;Datasheets and manuals
* ''[https://archive.org/details/mos_6500_mpu_preliminary_may_1976 6500 Series Datasheet]''; MOS Technology; 12 pages; 1976.
* ''[http://bytecollector.com/archive/misc/6500-10A_MCS6500hwMan_Jan76.pdf 6500 Series Hardware Manual] {{Webarchive|url=https://web.archive.org/web/20110913045342/http://bytecollector.com/archive/misc/6500-10A_MCS6500hwMan_Jan76.pdf |date=2011-09-13 }}''; 2nd Ed; MOS Technology; 182 pages; 1976.
* ''[http://bytecollector.com/archive/misc/6500-50A_MCS6500pgmManJan76.pdf 6500 Series Programming Manual] {{Webarchive|url=https://web.archive.org/web/20110913045402/http://bytecollector.com/archive/misc/6500-50A_MCS6500pgmManJan76.pdf |date=2011-09-13 }}''; 2nd Ed; MOS Technology; 262 pages; 1976.
;Books
* ''6502 Applications Book''; 1st Ed; [[Rodnay Zaks]]; Sybex; 281 pages; 1979; {{ISBN|978-0895880154}}. [https://archive.org/details/6502_Applications_Book/ (archive)]
* ''6502 Assembly Language Programming''; 2nd Ed; Lance Leventhal; Osborne/McGraw-Hill; 650 pages; 1986; {{ISBN|978-0078812163}}. [https://archive.org/details/6502-assembly-language-programming/ (archive)]
* ''6502 Assembly Language Subroutines''; 1st Ed; Lance Leventhal and Winthrop Saville; Osborne/McGraw-Hill; 550 pages; 1982; {{ISBN|978-0931988592}}. [https://archive.org/details/6502_Assembly_Language_Subroutines/ (archive)]
* ''6502 Games''; 1st Ed; Rodnay Zaks; Sybex; 292 pages; 1980; {{ISBN|978-0895880222}}. [https://archive.org/details/6502GamesRodnayZaks/ (archive)]
* ''6502 User's Manual''; 1st Ed; Joseph Carr; Reston; 288 pages; 1984; {{ISBN|978-0835970020}}. [https://archive.org/details/6502UsersManual/ (archive)]
* ''Advanced 6502 Programming''; 1st Ed; Rodnay Zaks; John Wiley & Sons; 292 pages; 1982; {{ISBN|978-0895880895}}. [https://archive.org/details/Advanced_6502_Programming/ (archive)]
* ''Machine Language For Beginners – Personal Computer Machine Language Programming For Atari, VIC, Apple, C64, and PET Computers''; 1st Ed; Richard Mansfield; Compute! Publications; 350 pages; 1983; {{ISBN|978-0942386110}}. [http://www.atariarchives.org/mlb/ (archive)] {{Webarchive|url=https://web.archive.org/web/20160810124305/http://www.atariarchives.org/mlb/ |date=2016-08-10 }}
* ''Programming the 6502''; 4th Ed; Rodnay Zaks; Sybex; 408 pages; 1983; {{ISBN|978-0895881359}}. [https://archive.org/details/Programming_the_6502_OCR/ (archive)]
* ''Programming the [[65816]] – including the 6502, [[65C02]], [[65802]]''; 1st Ed; David Eyes and Ron Lichty; Prentice Hall; 636 pages; 1986; {{ISBN|978-0893037895}}. [https://archive.org/details/0893037893ProgrammingThe65816/ (archive)]
* ''Microprocessors and Assembly Language''; Turkish; 7th Ed; Nurettin Topaloglu; Seckin Yayinevi; 328 pages; 2021; {{ISBN|978-975-02-6663-8}}.
;Reference cards
* ''6502 Microprocessor Instant Reference Card''; James Lewis; Micro Logic; 2 pages; 1980. [http://www.atarimania.com/documents/6502%20(65xx)%20Microprocessor%20Instant%20Reference%20Card.jpg (archive)] {{Webarchive|url=https://web.archive.org/web/20190904042615/http://www.atarimania.com/documents/6502%20(65xx)%20Microprocessor%20Instant%20Reference%20Card.jpg |date=2019-09-04 }}

==External links==
{{Wikibooks|6502 Assembly}}
{{Commons category|6502 microprocessor}}
* [http://www.6502.org/ 6502.org – the 6502 microprocessor resource] {{Webarchive|url=https://web.archive.org/web/20201129185700/http://www.6502.org/ |date=2020-11-29 }} – repository 
* [https://web.archive.org/web/20181004202006/https://www.commodore.ca/history/company/mos/mos_technology.htm The Rise of MOS Technology & The 6502] – Commodore archive
* [http://www.cpu-collection.de/?tn=1&l0=cl&l1=650x 650x information] {{Webarchive|url=https://web.archive.org/web/20200311235418/http://www.cpu-collection.de/?tn=1&l0=cl&l1=650x |date=2020-03-11 }} – Concise description, photos of MOS and second source chips; at cpu-collection.de
* [https://web.archive.org/web/20090113222331/http://mdfs.net/Docs/Comp/6502/ mdfs.net] – 6502 instruction set
* {{cite web |title=6502 – the first RISC µP |url=http://ericclever.com/6500/ |last=Clever |first=Eric |archive-url=https://web.archive.org/web/20120524112833/http://ericclever.com/6500/ |archive-date=24 May 2012 |url-status=dead}}
* {{cite magazine |last=Harrod |first=Dennette A. |url=http://www.wiz-worx.com/resume/byte8010.htm |title=6502 Gets Microprogrammable Instructions |magazine=[[Byte (magazine)|Byte]] |date=October 1980 |publisher=[[McGraw Hill]] |issn=0360-5280 |volume=5 |issue=10 |pages=282–285 |access-date=2006-05-14 |archive-url=https://web.archive.org/web/20060525053048/http://wiz-worx.com/resume/byte8010.htm |archive-date=2006-05-25 |url-status=dead}}
;Simulators, emulators
* [http://6502asm.com/ Online 6502 compatible assembler and emulator, written in JavaScript] {{Webarchive|url=https://web.archive.org/web/20110208004832/http://6502asm.com/ |date=2011-02-08}}
* [http://www.zophar.net/6502.html List of 6502 software emulators] {{Webarchive|url=https://web.archive.org/web/20200919032922/http://www.zophar.net/6502.html |date=2020-09-19 }} – Zophar's Domain
* [http://atarihq.com/danb/6502.shtml 6502 simulator for Windows] {{Webarchive|url=https://web.archive.org/web/20041204171239/http://atarihq.com/danb/6502.shtml |date=2004-12-04 }} – Atari Gaming Headquarters
* [http://www.visual6502.org/ Visual Transistor-level Simulation of 6502 CPU] {{Webarchive|url=https://web.archive.org/web/20110314114737/http://www.visual6502.org/ |date=2011-03-14 }}
* {{GitHub|MicroCoreLabs/Projects/tree/master/MCL65|MCL65 6502 CPU core, C code}} – MicroCore Labs
;Boards
* [http://searle.x10host.com/6502/Simple6502.html Grant's 7/8-chip 6502 board] {{Webarchive|url=https://web.archive.org/web/20220606014503/http://searle.x10host.com/6502/Simple6502.html |date=2022-06-06 }}
* [http://www.kswichit.com/6502/6502.html 6502 microprocessor training board] {{Webarchive|url=https://web.archive.org/web/20190714012420/http://www.kswichit.com/6502/6502.html |date=2019-07-14 }}
* [http://www.6502.org/trainers/ Build your own KIM-1 training board] {{Webarchive|url=https://web.archive.org/web/20190714012420/http://www.6502.org/trainers/ |date=2019-07-14 }} – see [[KIM-1]]
* {{GitHub|grappendorf/homecomputer-6502|6502 home computer}}
* [http://putnamelectronics.com/products.html PE6502 single board computer] {{Webarchive|url=https://web.archive.org/web/20200503122709/http://putnamelectronics.com/products.html |date=2020-05-03 }}
* {{GitHub|tebl/BE6502-Build-a-65c02-computer|BE6502 single board computer}} – based on Ben Eater videos
;FPGA
* [https://opencores.org/projects/cpu6502_true_cycle cpu6502_tc 6502 CPU core – VHDL source code] – OpenCores
* [https://opencores.org/projects/ag_6502 ag_6502 6502 CPU core – Verilog source code] {{Webarchive|url=https://web.archive.org/web/20200804093306/https://opencores.org/projects/ag_6502 |date=2020-08-04 }} – OpenCores
* [https://opencores.org/projects/m65c02 M65C02 65C02 CPU core – Verilog source code] {{Webarchive|url=https://web.archive.org/web/20200804103904/https://opencores.org/projects/m65c02 |date=2020-08-04 }} – OpenCores
* {{GitHub|MicroCoreLabs/Projects/tree/master/MCL65|MCL65 6502 CPU core}} – Verilog – MicroCore Labs

{{MOS CPU}}
{{Authority control}}

{{DEFAULTSORT:Mos Technology 6502}}
[[Category:MOS Technology microprocessors]]
[[Category:65xx microprocessors]]
[[Category:Computer-related introductions in 1975]]
[[Category:8-bit microprocessors]]