Editing MOS Technology 6510

{{Short description|8-bit microprocessor}}
{{Use mdy dates|date=January 2016}}
{{redirect|6510|the mobile phone|Nokia 6510}}
{{Infobox CPU
|name           = MOS Technology 6510
|image          = KL MOS 6510.jpg
|caption        = 
|produced-start = 
|produced-end   = 
|slowest        = 0.985  | slow-unit = MHz
|fastest        = 1.023  | fast-unit = MHz <!-- check -->
|data-width     = 8
|address-width  = 16
|manuf1         = [[MOS Technology]], [[Rockwell International|Rockwell]], [[Synertek]]
|arch           = MOS 6502
|pack1          = 40-pin [[Dual in-line package|DIP]]
|predecessor    = [[MOS Technology 6502|MOS 6502]]
|successor      = [[MOS Technology 8502|MOS 8502]]
|variant        = MOS 8500, 7501/8501, 8502, 6510T
}}
[[image:MOS Technologies large.jpg|thumb|300px|Image of the internals of a Commodore 64 showing the 6510 CPU (40-pin DIP, lower left). The chip on the right is the [[MOS Technology SID|6581 SID]]. The production week/year (WWYY) of each chip is given below its name.]]

The '''MOS Technology 6510''' is an [[8-bit computing|8-bit]] [[microprocessor]] designed by [[MOS Technology]]. It is a modified form of the very successful [[MOS Technology 6502|6502]]. The 6510 is widely used in the [[Commodore 64]] (C64) [[home computer]] and its variants. It is also used in the [[Seagate ST-251]] MFM harddisk.<ref>[https://github.com/ForgottenMachines/Seagate/blob/main/ST-251/Seagate_ST251_schematic.pdf ST-251 schematic]</ref>

The primary change from the 6502 is the addition of an 8-bit general purpose [[input/output|I/O]] port, although 6 I/O pins are available in the most common version of the 6510. In addition, the address bus can be made [[three-state logic|tristate]] and the CPU can be halted cleanly.

==Use==
In the C64, the extra I/O pins of the processor are used to control the computer's [[memory map]] by [[bank switching]], and for controlling three of the four signal lines of the [[Commodore Datasette|Datasette]] tape recorder (the electric motor control, key-press sensing and write data lines; the read data line went to another I/O chip).  It is possible, by writing the correct [[bit pattern]] to the processor at address $01, to completely expose almost the full 64&nbsp;[[kilobyte|KB]] of [[Random-access memory|RAM]] in the C64, leaving no [[Read-only memory|ROM]] or [[I/O]] hardware exposed except for the processor I/O port itself and its data directional register at address $00.<ref>{{cite magazine |url=http://www.atarimagazines.com/compute/issue32/112_1_COMMODORE_64_ARCHITECTURE.php |title=Commodore 64 Architecture |first=Jim|last=Butterfield |magazine=Compute! |date=January 1983 |page=208 |issue=32}}</ref>

==Variants==
[[Image:6510 CPU Pinout.svg|thumb|300px|Pin configuration of the most common variation of the 6510 CPU (/HALT in this image refers to the RDY pin.)]]

=== MOS 8500 {{anchor|8500}} ===
In 1985, MOS produced the '''8500''', an [[HMOS]] version of the 6510. Other than the process modification, it is virtually identical to the [[NMOS logic|NMOS]] version of the 6510. The 8500 was originally designed for use in the modernised C64, the C64C. However, in 1985, limited quantities of 8500s were found on older NMOS-based C64s. It finally made its official debut in 1987, appearing in a motherboard using the new 85xx HMOS chipset.

=== MOS 7501/8501 {{anchor|7501|8501}} ===
[[File:MOS8501R1.jpg|thumb|MOS 8501 CPU]]
The '''7501/8501''' variant of the 6510 was introduced in 1984.<ref name="auto">[http://plus4world.powweb.com/hardware/MOS_75018501 Hardware – MOS 7501/8501]</ref> Compared to the 6510, this variant extends the number of I/O port pins from 6 to 8, but omits the pins for non-maskable interrupt and clock output.<ref>[https://ist.uwaterloo.ca/~schepers/MJK/7501.html  CPU 7501 / 8501]</ref>   It is used in Commodore's [[Commodore 16|C16]], [[Commodore 16|C116]] and [[Commodore Plus/4|Plus/4]] home computers, where its I/O port controls not only the [[Commodore Datasette|Datasette]] but also the [[Commodore 1541#Interface|CBM Bus]] interface. The main difference between 7501 and 8501 CPUs is that they were manufactured with slightly different processes: 7501 was manufactured with [[HMOS|HMOS-1]] and 8501 with HMOS-2.<ref name="auto"/>

=== MOS 8502 {{anchor|8502}} ===
{{mainarticle|MOS Technology 8502}}
The 2&nbsp;[[Hertz|MHz]]-capable [[MOS Technology 8502|8502]] variant is used in the [[Commodore 128]]. All these CPUs are [[opcode]] compatible (including [[illegal opcode|undocumented opcodes]]).<ref>{{cite web|url=http://www.oxyron.de/html/opcodes02.html|title=6502/6510/8500/8502 Opcodes|last=Graham|website=www.oxyron.de}}</ref>

=== MOS 6510T {{anchor|6510T}} ===
The [[Commodore 1551]] disk drive (for the [[Commodore Plus/4]]) uses the '''6510T''', a version of the 6510 with eight I/O lines. The [[Non-maskable interrupt|NMI]] and RDY signals are not available.

==See also==
* [[Interrupts in 65xx processors]]

==References==
{{Reflist}}

==Further reading==
{{See also|MOS Technology 6502#Further reading|l1=List of books about 65xx microprocessor families}}

==External links==
* [http://www.devili.iki.fi/pub/Commodore/docs/datasheets/CSG/6510-8211_rev_a.zip MOS 6510 datasheet (GIF format, zipped)]
* [http://www.6502.org/documents/datasheets/mos/mos_6510_mpu.pdf MOS 6510 datasheet (PDF format)]
* [http://www.6502.org/documents/datasheets/mos/mos_6510_mpu_nov_1982.pdf MOS 6510 datasheet (preliminary, Nov. 1982, PDF format)]
* {{webarchive |url=https://web.archive.org/web/20230227154421/https://twitter.com/Siliconinsid/status/1587897081649397764 |title=Siliconinsider@Twitter - Die shot of MOS Technology 6510 |date=February 27, 2023 
}}
* [http://fms.komkon.org/EMUL8/ komkon.org - Computer Emulation Resources] (includes downloadable source code for 6502)
* {{webarchive |url=https://web.archive.org/web/20180728124917/http://www.c64web.com/ |date=July 28, 2018 |title=Web server using a MOS 6510 computer (aka C64) }}

{{MOS CPU}}

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[[Category:65xx microprocessors]]
[[Category:MOS Technology microprocessors]]
[[Category:Commodore 64]]
[[Category:8-bit microprocessors]]