Editing PCI Express

{{short description|Computer expansion bus standard}}
{{Distinguish|PCI-X|UCIe}}
{{For|Engineering, Procurement, Construction and Installation|EPCI}}
{{use dmy dates |date=October 2020}}
{{Infobox computer hardware bus
| name = PCI Express
| fullname = Peripheral Component Interconnect Express
| image = PCI Express.svg{{!}}class=skin-invert
| invent-date = {{Start date and age|2003}}
| invent-name = {{Hlist
  | [[Intel]]
  | [[Dell]]
  | [[Hewlett-Packard|HP]]
  | [[IBM]]
  }}
| super-name =
| super-date =
| replaces = {{Hlist
  | [[Peripheral Component Interconnect|PCI]]
  | [[PCI-X]]
  | [[Accelerated Graphics Port|AGP]]
  }}
| width = 1 per lane<ref name="auto">{{cite book | url=https://books.google.com/books?id=ZjyrAgAAQBAJ&dq=pcie+dual+simplex&pg=PA69 | isbn=978-0-7384-5121-3 | title=IBM Power 770 and 780 Technical Overview and Introduction | date=6 June 2013 | publisher=IBM Redbooks }}</ref> {{Small|(up to 16 lanes)}}
| numdev = 1 on each endpoint of each connection.{{Efn|Switches can create multiple endpoints out of one to allow sharing it with multiple devices.}}
| speed = [[Dual simplex]], up to 242&nbsp;GB/s
| style = s
| hotplug = Optional {{Small|(support with [[ExpressCard]], [[#PCI Express OCuLink|OCuLink]], [[CFexpress]] or [[U.2]])}}
| external = Optional {{Small|(support with [[#PCI Express OCuLink|OCuLink]] or [[#PCI Express External Cabling|PCI Express External Cabling]])}}
| website = {{URL|https://pcisig.com/}}
}}
[[File:LSI_9207-4i4e_PCI-E_SAS_HBA.jpg|thumb|A PCIe 3.0 x8 [[host bus adapter]]]]

[[File:PCI-E & PCI slots on DFI LanParty nF4 SLI-DR 20050531.jpg|thumb|Various slots on a [[computer motherboard]], from top to bottom: {{unordered list
 | PCI Express x4
 | PCI Express x16
 | PCI Express x1
 | PCI Express x16
 | [[Conventional PCI]] (32-bit, 5&nbsp;V)
}}]]

'''PCI Express''' ('''Peripheral Component Interconnect Express'''), officially abbreviated as '''PCIe''' or '''PCI-E''',<ref name="s5NDG" /> is a high-speed [[serial communication|serial]] [[computer]] [[expansion bus]] standard, meant to replace the older [[Conventional PCI|PCI]], [[PCI-X]] and [[Accelerated Graphics Port|AGP]] bus standards. It is the common [[motherboard]] interface for personal computers' [[Video card|graphics cards]], [[Capture card|capture cards]], [[sound card]]s, [[hard disk drive]] [[host adapter]]s, [[Solid-state drive|SSDs]], [[Wi-Fi]], and [[Ethernet]] hardware connections.<ref name="DQmzv" /> PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count, smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER),<ref name="gf9Lm" /> and native [[Hot swapping|hot-swap]] functionality. More recent revisions of the PCIe standard provide hardware support for [[I/O virtualization]].

The PCI Express electrical interface is measured by the number of simultaneous lanes.<ref name="sxOen"/> (A lane is a set of send and receive data lines, analogous to a road having one lane of traffic in each direction.) The interface is also used in a variety of other standards — most notably the [[laptop]] expansion card interface called [[ExpressCard]]. It is also used in the storage interfaces of [[SATA Express]], [[U.2]] (SFF-8639) and [[M.2]].

Formal specifications are maintained and developed by the [[PCI-SIG]] (PCI [[Special Interest Group]]) — a group of more than 900 companies that also maintains the [[conventional PCI]] specifications.

== Architecture <span class="anchor" id="SWITCH"></span> ==
[[File:Example PCI Express Topology.svg|thumb|upright=1.25|Example of the PCI&nbsp;Express topology:<br />white "junction boxes" represent PCI&nbsp;Express device downstream ports. The gray ones represent upstream ports.<ref name="pcie-basics" />{{rp|7}}]]
[[File:RouterBOARD RB14e, top view.jpg|thumb|upright=1.25|PCI Express x1 card containing a PCI Express switch (covered by a small [[heat sink]]), which creates multiple endpoints out of one endpoint and lets multiple devices share it]]

[[File:PCie lanes.jpg|thumb|The PCIe slots on a motherboard are often labeled with the number of PCIe lanes they have. Sometimes what may seem like a large slot may only have a few lanes. For instance, a x16 slot with only 4 PCIe lanes (bottom slot) is quite common.<ref>{{cite web |title=What are PCIe Slots and Their Uses |date=18 May 2021 |url=https://pcguide101.com/motherboard/what-are-pcie-slots/ |publisher=PC Guide 101 |access-date=21 June 2021}}</ref>]]

Conceptually, the PCI Express bus is a high-speed [[serial communication|serial]] replacement of the older PCI/PCI-X bus.<ref name="howstuffworks1" /> One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared [[parallel communications|parallel]] [[Bus (computing)|bus]] architecture, in which the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on point-to-point [[Network topology|topology]], with separate [[serial communication|serial]] links connecting every device to the [[root complex]] (host). Because of its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCI Express bus link supports [[Full-duplexed|full-duplex]] communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.

In terms of bus protocol, PCI Express communication is encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCI Express port (described later). Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors (and thus, new motherboards and new adapter boards); PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express preserves [[backward compatibility]] with PCI; legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the PCI Express standard, though new PCI Express features are inaccessible.

The PCI Express link between two devices can vary in size from one to 16 [[#Lane|lane]]s. In a multi-lane link, the packet data is striped across lanes, and peak data throughput scales with the overall link width. The lane count is automatically negotiated during device initialization and can be restricted by either endpoint. For example, a single-lane PCI Express (x1) card can be inserted into a multi-lane slot (x4, x8, etc.), and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure itself to use fewer lanes, providing a failure tolerance in case bad or unreliable lanes are present. The PCI Express standard defines link widths of x1, x2, x4, x8, and x16. Up to and including PCIe 5.0, x12, and x32 links were defined as well but virtually{{clarification needed|date=January 2025}} never used.<ref name="4TrCr" /> This allows the PCI Express bus to serve both cost-sensitive applications where high throughput is not needed, and performance-critical applications such as 3D graphics, networking ([[10 Gigabit Ethernet]] or multiport [[Gigabit Ethernet]]), and enterprise storage ([[Serial attached SCSI|SAS]] or [[Fibre Channel]]). Slots and connectors are only defined for a subset of these widths, with link widths in between using the next larger physical slot size.

As a point of reference, a PCI-X (133&nbsp;MHz 64-bit) device and a PCI Express&nbsp;1.0 device using four lanes (x4) have roughly the same peak single-direction transfer rate of 1064&nbsp;MB/s. The PCI Express bus has the potential to perform better than the PCI-X bus in cases where multiple devices are transferring data simultaneously, or if communication with the PCI Express peripheral is [[Two-way communication|bidirectional]].

=== Interconnect <span class="anchor" id="LINK"></span> ===
[[File:PCI Express Terminology.svg|thumb|A PCI Express link between two devices consists of one or more lanes, which are [[dual simplex]] channels using two [[differential signaling]] pairs.<ref name="pcie-basics" />{{rp|3}}]]

PCI Express devices communicate via a logical connection called an ''interconnect''<ref name="faq1" /> or ''link''. A link is a point-to-point communication channel between two PCI Express ports allowing both of them to send and receive ordinary PCI requests (configuration, I/O or memory read/write) and [[interrupt]]s ([[Peripheral Component Interconnect#Interrupts|INTx]], [[Message Signaled Interrupts|MSI or MSI-X]]). At the physical level, a link is composed of one or more ''lanes''.<ref name="faq1" /> Low-speed peripherals (such as an [[IEEE 802.11|802.11]] [[Wi-Fi]] [[Wireless network interface card|card]]) use a single-lane (x1) link, while a graphics adapter typically uses a much wider and therefore faster 16-lane (x16) link.

=== Lane <span class="anchor" id="LANE"></span> ===
A lane is composed of two [[differential signaling]] pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or [[signal trace]]s. Conceptually, each lane is used as a [[full-duplex]] [[byte stream]], transporting data packets in eight-bit "byte" format simultaneously in both directions between endpoints of a link.<ref name="2Nt8T" /> Physical PCI Express links may contain 1, 4, 8 or 16 lanes.<ref name="Gchhw" /><ref name="pcie-basics" />{{rp|4,5}}<ref name="faq1" /> Lane counts are written with an "x" prefix (for example, "x8" represents an eight-lane card or slot), with x16 being the largest size in common use.<ref name="odC7t" /> Lane sizes are also referred to via the terms "width" or "by" e.g., an eight-lane slot could be referred to as a "by 8" or as "8 lanes wide."

For mechanical card sizes, see [[#Form factors|below]].

=== Serial bus ===
{{unreferenced section|date=March 2018}}
The bonded serial [[Bus (computing)|bus]] architecture was chosen over the traditional parallel bus because of the inherent limitations of the latter, including [[half-duplex]] operation, excess signal count, and inherently lower [[Bandwidth (computing)|bandwidth]] due to [[timing skew]]. Timing skew results from separate electrical signals within a parallel interface traveling through conductors of different lengths, on potentially different [[printed circuit board]] (PCB) layers, and at possibly different [[Signal velocity|signal velocities]]. Despite being transmitted simultaneously as a single [[Word (data type)|word]], signals on a parallel interface have different travel duration and arrive at their destinations at different times. When the interface clock period is shorter than the largest time difference between signal arrivals, recovery of the transmitted word is no longer possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz.

[[File:PCIe vs PCI.gif|thumb|'''Highly simplified''' topologies of the Legacy PCI Shared (Parallel) Interface and the PCIe Serial Point-to-Point Interface<ref name="P7MD8" />]]

A serial interface does not exhibit timing skew because there is only one differential signal in each direction within each lane, and there is no external clock signal since clocking information is [[Clock recovery|embedded]] within the serial signal itself. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz range. PCI Express is one example of the general trend toward replacing parallel buses with serial interconnects; other examples include [[Serial ATA]] (SATA), [[USB]], [[Serial Attached SCSI]] (SAS), [[FireWire]] (IEEE 1394), and [[RapidIO]]. In digital video, examples in common use are [[Digital Visual Interface|DVI]], [[HDMI]], and [[DisplayPort]].

Multichannel serial design increases flexibility with its ability to allocate fewer lanes for slower devices.

== Form factors ==

=== PCI Express (standard) <span class="anchor" id="HHHL"></span><span class="anchor" id="FHHL"></span> ===
[[File:Intel P3608 NVMe flash SSD, PCI-E add-in card.jpg|thumb|Intel P3608 NVMe flash SSD, PCIe add-in card|alt=]]A PCI Express card fits into a slot of its physical size or larger (with x16 as the largest used), but may not fit into a smaller PCI Express slot; for example, a x16 card may not fit into a x4 or x8 slot. Some slots use open-ended sockets to permit physically longer cards and negotiate the best available electrical and logical connection.

The number of lanes actually connected to a slot may also be fewer than the number supported by the physical slot size. An example is a x16 slot that runs at x4, which accepts any x1, x2, x4, x8 or x16 card, but provides only four lanes. Its specification may read as "x16 (x4 mode)", while "mechanical @ electrical" notation (e.g. "x16&nbsp;@&nbsp;x4") is also common.{{Citation needed|date=July 2022}} The advantage is that such slots can accommodate a larger range of PCI Express cards without requiring motherboard hardware to support the full transfer rate. Standard mechanical sizes are x1, x4, x8, and x16. Cards using a number of lanes other than the standard mechanical sizes need to physically fit the next larger mechanical size (e.g. an x2 card uses the x4 size, or an x12 card uses the x16 size).

The cards themselves are designed and manufactured in various sizes. For example, [[solid-state drive]]s (SSDs) that come in the form of PCI Express cards often use [[Conventional PCI#Low-profile cards|HHHL]] (half height, half length) and [[Conventional PCI#Half-length full-height card|FHHL]] (full height, half length) to describe the physical dimensions of the card.<ref name="8AKZj" /><ref name="c1yve" />

{| class="wikitable"
|-
! rowspan=2" | PCI card type
! colspan="2" | Dimensions height × length × width, maximum
|-
! (mm)
! (in)
|-
| Full-Length
| 111.15 × 312.00 × 20.32
| 4.376 × 12.283 × 0.8
|-
| Half-Length
| 111.15 × 167.65 × 20.32
| 4.376 × {{0}}6.600 × 0.8
|-
| Low-Profile/Slim
| {{0}}68.90 × 167.65 × 20.32
| 2.731 × {{0}}6.600 × 0.8
|}

==== Non-standard video card form factors ====
Modern (since {{circa|2012}}<ref name="j6TTS" />) gaming [[video card]]s usually exceed the height as well as thickness specified in the PCI Express standard, due to the need for more capable and quieter [[Computer fan|cooling fans]], as gaming video cards often emit hundreds of watts of heat.<ref name="RAreG" /> Modern computer cases are often wider to accommodate these taller cards, but not always. Since full-length cards (312&nbsp;mm) are uncommon, modern cases sometimes cannot accommodate them. The thickness of these cards also typically occupies the space of 2 to 5<ref>{{Cite web |last=Discuss |first=btarunr |date=2023-01-06 |title=ASUS x Noctua RTX 4080 Graphics Card is 5 Slots Thick, We Go Hands-on |url=https://www.techpowerup.com/303148/asus-x-noctua-rtx-4080-graphics-card-is-5-slots-thick-we-go-hands-on |access-date=2024-09-19 |website=TechPowerUp |language=en}}</ref> PCIe slots. In fact, even the methodology of how to measure the cards varies between vendors, with some including the metal bracket size in dimensions and others not.

For instance, comparing three high-end video cards released in 2020: a [[Sapphire Technology|Sapphire]] [[Radeon RX 5000 series|Radeon RX 5700 XT]] card measures 135&nbsp;mm in height (excluding the metal bracket), which exceeds the PCIe standard height by 28&nbsp;mm,<ref name="E0Tsg" /> another Radeon RX 5700 XT card by [[XFX]] measures 55&nbsp;mm thick (i.e. 2.7 PCI slots at 20.32&nbsp;mm), taking up 3 PCIe slots,<ref name="mAt96" /> while an [[Asus]] [[GeForce 30 series|GeForce RTX 3080]] video card takes up two slots and measures 140.1{{nbsp}}mm × 318.5{{nbsp}}mm × 57.8{{nbsp}}mm, exceeding PCI Express's maximum height, length, and thickness respectively.<ref name="kk3xz" />

==== Pinout ====
The following table identifies the conductors on each side of the [[edge connector]] on a PCI Express card. The solder side of the [[printed circuit board]] (PCB) is the A-side, and the component side is the B-side.<ref name="IM1RH" /> PRSNT1# and PRSNT2# pins must be slightly shorter than the rest, to ensure that a hot-plugged card is fully inserted. The WAKE# pin uses full voltage to wake the computer, but must be [[pull up resistor|pulled high]] from the standby power to indicate that the card is wake capable.<ref name="PCIe card 2" />

{| class="wikitable"
|+ PCI Express connector pinout (x1, x4, x8 and x16 variants)
! Pin !! Side B !! Side A !! Description
| rowspan=54 |
! Pin !! Side B !! Side A !! Description
|-
! {{0}}1
|style="background:silver"| +12&nbsp;V || style="background:#9f9"| PRSNT1# ||align="left"| Must connect to farthest PRSNT2# pin
! 50
|style="background:#99f"| HSOp(8) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 8 transmit data, + and −
|-
! {{0}}2
|style="background:silver"| +12&nbsp;V ||style="background:silver"| +12&nbsp;V || rowspan="2" style="text-align:left;"|Main power pins
! 51
|style="background:#99f"| HSOn(8) ||style="background:#999"| Ground
|-
! {{0}}3
|style="background:silver"| +12&nbsp;V ||style="background:silver"| +12&nbsp;V
! 52
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(8) || rowspan="2" style="text-align:left;"| Lane 8 receive data, + and −
|-
! {{0}}4
|style="background:#999"| Ground ||style="background:#999"| Ground ||
! 53
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(8)
|-
! {{0}}5
|style="background:#fc6"| SMCLK ||style="background:#99f"| TCK || rowspan="5" style="text-align:left;"| [[SMBus]] and [[JTAG]] port pins
! 54
|style="background:#99f"| HSOp(9) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 9 transmit data, + and −
|-
! {{0}}6
|style="background:#fc6"| SMDAT ||style="background:#99f"| TDI
! 55
|style="background:#99f"| HSOn(9) ||style="background:#999"| Ground
|-
! {{0}}7
|style="background:#999"| Ground ||style="background:#f9f"| TDO
! 56
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(9) || rowspan="2" style="text-align:left;"| Lane 9 receive data, + and −
|-
! {{0}}8
|style="background:silver"| +3.3&nbsp;V ||style="background:#99f"| TMS
! 57
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(9)
|-
! {{0}}9
|style="background:#99f"| TRST# ||style="background:silver"| +3.3&nbsp;V
! 58
|style="background:#99f"| HSOp(10) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 10 transmit data, + and −
|-
! 10
|style="background:silver"|+3.3&nbsp;V aux ||style="background:silver"| +3.3&nbsp;V ||align="left"| Aux power & [[Standby power]]
! 59
|style="background:#99f"| HSOn(10) ||style="background:#999"| Ground
|-
! 11
|style="background:#fc6"| WAKE# ||style="background:#fc6"| PERST# ||align="left"| Link reactivation; fundamental reset <ref name="ajnim" />
! 60
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(10) || rowspan="2" style="text-align:left;"| Lane 10 receive data, + and −
|-
!colspan=4| Key notch
! 61
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(10)
|-
! 12
|style="background:#f9f"| CLKREQ#<ref name="vj2hg" /> ||style="background:#999"| Ground ||align="left"| Clock Request Signal
! 62
|style="background:#99f"| HSOp(11) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 11 transmit data, + and −
|-
! 13
|style="background:#999"| Ground ||style="background:#99f"| REFCLK+ ||align="left"| Reference clock differential pair
! 63
|style="background:#99f"| HSOn(11) ||style="background:#999"| Ground
|-
! 14
|style="background:#99f"| HSOp(0) ||style="background:#99f"| REFCLK− || rowspan="2" style="text-align:left;"| Lane 0 transmit data, + and −
! 64
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(11) || rowspan="2" style="text-align:left;"| Lane 11 receive data, + and −
|-
! 15
|style="background:#99f"| HSOn(0) ||style="background:#999"| Ground
! 65
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(11)
|-
! 16
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(0) || rowspan="2" style="text-align:left;"| Lane 0 receive data, + and −
! 66
|style="background:#99f"| HSOp(12) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 12 transmit data, + and −
|-
! 17
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(0)
! 67
|style="background:#99f"| HSOn(12) ||style="background:#999"| Ground
|-
! 18
|style="background:#999"| Ground ||style="background:#999"| Ground ||
! 68
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(12) || rowspan="2" style="text-align:left;"| Lane 12 receive data, + and −
|-
|colspan=4| PCI Express x1 cards end at pin 18
! 69
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(12)
|-
! 19
|style="background:#99f"| HSOp(1) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 1 transmit data, + and −
! 70
|style="background:#99f"| HSOp(13) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 13 transmit data, + and −
|-
! 20
|style="background:#99f"| HSOn(1) ||style="background:#999"| Ground
! 71
|style="background:#99f"| HSOn(13) ||style="background:#999"| Ground
|-
! 21
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(1) || rowspan="2" style="text-align:left;"| Lane 1 receive data, + and −
! 72
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(13) || rowspan="2" style="text-align:left;"| Lane 13 receive data, + and −
|-
! 22
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(1)
! 73
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(13)
|-
! 23
|style="background:#99f"| HSOp(2) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 2 transmit data, + and −
! 74
|style="background:#99f"| HSOp(14) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 14 transmit data, + and −
|-
! 24
|style="background:#99f"| HSOn(2) ||style="background:#999"| Ground
! 75
|style="background:#99f"| HSOn(14) ||style="background:#999"| Ground
|-
! 25
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(2) || rowspan="2" style="text-align:left;"| Lane 2 receive data, + and −
! 76
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(14) || rowspan="2" style="text-align:left;"| Lane 14 receive data, + and −
|-
! 26
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(2)
! 77
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(14)
|-
! 27
|style="background:#99f"| HSOp(3) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 3 transmit data, + and −
! 78
|style="background:#99f"| HSOp(15) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 15 transmit data, + and −
|-
! 28
|style="background:#99f"| HSOn(3) ||style="background:#999"| Ground
! 79
|style="background:#99f"| HSOn(15) ||style="background:#999"| Ground
|-
! 29
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(3) || rowspan="2" style="text-align:left;"| Lane 3 receive data, + and −<br />"Power brake", active-low to reduce device power
! 80
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(15) || rowspan="2" style="text-align:left;"| Lane 15 receive data, + and −
|-
! 30
|style="background:#fc6"| PWRBRK#<ref name="YpQVq" /> ||style="background:#f9f"| HSIn(3)
! 81
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(15)
|-
! 31
|style="background:#9f9"| PRSNT2# ||style="background:#999"| Ground ||rowspan=2|
! 82
|style="background:#ff9"| Reserved ||style="background:#999"| Ground ||
|-
! 32
|style="background:#999"| Ground ||style="background:#ff9"| Reserved
|-
|colspan=4| PCI Express x4 cards end at pin 32
|-
! 33
|style="background:#99f"| HSOp(4) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 4 transmit data, + and −
|-
! 34
|style="background:#99f"| HSOn(4) ||style="background:#999"| Ground
|-
! 35
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(4) || rowspan="2" style="text-align:left;"| Lane 4 receive data, + and −
|-
! 36
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(4)
|-
! 37
|style="background:#99f"| HSOp(5) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 5 transmit data, + and −
|-
! 38
|style="background:#99f"| HSOn(5) ||style="background:#999"| Ground
|-
! 39
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(5) || rowspan="2" style="text-align:left;"| Lane 5 receive data, + and −
|-
! 40
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(5)
|-
! 41
|style="background:#99f"| HSOp(6) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 6 transmit data, + and −
|-
! 42
|style="background:#99f"| HSOn(6) ||style="background:#999"| Ground
|-
! 43
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(6) || rowspan="2" style="text-align:left;"| Lane 6 receive data, + and −
!colspan=4| Legend
|-
! 44
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(6)
!style="background:#999" colspan=2| Ground pin
| colspan="2" style="text-align:left;"| Zero volt reference
|-
! 45
|style="background:#99f"| HSOp(7) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 7 transmit data, + and −
!style="background:silver" colspan=2| Power pin
| colspan="2" style="text-align:left;"| Supplies power to the PCIe card
|-
! 46
|style="background:#99f"| HSOn(7) ||style="background:#999"| Ground
!style="background:#f9f" colspan=2| Card-to-host pin
| colspan="2" style="text-align:left;"| Signal from the card to the motherboard
|-
! 47
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(7) || rowspan="2" style="text-align:left;"| Lane 7 receive data, + and −
!style="background:#99f" colspan=2| Host-to-card pin
| colspan="2" style="text-align:left;"| Signal from the motherboard to the card
|-
! 48
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(7)
!style="background:#fc6" colspan=2| [[Open drain]]
| colspan="2" style="text-align:left;"| May be pulled low or sensed by multiple cards
|-
! 49
|style="background:#999"| Ground ||style="background:#999"| Ground ||
!style="background:#9f9" colspan=2| Sense pin
| colspan="2" style="text-align:left;"| Tied together on card
|-
|colspan=4| PCI Express x8 cards end at pin 49
!style="background:#ff9" colspan=2| Reserved
| colspan="2" style="text-align:left;"| Not presently used, do not connect
|}

==== Power ====
[[File:Powering of PCIe Slot.png|thumb|upright=1.25|The main {{val|12|ul=V}} power supply for the PCIe slot is pins B2, B3 (side B) and pins A2, A3 (side A). Power standby {{val|3.3|ul=V}} is pin B10 and A10. PCIe x1 cards can draw up to {{val|25|ul=W}} and x16 graphics cards can draw up to {{val|75|ul=W}}, combined.<ref>{{cite web |date=2022-01-16 |title=Where Does PCIe Cable Go? |url=https://greatpcreview.com/guides/where-does-pcie-cables-go/ |access-date=2022-06-10 |language=en-US}}</ref>]]

===== Slot power =====
<!--
Please DO NOT add the claim that the PCI express 2.x standard adds support for up to 150&nbsp;W from the slot itself without a very good reference. While several references make the claim, particularly around the time of release, other references particularly those relying on the spec. dispute this. See the talk page discussion dated November 2012 for details.
-->
All PCI express cards may consume up to {{val|3|ul=A}} at {{val|+3.3|ul=V}} ({{val|9.9|ul=W}}). The amount of +12&nbsp;V and total power they may consume depends on the form factor and the role of the card:<ref name="CEM1.1" />{{rp|35–36}}<ref name="jArAO" /><ref>''PCI Express Base Specification, Revision 1.1'' Page 332</ref>
* x1 cards are limited to 0.5&nbsp;A at +12{{nbsp}}V (6&nbsp;W) and 10&nbsp;W combined.
* x4 and wider cards are limited to 2.1&nbsp;A at +12{{nbsp}}V (25&nbsp;W) and 25&nbsp;W combined.
* A full-sized x1 card may draw up to the 25&nbsp;W limits after initialization and software configuration as a high-power device.
* A full-sized x16 graphics card may draw up to 5.5&nbsp;A at +12{{nbsp}}V (66&nbsp;W) and 75&nbsp;W combined after initialization and software configuration as a high-power device.<ref name="PCIe card 2" />{{rp|38–39}}

===== 6- and 8-pin power connectors =====
[[File:PCI Express Power Supply Connector-female PNr°0438.jpg|thumb|upright=1.25|8-pin (left) and 6-pin (right) [[Molex Mini-fit Jr.|power connectors]] used on PCI Express cards]]

Optional connectors add {{val|75|ul=W}} (6-pin) or {{val|150|ul=W}} (8-pin) of +12&nbsp;V power for up to {{val|300|ul=W}} total ({{nowrap|2 @ 75&nbsp;W + 1 @ 150&nbsp;W}}).
* Sense0 pin is connected to ground by the cable or power supply, or float on board if cable is not connected.
* Sense1 pin is connected to ground by the cable or power supply, or float on board if cable is not connected.

Some cards use two 8-pin connectors, but that has not been standardized {{as of|lc=y|2018}}. Therefore, such cards must not carry the official PCI Express logo. This configuration allows 375&nbsp;W total ({{nowrap|1 @ 75&nbsp;W + 2 @ 150&nbsp;W}}) and will likely be standardized by PCI-SIG with the PCI Express 4.0 standard.{{Update inline|reason=PCI Express is at 5.0 already…|date=May 2021}} The 8-pin PCI Express connector should not be confused with the [[EPS12V]] connector, which is mainly used for powering SMP and multi-core systems. The power connectors are variants of the Molex Mini-Fit Jr. series connectors.<ref name="JuErgh" />
{| class="wikitable" style="background:white; border:0"
|+ Molex Mini-Fit Jr. part numbers<ref name="JuErgh" />
! Pins
! Female/receptacle <br />on PS cable
!Male/right-angle <br />header on PCB
|-
|6-pin
|45559-0002
|45558-0003
|-
|8-pin
|45587-0004
|45586-0005, 45586-0006
|}
{| class="wikitable" style="border:0"
! colspan=2 style="background:white; border:0" | 6-pin power connector (75&nbsp;W)<ref name="o2GFI" />
| rowspan=10 style="border:0; background:white"|
! colspan=2 style="background:white; border:0" | 8-pin power connector (150&nbsp;W)<ref name="uLc7Q" /><ref name="CEM3.0" /><ref name="mcd6L" />
| rowspan=10 style="border:0;background:white"| [[File:PCIe6connector.svg|thumb|185px|<small>6 pin power connector pin map</small>]]<br />
                               [[File:PCIe8connector.svg|thumb|224px|&emsp;&emsp;<small>8 pin power connector pin map</small>]]
|-
! Pin !! Description
! Pin !! Description
|-
| {{0}}1 || +12&nbsp;V
| {{0}}1 || +12&nbsp;V
|-
| {{0}}2 || {{n/a|Not connected (usually +12&nbsp;V as well)}}
| {{0}}2 || +12&nbsp;V
|-
| {{0}}3 || +12&nbsp;V
| {{0}}3 || +12&nbsp;V
|-
| colspan=2 style="background:white; border:0" |
| {{0}}4 || Sense1 (8-pin connected{{efn-ua|When a 6-pin connector is plugged into an 8-pin receptacle the card is notified by a missing ''Sense1'' that it may only use up to 75&nbsp;W.}})
|-
| {{0}}4 || Ground
| {{0}}5 || Ground
|-
| {{0}}5 || Sense
| {{0}}6 || Sense 0 (6-pin or 8-pin connected)
|-
| {{0}}6 || Ground
| {{0}}7 || Ground
|-
| colspan=2 style="background:white; border:0" |
| {{0}}8 || Ground
|}
{{notelist-ua}}

===== 12VHPWR connector =====
{{Excerpt|16-Pin 12vHPWR connector|templates=-Advert}}

===== 48VHPWR connector =====
In 2023 PCIe CEM 5.1 introduced a connector for 48 Volts with two current-carrying contacts and four sense pins.<ref name="PCIe5.1 CEM">''PCI Express Card Electromechanical Specification Revision 5.1, Version 1.0'', 30 March 2023 – 10. PCI Express 48VHPWR Auxiliary Power Connector Definition</ref> The contacts are rated for 15 Amps continuous current. The 48VHPWR connector can carry 720 watts. Later it was removed and an incompatible 48V 1x2 connector was introduced where Sense0 and Sense1 are located farthest from each other.
	
{| class="wikitable"
|+ 48VHPWR pinout
! Pin !! Signal
|-
| P1 || +48 V
|-
|P2 || Ground
|-
| S1 || CARD_PWR_STABLE
|-
| S2 || CARD_CBL_PRES#
|-
| S3 || SENSE0
|-
| S4 || SENSE1
|}

=== PCI Express Mini Card <span class="anchor" id="MINI-CARD"></span> ===
<!-- [[PCI Express Mini Card]], [[Mini PCI Express]], [[Mini PCIe]], [[Mini PCI-E]], and [[M-PCIe]] redirect here. -->
[[File:Intel WM3945ABG MOW2 and its connector 20070216.jpg|thumb|A [[WLAN]] PCI Express Mini Card and its connector]]
[[File:MiniPCI and MiniPCI Express cards.jpg|thumb|MiniPCI and MiniPCI Express cards in comparison]]

'''PCI Express Mini Card''' (also known as '''Mini PCI Express''', '''Mini PCIe''', '''Mini PCI-E''', '''mPCIe''', and '''PEM'''), based on PCI Express, is a replacement for the [[Mini PCI]] form factor. It is developed by the [[PCI-SIG]]. The host device supports both PCI Express and [[USB]]&nbsp;2.0 connectivity, and each card may use either standard. Most laptop computers built after 2005 use PCI Express for expansion cards; however, {{as of|2015|lc=yes}}, many vendors are moving toward using the newer [[M.2]] form factor for this purpose.<ref>{{cite web | url=https://arstechnica.com/gadgets/2015/02/understanding-m-2-the-interface-that-will-speed-up-your-next-ssd/ | title=Understanding M.2, the interface that will speed up your next SSD | date=8 February 2015 }}</ref>

Due to different dimensions, PCI Express Mini Cards are not physically compatible with standard full-size PCI Express slots; however, passive adapters exist that let them be used in full-size slots.<ref name="DmwJz" /> 

==== Physical dimensions ====
Dimensions of PCI Express Mini Cards are 30&nbsp;mm × 50.95&nbsp;mm (width&nbsp;× length) for a Full Mini Card. There is a 52-pin [[edge connector]], consisting of two staggered rows on a 0.8&nbsp;mm pitch. Each row has eight contacts, a gap equivalent to four contacts, then a further 18 contacts. [[Printed circuit board|Boards]] have a thickness of 1.0&nbsp;mm, excluding the components. A "Half Mini Card" (sometimes abbreviated as HMC) is also specified, having approximately half the physical length of 26.8&nbsp;mm. There are also half size mini PCIe cards that are 30 x 31.90 mm which is about half the length of a full size mini PCIe card.<ref>{{cite book | url=https://books.google.com/books?id=otfPEAAAQBAJ&dq=pci+express+micro&pg=PT628 | isbn=978-0-13-816625-0 | title=IT Essentials Companion Guide v8 | date=9 July 2023 | publisher=Cisco Press }}</ref><ref>{{cite book | url=https://google.com.pa/books/edition/Mobile_Computing_Deployment_and_Manageme/rP5gBgAAQBAJ?hl=en&gbpv=1&dq=mini+pcie+full+size+half+size&pg=PA491&printsec=frontcover | isbn=978-1-118-82461-0 | title=Mobile Computing Deployment and Management: Real World Skills for CompTIA Mobility+ Certification and Beyond | date=24 February 2015 | publisher=John Wiley & Sons }}</ref> 

==== Electrical interface ====
PCI Express Mini Card edge connectors provide multiple connections and buses:
* PCI Express x1 (with SMBus)
* USB&nbsp;2.0
* Wires to diagnostics LEDs for wireless network (i.e., [[Wi-Fi]]) status on computer's chassis
* [[Subscriber Identity Module|SIM]] card for [[GSM]] and [[WCDMA]] applications (UIM signals on spec.)
* Future extension for another PCIe lane
* 1.5&nbsp;V and 3.3&nbsp;V power

==== Mini-SATA (mSATA) variant <span class="anchor" id="MSATA"></span> ====
[[File:Intel 525 mSATA SSD.jpg|thumb|upright|An Intel mSATA SSD]]
Despite sharing the Mini PCI Express form factor, an [[mSATA]] slot is not necessarily electrically compatible with Mini PCI Express. For this reason, only certain notebooks are compatible with mSATA drives. Most compatible systems are based on Intel's Sandy Bridge processor architecture, using the Huron River platform. Notebooks such as Lenovo's ThinkPad T, W and X series, released in March–April 2011, have support for an mSATA SSD card in their [[Wireless WAN|WWAN]] card slot. The ThinkPad Edge E220s/E420s, and the Lenovo IdeaPad Y460/Y560/Y570/Y580 also support mSATA.<ref name="5xxpo" /> On the contrary, the L-series among others can only support M.2 cards using the PCIe standard in the WWAN slot.

Some notebooks (notably the [[Asus Eee PC]], the [[Apple Inc.|Apple]] [[MacBook Air]], and the Dell mini9 and mini10) use a variant of the PCI Express Mini Card as an [[solid-state drive|SSD]]. This variant uses the reserved and several non-reserved pins to implement SATA and IDE interface passthrough, keeping only USB, ground lines, and sometimes the core PCIe x1 bus intact.<ref name="EeePC" /> This makes the "miniPCIe" flash and solid-state drives sold for netbooks largely incompatible with true PCI Express Mini implementations.

Also, the typical Asus miniPCIe SSD is 71&nbsp;mm long, causing the Dell 51&nbsp;mm model to often be (incorrectly) referred to as half length. A true 51&nbsp;mm Mini PCIe SSD was announced in 2009, with two stacked PCB layers that allow for higher storage capacity. The announced design preserves the PCIe interface, making it compatible with the standard mini PCIe slot. No working product has yet been developed.

Intel has numerous desktop boards with the PCIe x1 Mini-Card slot that typically do not support mSATA SSD. A list of desktop boards that natively support mSATA in the PCIe x1 Mini-Card slot (typically multiplexed with a SATA port) is provided on the Intel Support site.<ref name="xpI66" />

=== PCI Express M.2 ===
{{Main|M.2}}
M.2 replaces the mSATA standard and Mini PCIe.<ref name="oL68r" /> Computer bus interfaces provided through the M.2 connector are PCI Express 3.0 or higher (up to four lanes), Serial ATA 3.0, and USB 3.0 (a single logical port for each of the latter two). It is up to the manufacturer of the M.2 host or device to choose which interfaces to support, depending on the desired level of host support and device type.

=== PCI Express External Cabling <span class="anchor" id="EXTERNAL-CABLING"></span> ===
''PCI Express External Cabling'' (also known as ''External PCI Express'', ''Cabled PCI Express'', or ''ePCIe'') specifications were released by the [[PCI-SIG]] in February 2007.<ref name="pcie_cabling1.0" /><ref name="ZTXPi" />

Standard cables and connectors have been defined for x1, x4, x8, and x16 link widths, with a transfer rate of 250&nbsp;MB/s per lane. The PCI-SIG also expects the norm to evolve to reach 500&nbsp;MB/s, as in PCI Express 2.0. An example of the uses of Cabled PCI Express is a metal enclosure, containing a number of PCIe slots and PCIe-to-ePCIe adapter circuitry. This device would not be possible had it not been for the ePCIe specification.

==== PCI Express OCuLink <span class="anchor" id="OCULINK"></span> ====
''OCuLink'' (standing for "optical-copper link", as ''Cu'' is the [[Symbol (chemistry)|chemical symbol]] for [[copper]]) is an extension for the "cable version of PCI Express". Version 1.0 of OCuLink, released in Oct 2015, supports up to 4 PCIe 3.0 lanes (3.9&nbsp;GB/s) over copper cabling; a [[fiber optic]] version may appear in the future.

The most recent version of OCuLink, OCuLink-2, supports up to 16&nbsp;GB/s (PCIe 4.0 x8)<ref name="OCuLink2" /> while the maximum bandwidth of a [[USB 4]] cable is 10GB/s.

While initially intended for use in PCIe interconnections in servers, OCuLink's popularity lies primarily in its use for laptops for the connection of powerful external GPU boxes, a more prevalent application.<ref name="6MiK5" />

=== Derivative forms ===
Numerous other form factors use, or are able to use, PCIe. These include:
* Low-height card
* [[ExpressCard]]: Successor to the [[PC Card]] form factor (with x1 PCIe and USB 2.0; hot-pluggable)
* PCI Express ExpressModule: A hot-pluggable modular form factor defined for servers and workstations
* [[XQD card]]: A PCI Express-based flash card standard by the [[CompactFlash Association]] with x2 PCIe
* [[CFexpress]] card: A PCI Express-based flash card by the CompactFlash Association in three form factors supporting 1 to 4 PCIe lanes
* SD card: The [[SD card#SD Express|SD Express]] bus, introduced in version 7.0 of the SD specification uses a x1 PCIe link
* [[Switched Mezzanine Card|XMC]]: Similar to the [[Common Mezzanine Card|CMC]]/[[PCI Mezzanine Card|PMC]] form factor (VITA 42.3)
* [[Advanced Telecommunications Computing Architecture|AdvancedTCA]]: A complement to [[CompactPCI]] for larger applications; supports serial based backplane topologies
* [[Advanced Mezzanine Card|AMC]]: A complement to the [[Advanced Telecommunications Computing Architecture|AdvancedTCA]] specification; supports processor and I/O modules on ATCA boards (x1, x2, x4 or x8 PCIe).
* [[FeaturePak]]: A tiny expansion card format (43{{nbsp}}mm × 65&nbsp;mm) for embedded and small-form-factor applications, which implements two x1 PCIe links on a high-density connector along with USB, I2C, and up to 100 points of I/O
* [[Universal IO]]: A variant from [[Supermicro|Super Micro Computer]] Inc designed for use in low-profile rack-mounted chassis.<ref name="tNP5L" /> It has the connector bracket reversed so it cannot fit in a normal PCI Express socket, but it is pin-compatible and may be inserted if the bracket is removed.
* [[M.2]] (formerly known as NGFF)
* [[M-PCIe]] brings PCIe 3.0 to mobile devices (such as tablets and smartphones), over the [[M-PHY]] physical layer.<ref name="osiit" /><ref name="PoRghEr" />
* [[U.2]] (formerly known as SFF-8639)
* [[SlimSAS]]

The PCIe slot connector can also carry protocols other than PCIe. Some [[List of Intel chipsets|9xx series Intel chipsets]] support [[Serial Digital Video Out]], a proprietary technology that uses a slot to transmit video signals from the host CPU's [[Intel GMA|integrated graphics]] instead of PCIe, using a supported add-in.

The PCIe transaction-layer protocol can also be used over some other interconnects, which are not electrically PCIe:
* [[Thunderbolt (interface)|Thunderbolt]]: A royalty-free <!-- as of Thunderbolt 3 --> interconnect standard by Intel that combines [[DisplayPort]] and PCIe protocols in a form factor compatible with [[Mini DisplayPort]]. Thunderbolt 3.0 also combines USB 3.1 and uses the [[USB-C]] form factor as opposed to Mini DisplayPort.
* [[USB4]]

== History and revisions ==
While in early development, PCIe was initially referred to as ''HSI'' (for ''High Speed Interconnect''), and underwent a name change to ''3GIO'' (for ''3rd Generation I/O'') before finally settling on its [[PCI-SIG]] name ''PCI Express''. A technical working group named the ''Arapaho Work Group'' (AWG) drew up the standard. For initial drafts, the AWG consisted only of Intel engineers; subsequently, the AWG expanded to include industry partners.

Since, PCIe has undergone several large and smaller revisions, improving on performance and other features.

=== Comparison table ===
{| class="wikitable" style="text-align:right"
|+ PCI Express link performance<ref name="faq4" /><ref name="faq3" />
|- style="line-height:120%"
! scope="col" rowspan=2 | Version
! scope="col" rowspan=2 | Intro-<br />duced
! scope="col" rowspan=2 colspan=2 | Line code
! scope="col" rowspan=2 | Transfer rate<br />(per lane){{Efn-lr|name="both-directions"|In each direction (each lane is a dual simplex channel).}}{{Efn-lr|name="transfer-rate"|Transfer rate refers to the encoded serial bit rate; 2.5 GT/s means 2.5&nbsp;Gbit/s serial data rate.}}
! scope="col" colspan=5 | Throughput{{Efn-lr|name="both-directions"}}{{Efn-lr|name="throughput"|Throughput indicates the usable bandwidth (i.e. only including the payload, not the 8b/10b, 128b/130b, or 242B/256B encoding overhead). The PCIe 1.0 transfer rate of 2.5&nbsp;GT/s per lane means a 2.5&nbsp;Gbit/s serial bit rate; after applying a 8b/10b encoding, this corresponds to a useful throughput of 2.0&nbsp;Gbit/s &#61; 250&nbsp;MB/s.}}
|-
! scope="col" | ×1
! scope="col" | ×2
! scope="col" | ×4
! scope="col" | ×8
! scope="col" | ×16
|-
! scope="row" | 1.0
| 2003
| rowspan=5 | [[Non-return-to-zero|NRZ]]
| rowspan=2 | [[8b/10b]]
| {{Nowrap|2.5 [[GT/s]]}}
| {{Nowrap|0.250 [[GB/s]]}}
| {{COther|{{Nowrap|0.500 GB/s}}|align=right}}
| {{Nowrap|1.000 GB/s}}
| {{COther|{{Nowrap|2.000 GB/s}}|align=right}}
| {{Nowrap|4.000 GB/s}}
|-
! scope="row" | 2.0
| 2007
| {{Nowrap|5.0 GT/s}}
| {{COther|{{Nowrap|0.500 GB/s}}|align=right}}
| {{Nowrap|1.000 GB/s}}
| {{COther|{{Nowrap|2.000 GB/s}}|align=right}}
| {{Nowrap|4.000 GB/s}}
| {{CNone|{{Nowrap|8.000 GB/s}}|align=right}}
|-
! scope="row" | 3.0
| 2010
| rowspan=3 | [[128b/130b]]
| {{Nowrap|8.0 GT/s}}
| {{Nowrap|0.985 GB/s}}
| {{COther|{{Nowrap|1.969 GB/s}}|align=right}}
| {{Nowrap|3.938 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}7.877 GB/s}}|align=right}}
| {{Nowrap|15.754 GB/s}}
|-
! scope="row" | 4.0
| 2017
| {{Nowrap|16.0 GT/s}}
| {{COther|{{Nowrap|1.969 GB/s}}|align=right}}
| {{Nowrap|3.938 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}7.877 GB/s}}|align=right}}
| {{Nowrap|15.754 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}31.508 GB/s}}|align=right}}
|-
! scope="row" | 5.0
| 2019
| {{Nowrap|32.0 GT/s}}
| {{Nowrap|3.938 GB/s}}
| {{CNone|{{Nowrap|{{0|0}}7.877 GB/s}}|align=right}}
| {{Nowrap|15.754 GB/s}}
| {{CNone|{{Nowrap|31.508 GB/s}}|align=right}}
| {{Nowrap|63.015 GB/s}}
|-
! scope="row" | 6.0 
| 2022
| rowspan=2 | {{Nowrap|[[PAM-4]]}}<br />[[Forward error correction|FEC]]
| rowspan=2 | 1b/1b<br />242B/256B [[Flit (computer networking)|FLIT]]
| {{Nowrap|64.0 GT/s}}<br />{{Nowrap|32.0 G[[Baud|Bd]]}}
| {{CNone|{{Nowrap|7.563 GB/s}}|align=right}}
| {{Nowrap|15.125 GB/s}}
| {{CNone|{{Nowrap|30.250 GB/s}}|align=right}}
| {{Nowrap|60.500 GB/s}}
| {{CNone|{{Nowrap|121.000 GB/s}}|align=right}}
|-
! scope="row" | 7.0 
| 2025<br />(planned)
| {{Nowrap|128.0 GT/s}}<br />{{Nowrap|64.0 GBd}}
| {{Nowrap|15.125 GB/s}}
| {{CNone|{{Nowrap|30.250 GB/s}}|align=right}}
| {{Nowrap|60.500 GB/s}}
| {{CNone|{{Nowrap|121.000 GB/s}}|align=right}}
| {{Nowrap|242.000 GB/s}}
|}

; Notes
{{Notelist-lr}}

=== PCI Express 1.0a <span class="anchor" id="1.0"></span><span class="anchor" id="1.0a"></span> ===
In 2003, PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of 250&nbsp;MB/s and a [[transfer (computing)|transfer rate]] of 2.5 gigatransfers per second (GT/s).

Transfer rate is expressed in transfers per second instead of bits per second because the number of transfers includes the overhead bits, which do not provide additional throughput;<ref name="HroAC" /> PCIe 1.x uses an [[8b/10b encoding]] scheme, resulting in a 20% (=&nbsp;2/10) overhead on the raw channel bandwidth.<ref name="tfQxK" /> So in the PCIe terminology, transfer rate refers to the encoded bit rate: 2.5&nbsp;GT/s is 2.5&nbsp;Gbit/s on the encoded serial link. This corresponds to 2.0&nbsp;Gbit/s of pre-coded data or 250&nbsp;MB/s, which is referred to as throughput in PCIe.

==== PCI Express 1.1 <span class="anchor" id="1.1"></span> ====
In 2005, PCI-SIG<ref name="n9qGs" /> introduced PCIe 1.1. This updated specification includes clarifications and several improvements, but is fully compatible with PCI Express 1.0a. No changes were made to the data rate.

=== PCI Express 2.0 <span class="anchor" id="2.0"></span> ===
[[File:Rosewill-USB3-PCI-Express-Card.jpg|thumb|A PCI Express&nbsp;2.0 x1 expansion card that provides USB&nbsp;3.0 connectivity{{Efn|The card's [[Serial ATA#Standard connector|Serial ATA power connector]] is present because the USB&nbsp;3.0 ports require more power than the PCI Express bus can supply. More often, a [[Molex connector#Disk drive|4-pin Molex power connector]] is used.}}]]

[[PCI-SIG]] announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.<ref name="PCIExpressPressRelease" /> The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5{{nbsp}}GT/s and the per-lane throughput rises from 250&nbsp;MB/s to 500&nbsp;MB/s. Consequently, a 16-lane PCIe connector (x16) can support an aggregate throughput of up to 8&nbsp;GB/s.

PCIe 2.0 motherboard slots are fully [[backward compatible]] with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 work, with the other being v1.1 or v1.0a.

The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.<ref name="UaYlc" />

[[Intel Corporation|Intel]]'s first PCIe 2.0 capable chipset was the [[G35 (chipset)|X38]] and boards began to ship from various vendors ([[Universal abit|Abit]], [[Asus]], [[Gigabyte Technology|Gigabyte]]) as of 21 October 2007.<ref name="wHHTf" /> AMD started supporting PCIe 2.0 with its [[AMD 700 chipset series]] and nVidia started with the [[nForce 700|MCP72]].<ref name="gL2GQ" /> All of Intel's prior chipsets, including the [[Intel P35]] chipset, supported PCIe 1.1 or 1.0a.<ref name="mUQKD" />

Like 1.x, PCIe 2.0 uses an [[8b/10b encoding]] scheme, therefore delivering, per-lane, an effective 4&nbsp;Gbit/s max. transfer rate from its 5&nbsp;GT/s raw data rate.

==== PCI Express 2.1 <span class="anchor" id="2.1"></span> ====
PCI Express 2.1 (with its specification dated 4 March 2009) supports a large proportion of the management, support, and troubleshooting systems planned for full implementation in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. The increase in power from the slot breaks backward compatibility between PCI Express 2.1 cards and some older motherboards with 1.0/1.0a, but most motherboards with PCI Express 1.1 connectors are provided with a BIOS update by their manufacturers through utilities to support backward compatibility of cards with PCIe 2.1.

=== PCI Express 3.0 <span class="anchor" id="3.0"></span> ===
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 [[gigatransfer]]s per second (GT/s), and that it would be backward compatible with existing PCI Express implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until Q2 2010.<ref name="cVjNG" /> New features for the PCI Express 3.0 specification included a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, [[phase-locked loop|PLL]] improvements, clock data recovery, and channel enhancements of currently supported topologies.<ref name="extrmetech" />

Following a six-month technical analysis of the feasibility of scaling the PCI Express interconnect bandwidth, PCI-SIG's analysis found that 8 gigatransfers per second could be manufactured in mainstream silicon process technology, and deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) with the PCI Express protocol stack.

PCI Express&nbsp;3.0 upgraded the [[encoding scheme]] to 128b/130b from the previous [[8b/10b encoding]], reducing the bandwidth overhead from 20% of  PCI Express&nbsp;2.0 to approximately 1.54% (=&nbsp;2/130). PCI Express 3.0's 8&nbsp;GT/s bit rate effectively delivers 985&nbsp;MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0.<ref name="faq3" />

On 18 November 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.<ref name="ajVA3" />

==== PCI Express 3.1 <span class="anchor" id="3.1"></span> ====
In September 2013, PCI Express&nbsp;3.1 specification was announced for release in late 2013 or early 2014, consolidating various improvements to the published PCI Express&nbsp;3.0 specification in three areas: power management, performance and functionality.<ref name="PoRghEr" /><ref name="5lvIH" /> It was released in November 2014.<ref name="9EIkz" />

=== PCI Express 4.0 <span class="anchor" id="4.0"></span> ===
On 29 November 2011, PCI-SIG preliminarily announced PCI Express 4.0,<ref name="W466M" /> providing a 16&nbsp;GT/s bit rate that doubles the bandwidth provided by PCI Express 3.0 to 31.5&nbsp;GB/s in each direction for a 16-lane configuration, while maintaining backward and [[forward compatibility]] in both software support and used mechanical interface.<ref name="QNZsy" /> PCI Express 4.0 specs also bring OCuLink-2, an alternative to [[Thunderbolt (interface)|Thunderbolt]]. OCuLink version 2 has up to 16&nbsp;GT/s (16{{nbsp}}GB/s total for x8 lanes),<ref name="OCuLink2" /> while the maximum bandwidth of a Thunderbolt 3 link is 5{{nbsp}}GB/s.

In June 2016 Cadence, PLDA and Synopsys demonstrated PCIe 4.0 physical-layer, controller, switch and other IP blocks at the PCI SIG’s annual developer’s conference.<ref name="EE_4+5" />
 
[[Mellanox Technologies]] announced the first 100{{nbsp}}Gbit/s network adapter with PCIe 4.0 on 15 June 2016,<ref name="FZ4hQ" /> and the first 200{{nbsp}}Gbit/s network adapter with PCIe 4.0 on 10 November 2016.<ref name="zovf4" />

In August 2016, [[Synopsys]] presented a test setup with FPGA clocking a lane to PCIe 4.0 speeds at the [[Intel Developer Forum]]. Their IP has been licensed to several firms planning to present their chips and products at the end of 2016.<ref name="heise_idf_2016" />

On the IEEE Hot Chips Symposium in August 2016 [[IBM]] announced the first CPU with PCIe 4.0 support, [[POWER9]].<ref name="HC28-IBM-Power9">{{Cite web|url=https://old.hotchips.org/wp-content/uploads/hc_archives/hc28/HC28.23-Tuesday-Epub/HC28.23.90-High-Perform-Epub/HC28.23.921-.POWER9-Thompto-IBM-final.pdf|title=Brian Thompto, POWER9 Processor for the Cognitive Era}}</ref><ref name="IEEE-Power9">[https://ieeexplore.ieee.org/xpl/conhome/7932734/proceeding 2016 IEEE Hot Chips 28 Symposium (HCS), 21–23 Aug. 2016]</ref>

PCI-SIG officially announced the release of the final PCI Express 4.0 specification on 8 June 2017.<ref name="TR_pcie4" /> The spec includes improvements in flexibility, scalability, and lower-power.

On 5 December 2017 IBM announced the first system with PCIe 4.0 slots, Power AC922.<ref name="2HOSh" /><ref name="IBM-ZG17-0147">{{Cite web|url=https://www.ibm.com/docs/en/announcements/archive/ENUSZG17-0147|title=IBM Power System AC922 (8335-GTG) server helps you to harness breakthrough accelerated AI, HPDA, and HPC performance for faster time to insight|date=2017-12-05|access-date=2025-04-25|website=www.ibm.com|archive-url=https://web.archive.org/web/20240627011358/https://www.ibm.com/docs/en/announcements/archive/ENUSZG17-0147|archive-date=2024-06-27|url-status=live}}</ref>

NETINT Technologies introduced the first [[NVM Express|NVMe]] SSD based on PCIe 4.0 on 17 July 2018, ahead of Flash Memory Summit 2018<ref name="ChNhD" />

[[Advanced Micro Devices|AMD]] announced on 9 January 2019 its upcoming [[Zen 2]]-based processors and X570 chipset would support PCIe 4.0.<ref name="Akskd" /> AMD had hoped to enable partial support for older chipsets, but instability caused by motherboard traces not conforming to PCIe 4.0 specifications made that impossible.<ref name="KDBMK" /><ref name="CAY71" />

Intel released their first mobile CPUs with PCI Express 4.0 support in mid-2020, as a part of the [[Tiger Lake (microprocessor)|Tiger Lake]] microarchitecture.<ref name="C02lC" />

=== PCI Express 5.0 <span class="anchor" id="5.0"></span> ===
[[File:Detailaufnahme des ASRock TRX50 WS 20240406 HOF1835-HDR RAW-Export 000185.png|thumb|Three PCIe 5.0 x16 (first and third slots at x16, fourth slot at x8 throughput) and two PCIe 4.0 x16 slots (second slot at x4, fifth slot at x8 throughput) on a 2023 workstation mainboard.]]
In June 2017, PCI-SIG announced the PCI Express 5.0 preliminary specification.<ref name="TR_pcie4" /> Bandwidth was expected to increase to 32{{nbsp}}GT/s, yielding 63{{nbsp}}GB/s<!-- 32 GT/s × 16 × 128/130 / 8 = 63,015,384,615 B/s --> in each direction in a 16-lane configuration. The draft spec was expected to be standardized in 2019.{{citation needed|date=July 2019}} Initially, {{Nowrap|25.0 GT/s}} was also considered for technical feasibility.

On 7 June 2017 at PCI-SIG DevCon, Synopsys recorded the first demonstration of PCI Express 5.0 at 32&nbsp;GT/s.<ref name="Syn50" />

On 31 May 2018, PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day.<ref name="n6z9y" /><ref name="9OVm8" />

On 10 December 2018, the PCI SIG released version 0.9 of the PCIe 5.0 specification to its members,<ref name="PCIe5r09" />
and on 17 January 2019, PCI SIG announced the version 0.9 had been ratified, with version 1.0 targeted for release in the first quarter of 2019.<ref name="ETVqe" />

On 29 May 2019, PCI-SIG officially announced the release of the final PCI Express 5.0 specification.<ref name="MW69U" />

On 20 November 2019, [[Jiangsu Huacun]] presented the first PCIe 5.0 Controller HC9001 in a 12&nbsp;nm manufacturing process<ref name="yk5Nd" /> and production started in 2020.

On 17 August 2020, IBM announced the [[Power10]] processor with PCIe 5.0 and up to 32 lanes per single-chip module (SCM) and up to 64 lanes per double-chip module (DCM).<ref>{{Cite web|url=https://hc32.hotchips.org/assets/program/conference/day1/HotChips2020_Server_Processors_IBM_Starke_POWER10_v33.pdf|title=IBM's POWER10 Processor, Hot Chips 32, August 16–18, 2020}}</ref>

On 9 September 2021, IBM announced the Power E1080 Enterprise server with planned availability date 17 September.<ref name="IBM-ENUSZG21-0059">[https://www.ibm.com/common/ssi/rep_ca/9/877/ENUSZG21-0059/index.html Power E1080 Enterprise server delivers a uniquely architected platform to help securely and efficiently scale core operational and AI applications in a hybrid cloud, IBM Europe Hardware Announcement ZG21-0059]</ref> It can have up to 16 Power10 SCMs with maximum of 32 slots per system which can act as PCIe 5.0 x8 or PCIe 4.0 x16.<ref name="IBM-REDP-5649-00">[http://www.redbooks.ibm.com/redpapers/pdfs/redp5649.pdf IBM Power E1080 Technical Overview and Introduction]</ref> Alternatively they can be used as PCIe 5.0 x16 slots for optional optical CXP converter adapters connecting to external PCIe expansion drawers.

On 27 October 2021, Intel announced the 12th Gen Intel Core CPU family, the world's first consumer x86-64 processors with PCIe 5.0 (up to 16 lanes) connectivity.<ref>{{cite web|url=https://www.intel.com/content/www/us/en/newsroom/news/12th-gen-core-processors.html |title=Intel Unveils 12th Gen Intel Core, Launches World's Best Gaming |date=31 December 2021 |publisher=Intel.com |accessdate=2022-02-16}}</ref>

On 22 March 2022, Nvidia announced Nvidia Hopper GH100 GPU, the world's first PCIe 5.0 GPU.<ref>{{cite web|url=https://nvidianews.nvidia.com/news/nvidia-announces-hopper-architecture-the-next-generation-of-accelerated-computing|title = NVIDIA Announces Hopper Architecture, the Next Generation of Accelerated Computing}}</ref>

On 23 May 2022, AMD announced its Zen 4 architecture with support for up to 24 lanes of PCIe 5.0 connectivity on consumer platforms and 128 lanes on server platforms.<ref>{{cite web|url=https://www.amd.com/en/press-releases/2022-05-23-amd-showcases-growth-gaming-commercial-and-mainstream-mobile-and-industry|title=AMD Showcases Industry-Leading Gaming, Commercial, and Mainstream PC Technologies at COMPUTEX 2022|publisher=AMD.com|accessdate=2022-05-23}}</ref><ref>{{cite web|url=
https://www.amd.com/en/campaigns/epyc-9004-architecture|title=4th Gen AMD EPYC™ Processor Architecture|publisher=AMD.com|accessdate=2022-11-12}}</ref>

=== PCI Express 6.0 <span class="anchor" id="6.0"></span> ===
On 18 June 2019, PCI-SIG announced the development of PCI Express 6.0 specification. Bandwidth is expected to increase to 64{{nbsp}}GT/s, yielding 128{{nbsp}}GB/s in each direction in a 16-lane configuration, with a target release date of 2021.<ref name="businesswire.com" /> The new standard uses 4-level [[pulse-amplitude modulation]] (PAM-4) with a low-latency [[forward error correction]] (FEC) in place of [[non-return-to-zero]] (NRZ) modulation.<ref name="O5gOe" /> Unlike previous PCI Express versions, forward error correction is used to increase data integrity and PAM-4 is used as line code so that two bits are transferred per transfer. With 64{{nbsp}}GT/s data transfer rate (raw bit rate), up to 121{{nbsp}}GB/s in each direction is possible in x16 configuration.<ref name="businesswire.com" />

On 24 February 2020, the PCI Express 6.0 revision 0.5 specification (a "first draft" with all architectural aspects and requirements defined) was released.<ref name="puGmx" />

On 5 November 2020, the PCI Express 6.0 revision 0.7 specification (a "complete draft" with electrical specifications validated via test chips) was released.<ref name="ltCSi" />

On 6 October 2021, the PCI Express 6.0 revision 0.9 specification (a "final draft") was released.<ref name="60r9">{{cite web |last=Yanes |first=Al |title=PCIe® 6.0 Specification, Version 0.9: One Step Closer to Final Release {{!}} PCI-SIG |url=https://pcisig.com/blog/pcie®-60-specification-version-09-one-step-closer-final-release |website=pcisig.com |access-date=6 October 2021}}</ref>

On 11 January 2022, PCI-SIG officially announced the release of the final PCI Express 6.0 specification.<ref>{{cite web|url=https://www.businesswire.com/news/home/20220111005011/en/PCI-SIG%C2%AE-Releases-PCIe%C2%AE-6.0-Specification-Delivering-Record-Performance-to-Power-Big-Data-Applications |title=PCI-SIG® Releases PCIe® 6.0 Specification Delivering Record Performance to Power Big Data Applications |publisher=Business Wire |date=2022-01-11 |accessdate=2022-02-16}}</ref>

[[PAM-4]] coding results in a vastly higher [[bit error rate]] (BER) of 10<sup>−6</sup> (vs. 10<sup>−12</sup> previously), so in place of 128b/130b encoding, a 3-way interlaced [[forward error correction]] (FEC) is used in addition to [[cyclic redundancy check]] (CRC). A fixed 256 byte [[Flit (computer networking)|Flow Control Unit]] (FLIT) block carries 242 bytes of data, which includes variable-sized transaction level packets (TLP) and data link layer payload (DLLP); remaining 14 bytes are reserved for 8-byte CRC and 6-byte FEC.<ref name=pcie6_evolution_blog>{{cite web|url=https://pcisig.com/blog/evolution-pci-express-specification-its-sixth-generation-third-decade-and-still-going-strong |title=The Evolution of the PCI Express Specification: On its Sixth Generation, Third Decade and Still Going Strong |publisher=Pci-Sig |date=2022-01-11 |accessdate=2022-02-16}}</ref><ref name="PCIe6_fut">{{cite web|url=https://www.youtube.com/watch?v=jhehXwnu0Ss | archive-url=https://ghostarchive.org/varchive/youtube/20211030/jhehXwnu0Ss| archive-date=2021-10-30|title=PCIe 6.0 Specification: The Interconnect for I/O Needs of the Future |page=8 |author=Debendra Das Sharma | date=8 June 2020|publisher=PCI-SIG}}{{cbignore}}</ref> 3-way [[Gray code]] is used in PAM-4/FLIT mode to reduce error rate; the interface does not switch to NRZ and 128/130b encoding even when retraining to lower data rates.<ref name=cadence_pice6>{{cite web|url=https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/design-ip/pushing-the-envelope-with-pcie-6-wp.pdf |title=Pushing the Envelope with PCIe 6.0: Bringing PAM4 to PCIe |date= |accessdate=2022-02-16}}</ref><ref name=pcie6_webinar>{{cite web|url=https://pcisig.com/sites/default/files/files/PCIe%206.0%20Webinar_Final_.pdf |title=PowerPoint Presentation |date= |accessdate=2022-02-16}}</ref>

=== PCI Express 7.0 <span class="anchor" id="7.0"></span> ===
On 21 June 2022, PCI-SIG announced the development of PCI Express 7.0 specification.<ref>{{cite web|url=https://www.businesswire.com/news/home/20220621005137/en |title=PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s |publisher=Business Wire |date=2022-06-21 |accessdate=2022-06-25}}</ref> It will deliver 128&nbsp;GT/s raw bit rate and up to 242&nbsp;GB/s per direction in x16 configuration, using the same [[Pulse-amplitude modulation|PAM4]] signaling as version 6.0. Doubling of the data rate will be achieved by fine-tuning channel parameters to decrease signal losses and improve power efficiency, but signal integrity is expected to be a challenge. The specification is expected to be finalized in 2025.

On 3 April 2024, the PCI Express 7.0 revision 0.5 specification (a "first draft") was released.<ref name="PCIe70v05"/>

On 17 January 2025, PCI-SIG announced the release of PCIe 7.0 specification version 0.7 (a "complete draft").<ref name="PCIe70v07"/>

On 19 March 2025, PCI-SIG announced the release of PCIe 7.0 specification version 0.9 (a "final draft"); planned final release is still in 2025.<ref name="PCIe70v09"/>

The following main points were formulated as objectives of the new standard:
* Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
* Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
* Focusing on the channel parameters and reach
* Improving power efficiency
* Continuing to deliver the low-latency and high-reliability targets
* Maintaining backwards compatibility with all previous generations of PCIe technology

== Extensions and future directions <span class="anchor" id="M-PCIE"></span><span class="anchor" id="Thunderbolt"></span> ==
Some vendors offer PCIe over fiber products,<ref name="PCIeFiber" /><ref name="adnacoPCIe" /><ref name="g6np3" /> with active optical cables (AOC) for PCIe switching at increased distance in PCIe expansion drawers,<ref name="IBM-REDP-5137-00">{{Cite web|url=http://www.redbooks.ibm.com/redpapers/pdfs/redp5137.pdf|title=IBM Power Systems E870 and E880 Technical Overview and Introduction}}</ref><ref name="IBM-REDP-5649-00"/> or in specific cases where transparent PCIe bridging is preferable to using a more mainstream standard (such as [[InfiniBand]] or [[Ethernet]]) that may require additional software to support it.

''[[Thunderbolt (interface)|Thunderbolt]]'' was co-developed by [[Intel]] and [[Apple Inc.|Apple]] as a general-purpose high speed interface combining a logical PCIe link with [[DisplayPort]] and was originally intended as an all-fiber interface, but due to early difficulties in creating a consumer-friendly fiber interconnect, nearly all implementations are copper systems. A notable exception, the [[Sony Vaio Z series|Sony VAIO Z]] VPC-Z2, uses a nonstandard USB port with an optical component to connect to an outboard PCIe display adapter. Apple has been the primary driver of Thunderbolt adoption through 2011, though several other vendors<ref name="kZCuH" /> have announced new products and systems featuring Thunderbolt. Thunderbolt 3 forms the basis of the [[USB4]] standard.

''Mobile PCIe'' specification (abbreviated to ''M-PCIe'') allows PCI Express architecture to operate over the [[MIPI Alliance]]'s [[M-PHY]] physical layer technology. Building on top of already existing widespread adoption of M-PHY and its low-power design, Mobile PCIe lets mobile devices use PCI Express.<ref name="RKmF2" />

=== Draft process ===
There are 5 primary releases/checkpoints in a PCI-SIG specification:<ref name="yT5P8" />
* Draft 0.3 (Concept): this release may have few details, but outlines the general approach and goals.
* Draft 0.5 (First draft): this release has a complete set of architectural requirements and must fully address the goals set out in the 0.3 draft.
* Draft 0.7 (Complete draft): this release must have a complete set of functional requirements and methods defined, and no new functionality may be added to the specification after this release. Before the release of this draft, electrical specifications must have been validated via test silicon.
* Draft 0.9 (Final draft): this release allows PCI-SIG member companies to perform an internal review for intellectual property, and no functional changes are permitted after this draft.
* 1.0 (Final release): this is the final and definitive specification, and any changes or enhancements are through Errata documentation and Engineering Change Notices (ECNs) respectively.

Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources.

== Hardware protocol summary ==
The PCIe link is built around dedicated unidirectional couples of serial (1-bit), point-to-point connections known as ''lanes''. This is in sharp contrast to the earlier PCI connection, which is a bus-based system where all the devices share the same bidirectional, 32-bit or 64-bit parallel bus.

PCI Express is a [[layered protocol]], consisting of a ''[[#Transaction layer|transaction layer]]'', a ''[[#Data link layer|data link layer]]'', and a ''[[#Physical layer|physical layer]]''. The Data Link Layer is subdivided to include a [[media access control]] (MAC) sublayer. The Physical Layer is subdivided into logical and electrical sublayers. The Physical logical-sublayer contains a physical coding sublayer (PCS). The terms are borrowed from the [[IEEE 802]] networking protocol model.

=== Physical layer <span class="anchor" id="PHYSICAL-LAYER"></span> ===
{| class="wikitable floatright" style="margin-left: 1.5em; margin-right: 0; margin-top: 0;"
|+ Connector pins and lengths
|-
! rowspan="2" | Lanes
! colspan="2" | Pins
! colspan="2" | Length
|-
! Total
! Variable
! Total
! Variable
|-
| {{0}}x1 || 2×18 = {{0}}36<ref name="9tQ3g" /> || 2×{{0}}7 = {{0}}14 || 25&nbsp;mm || {{0}}7.65&nbsp;mm
|-
| {{0}}x4 || 2×32 = {{0}}64 || 2×21 = {{0}}42 || 39&nbsp;mm || 21.65&nbsp;mm
|-
| {{0}}x8 || 2×49 = {{0}}98 || 2×38 = {{0}}76 || 56&nbsp;mm || 38.65&nbsp;mm
|-
| {{0}}x16 || 2×82 = 164 || 2×71 = 142 || 89&nbsp;mm || 71.65&nbsp;mm
|}

[[File:PCIe J1900 SoC ITX Mainboard IMG 1820.JPG|thumb|An open-end PCI Express x1 connector lets longer cards that use more lanes be plugged while operating at x1 speeds.]]

The PCIe Physical Layer (''PHY'', ''PCIEPHY'', ''PCI Express PHY'', or ''PCIe PHY'') specification is divided into two sub-layers, corresponding to electrical and logical specifications. The logical sublayer is sometimes further divided into a MAC sublayer and a PCS, although this division is not formally part of the PCIe specification. A specification published by Intel, the PHY Interface for PCI Express (PIPE),<ref name="pipe_spec" /> defines the MAC/PCS functional partitioning and the interface between these two sub-layers. The PIPE specification also identifies the ''physical media attachment'' (PMA) layer, which includes the [[SerDes|serializer/deserializer (SerDes)]] and other analog circuitry; however, since SerDes implementations vary greatly among [[Application-specific integrated circuit|ASIC]] vendors, PIPE does not specify an interface between the PCS and PMA.

At the electrical level, each lane consists of two unidirectional [[Differential signaling|differential pair]]s operating at 2.5, 5, 8, 16 or 32&nbsp;[[Gigabit|Gbit]]/s, depending on the negotiated capabilities. Transmit and receive are separate differential pairs, for a total of four data wires per lane.

A connection between any two PCIe devices is known as a ''link'', and is built up from a collection of one or more ''lanes''. All devices must minimally support single-lane (x1) link. Devices may optionally support wider links composed of up to 32 lanes.<ref name="PCIe-System-Architecture">{{Cite web|url=https://www.mindshare.com/files/ebooks/PCI%20Express%20System%20Architecture.pdf|title=PCI Express System Architecture}}</ref><ref name="Intel-PCIe">{{Cite web|url=https://www.intel.com/content/www/us/en/support/ru-banner.html|title=Communications|website=Intel}}</ref> This allows for very good compatibility in two ways:
* A PCIe card physically fits (and works correctly) in any slot that is at least as large as it is (e.g., a x1 sized card works in any sized slot);
* A slot of a large physical size (e.g., x16) can be wired electrically with fewer lanes (e.g., x1, x4, x8, or x12) as long as it provides the ground connections required by the larger physical slot size.
In both cases, PCIe negotiates the highest mutually supported number of lanes. Many graphics cards, motherboards and [[BIOS]] versions are verified to support x1, x4, x8 and x16 connectivity on the same connection.

The width of a PCIe connector is 8.8&nbsp;mm, while the height is 11.25&nbsp;mm, and the length is variable. The fixed section of the connector is 11.65&nbsp;mm in length and contains two rows of 11 pins each (22 pins total), while the length of the other section is variable depending on the number of lanes. The pins are spaced at 1&nbsp;mm intervals, and the thickness of the card going into the connector is 1.6&nbsp;mm.<ref name="pcie_schematics1" /><ref name="pcie_schematics2" />

==== Data transmission ====
PCIe sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency is still comparable to conventional PCI, which has dedicated interrupt lines. When the problem of IRQ sharing of pin based interrupts is taken into account and the fact that message signaled interrupts (MSI) can bypass an I/O APIC and be delivered to the CPU directly, MSI performance ends up being substantially better.<ref name="vV4Hv" />

Data transmitted on multiple-lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCIe specification refers to this interleaving as ''data striping''. While requiring significant hardware complexity to synchronize (or [[clock skew|deskew]]) the incoming striped data, striping can significantly reduce the latency of the ''n''th byte on a link. While the lanes are not tightly synchronized, there is a limit to the ''lane to lane skew'' of 20/8/6&nbsp;ns for 2.5/5/8&nbsp;GT/s so the hardware buffers can re-align the striped data.<ref name="iPAaS" /> Due to padding requirements, striping may not necessarily reduce the latency of small data packets on a link.

As with other high data rate serial transmission protocols, the clock is [[self-clocking signal|embedded]] in the signal. At the physical level, PCI Express 2.0 utilizes the [[8b/10b encoding]] scheme<ref name="faq3" /> (line code) to ensure that strings of consecutive identical digits (zeros or ones) are limited in length. This coding was used to prevent the receiver from losing track of where the bit edges are. In this coding scheme every eight (uncoded) payload bits of data are replaced with 10 (encoded) bits of transmit data, causing a 20% overhead in the electrical bandwidth. To improve the available bandwidth, PCI Express version 3.0 instead uses [[64b/66b encoding|128b/130b]] encoding (1.54% overhead). [[Line encoding]] limits the run length of identical-digit strings in data streams and ensures the receiver stays synchronised to the transmitter via [[clock recovery]].

A desirable balance (and therefore [[spectral density]]) of 0 and 1 bits in the data stream is achieved by [[XOR]]ing a known [[Linear-feedback shift register|binary polynomial]] as a "[[scrambler]]" to the data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by applying the XOR a second time. Both the scrambling and descrambling steps are carried out in hardware.

Dual simplex in PCIe means there are two simplex channels on every PCIe lane. Simplex means communication is only possible in one direction. By having two simplex channels, two-way communication is made possible. One differential pair is used for each channel.<ref>{{cite web |title=PCIe Data Transmission Overview  |website=[[Microchip Technology]] |url=https://ww1.microchip.com/downloads/aemDocuments/documents/TCG/ProductDocuments/Brochures/00003818.pdf }}</ref><ref name="auto"/><ref>{{cite book | url=https://books.google.com/books?id=k_HJCgAAQBAJ&dq=pcie+differential+pair&pg=PT128 | isbn=978-0-7686-9003-3 | title=CompTIA A+ Exam Cram (Exams 220-602, 220-603, 220-604) | date=19 July 2007 | publisher=Pearson Education }}</ref>

=== Data link layer ===
The data link layer performs three vital services for the PCIe link:
# sequence the transaction layer packets (TLPs) that are generated by the transaction layer,
# ensure reliable delivery of TLPs between two endpoints via an acknowledgement protocol ([[Acknowledge character|ACK]] and [[Negative-acknowledge character|NAK]] signaling) that explicitly requires replay of unacknowledged/bad TLPs,
# initialize and manage flow control credits

On the transmit side, the data link layer generates an incrementing sequence number for each outgoing TLP. It serves as a unique identification tag for each transmitted TLP, and is inserted into the header of the outgoing TLP. A 32-bit [[cyclic redundancy check]] code (known in this context as Link CRC or LCRC) is also appended to the end of each outgoing TLP.

On the receive side, the received TLP's LCRC and sequence number are both validated in the link layer. If either the LCRC check fails (indicating a data error), or the sequence-number is out of range (non-consecutive from the last valid received TLP), then the bad TLP, as well as any TLPs received after the bad TLP, are considered invalid and discarded. The receiver sends a negative acknowledgement message (NAK) with the sequence-number of the invalid TLP, requesting re-transmission of all TLPs forward of that sequence-number. If the received TLP passes the LCRC check and has the correct sequence number, it is treated as valid. The link receiver increments the sequence-number (which tracks the last received good TLP), and forwards the valid TLP to the receiver's transaction layer. An ACK message is sent to remote transmitter, indicating the TLP was successfully received (and by extension, all TLPs with past sequence-numbers.)

If the transmitter receives a NAK message, or no acknowledgement (NAK or ACK) is received until a timeout period expires, the transmitter must retransmit all TLPs that lack a positive acknowledgement (ACK). Barring a persistent malfunction of the device or transmission medium, the link-layer presents a reliable connection to the transaction layer, since the transmission protocol ensures delivery of TLPs over an unreliable medium.

In addition to sending and receiving TLPs generated by the transaction layer, the data-link layer also generates and consumes data link layer packets (DLLPs). ACK and NAK signals are communicated via DLLPs, as are some power management messages and flow control credit information (on behalf of the transaction layer).

In practice, the number of in-flight, unacknowledged TLPs on the link is limited by two factors: the size of the transmitter's replay buffer (which must store a copy of all transmitted TLPs until the remote receiver ACKs them), and the flow control credits issued by the receiver to a transmitter. PCI Express requires all receivers to issue a minimum number of credits, to guarantee a link allows sending PCIConfig TLPs and message TLPs.

=== Transaction layer ===
PCI Express implements split transactions (transactions with request and response separated by time), allowing the link to carry other traffic while the target device gathers data for the response.

PCI Express uses credit-based flow control. In this scheme, a device advertises an initial amount of credit for each received buffer in its transaction layer. The device at the
opposite end of the link, when sending transactions to this device, counts the number of credits each TLP consumes from its account. The sending device may only transmit a TLP when doing so does not make its consumed credit count exceed its credit limit. When the receiving device finishes processing the TLP from its buffer, it signals a return of credits to the sending device, which increases the credit limit by the restored amount. The credit counters are modular counters, and the comparison of consumed credits to credit limit requires [[modular arithmetic]]. The advantage of this scheme (compared to other methods such as wait states or handshake-based transfer protocols) is that the latency of credit return does not affect performance, provided that the credit limit is not encountered. This assumption is generally met if each device is designed with adequate buffer sizes.

PCIe 1.x is often quoted to support a data rate of 250&nbsp;MB/s in each direction, per lane. This figure is a calculation from the physical signaling rate (2.5&nbsp;[[gigabaud]]) divided by the encoding overhead (10 bits per byte). This means a sixteen lane (x16) PCIe card would then be theoretically capable of 16x250&nbsp;MB/s = 4&nbsp;GB/s in each direction. While this is correct in terms of data bytes, more meaningful calculations are based on the usable data payload rate, which depends on the profile of the traffic, which is a function of the high-level (software) application and intermediate protocol levels.

Like other high data rate serial interconnect systems, PCIe has a protocol and processing overhead due to the additional transfer robustness (CRC and acknowledgements). Long continuous unidirectional transfers (such as those typical in high-performance storage controllers) can approach >95% of PCIe's raw (lane) data rate. These transfers also benefit the most from increased number of lanes (x2, x4, etc.) But in more typical applications (such as a [[Universal Serial Bus|USB]] or [[Ethernet]] controller), the traffic profile is characterized as short data packets with frequent enforced acknowledgements.<ref name="traffic_profile" /> This type of traffic reduces the efficiency of the link, due to overhead from packet parsing and forced interrupts (either in the device's host interface or the PC's CPU). Being a protocol for devices connected to the same [[printed circuit board]], it does not require the same tolerance for transmission errors as a protocol for communication over longer distances, and thus, this loss of efficiency is not particular to PCIe.

=== Efficiency of the link ===
As for any network-like communication links, some of the raw bandwidth is consumed by protocol overhead:<ref name="Xilinx">{{cite web|title=Understanding Performance of PCI Express Systems|url=https://www.xilinx.com/support/documentation/white_papers/wp350.pdf|last=Lawley|first=Jason|publisher=Xilinx|version=1.2|date=2014-10-28}}</ref>

A PCIe 1.x lane for example offers a data rate on top of the physical layer of 250&nbsp;MB/s (simplex). This is not the payload bandwidth but the physical layer bandwidth – a PCIe lane has to carry additional information for full functionality.{{r|Xilinx}}

{| class="wikitable"
|+Gen 2 Transaction Layer Packet{{r|Xilinx|p=3}}
!scope="row" scope="col" style="width: 80px;" |Layer
!scope="col" style="width: 20px;" |PHY
!scope="col" style="width: 120px;" |Data Link Layer
!scope="col" style="width: 400px;" colspan="3" |Transaction
!scope="col" style="width: 120px;" |Data Link Layer
!scope="col" style="width: 20px;" |PHY
|-
!scope="row" |Data
|Start
|Sequence
|scope="col" style="width: 75px;" |Header
|scope="col" style="text-align:center; width: 250px;" |Payload
|scope="col" style="width: 75px;" |ECRC
|LCRC
|End
|-
!scope="row" |Size (Bytes)
|1
|2
|12 or 16
|scope="col" style="text-align:center;" |0 to 4096
|4 (optional)
|4
|1
|}
The Gen2 overhead is then 20, 24, or 28 bytes per transaction.{{Clarify |reason=Don't we also have a 8/10b encoding overhead that's not factored in to any of this?|date=September 2021}}{{Citation needed|reason=I fixed the bad math here, but it needs a source, not me and a calculator|date=September 2021}}

{| class="wikitable"
|+Gen 3 Transaction Layer Packet{{r|Xilinx|p=3}}
!scope="row" scope="col" style="width: 80px;" |Layer
!scope="col" style="width: 40px;" |PHY
!scope="col" style="width: 120px;" |Data Link Layer
!scope="col" colspan="3" style="width: 400px;" |Transaction Layer
!scope="col" style="width: 120px;" |Data Link Layer
|-
!scope="row" |Data
|Start
|Sequence
|scope="col" style="width: 75px;" |Header
|scope="col" style="width: 250px;text-align:center;" |Payload
|scope="col" style="width: 75px;" |ECRC
|LCRC
|-
!scope="row" |Size (Bytes)
|4
|2
|12 or 16
|scope="col" style="text-align:center; |0 to 4096
|4 (optional)
|4
|}
The Gen3 overhead is then 22, 26 or 30 bytes per transaction.<!-- Seriously how did somebody get odd numbers out of this? -->{{Clarify |reason=Don't we also have a 128/130b encoding overhead that's not factored in to any of this?|date=September 2021}}{{Citation needed|reason=I fixed the bad math here, but it needs a source, not me and a calculator|date=September 2021}}

The <math>\text{Packet Efficiency} = \frac{\text{Payload}}{\text{Payload} + \text{Overhead}}</math> for a 128 byte payload is 86%, and 98% for a 1024 byte payload. For small accesses like register settings (4 bytes), the efficiency drops as low as 16%.{{Citation needed|reason=Formula is in text, but it didn't state this anywhere or anything about register settings being 4 bytes or the like... and most of the PCIe config registers aren't on the devices and don't need a bus access, they're just sitting around in a DMA region mapped to the CPU's control registers|date=September 2021}}

The maximum payload size (MPS) is set on all devices based on smallest maximum on any device in the chain. If one device has an MPS of 128 bytes, ''all'' devices of the tree must set their MPS to 128 bytes. In this case the bus will have a peak efficiency of 86% for writes.{{r|Xilinx|p=3}}

== Applications ==
[[File:ASUS GTX-650 Ti TOP Cu-II PCI Express 3.0 x16 graphics card.jpg|thumb|[[Asus]] Nvidia GeForce GTX 650 Ti, a PCI Express 3.0 x16 graphics card]]
[[File:NVIDIA-GTX-1070-FoundersEdition-FL.jpg|thumb|The [[Nvidia]] GeForce GTX 1070, a PCI Express 3.0 x16 Graphics card]]
[[File:An Intel 82574L Gigabit Ethernet NIC, PCI Express x1 card.jpg|thumb|[[Intel]] 82574L Gigabit Ethernet [[Network interface controller|NIC]], a PCI Express x1 card]]
[[File:SATA 6 Gbit-s controller, in form of a PCI Express card.jpg|thumb|A [[Marvell Technology|Marvell]]-based [[SATA&nbsp;3.0]] controller, as a PCI Express x1 card]]

PCI Express operates in consumer, server, and industrial applications, as a motherboard-level interconnect (to link motherboard-mounted peripherals), a passive backplane interconnect and as an [[expansion card]] interface for add-in boards.

In virtually all modern ({{as of|2012|lc=on}}) PCs, from consumer laptops and desktops to enterprise data servers, the PCIe bus serves as the primary motherboard-level interconnect, connecting the host system-processor with both integrated peripherals (surface-mounted ICs) and add-on peripherals (expansion cards). In most of these systems, the PCIe bus co-exists with one or more legacy PCI buses, for backward compatibility with the large body of legacy PCI peripherals.

{{As of | 2013}}, PCI Express has replaced [[Accelerated Graphics Port|AGP]] as the default interface for graphics cards on new systems. Almost all models of [[graphics card]]s released since 2010 by [[AMD Graphics|AMD]] (ATI) and [[Nvidia]] use PCI Express. Nvidia used the high-bandwidth data transfer of PCIe for its [[Scalable Link Interface]] (SLI) technology, which allowed multiple graphics cards of the same chipset and model number to run in tandem, allowing increased performance.{{Citation needed |reason=Needs cables running across the top connecting the cards, unsure if this is something proprietary or PCIe 1x based.|date=September 2021}} This interface has, since, been discontinued. AMD has also developed a multi-GPU system based on PCIe called [[ATI CrossFire|CrossFire]].{{Citation needed |reason=Needs cables running across the top connecting the cards, unsure if this is something proprietary or PCIe 1x based.|date=September 2021}} AMD, Nvidia, and Intel have released motherboard chipsets that support as many as four PCIe x16 slots, allowing tri-GPU and quad-GPU card configurations.

=== External GPUs ===
Theoretically, external PCIe could give a notebook the graphics power of a desktop, by connecting a notebook with any PCIe desktop video card (enclosed in its own external housing, with a power supply and cooling); this is possible with an ExpressCard or [[Thunderbolt (interface)|Thunderbolt]] interface. An ExpressCard interface provides [[bit rate]]s of 5&nbsp;Gbit/s (0.5&nbsp;GB/s throughput), whereas a Thunderbolt interface provides bit rates of up to 40&nbsp;Gbit/s (5&nbsp;GB/s throughput).

In 2006, [[Nvidia]] developed the [[Nvidia Quadro Plex|Quadro Plex]] external PCIe family of [[Graphics processing unit|GPUs]] that can be used for advanced graphic applications for the professional market.<ref name="gxHZT" /> These video cards require a PCI Express x8 or x16 slot for the host-side card, which connects to the Plex via a [[VHDCI]] carrying eight PCIe lanes.<ref name="zJYg8" />

In 2008, AMD announced the [[ATI XGP]] technology, based on a proprietary cabling system that is compatible with PCIe x8 signal transmissions.<ref name="HgxXj" /> This connector is available on the Fujitsu Amilo and the Acer Ferrari One notebooks. Fujitsu launched their AMILO GraphicBooster enclosure for XGP soon thereafter.<ref name="WHU07" /> Around 2010 Acer launched the Dynavivid graphics dock for XGP.<ref name="mvR09" />

In 2010, external card hubs were introduced that can connect to a laptop or desktop through a PCI ExpressCard slot. These hubs can accept full-sized graphics cards. Examples include MSI GUS,<ref name="ZAJ0y" /> Village Instrument's ViDock,<ref name="J5UtH" /> the Asus [[XG Station]], Bplus PE4H V3.2 adapter,<ref name="jWWJt" /> as well as more improvised DIY devices.<ref name="ERk1e" /> However such solutions are limited by the size (often only x1) and version of the available PCIe slot on a laptop.

The Intel Thunderbolt interface has provided a new option to connect with a PCIe card externally. Magma has released the ExpressBox 3T, which can hold up to three PCIe cards (two at x8 and one at x4).<ref name="CvJwZ" /> MSI also released the Thunderbolt GUS II, a PCIe chassis dedicated for video cards.<ref name="OLzu7" /> Other products such as the Sonnet's Echo Express<ref name="5LOrR" /> and mLogic's mLink are Thunderbolt PCIe chassis in a smaller form factor.<ref name="apXPa" />

In 2017, more fully featured external card hubs were introduced, such as the Razer Core, which has a full-length PCIe x16 interface.<ref name="PXbHS" />

=== Storage devices ===
[[File:PCIe card full height.jpg|thumb|An [[OCZ]] RevoDrive [[Solid-state drive|SSD]], a full-height x4 PCI Express card]]
{{See also|SATA Express|NVMe}}

The PCI Express protocol can be used as data interface to [[flash memory]] devices, such as [[memory card]]s and [[solid-state drive]]s (SSDs).

The [[XQD card]] is a memory card format utilizing PCI Express, developed by the CompactFlash Association, with transfer rates of up to 1&nbsp;GB/s.<ref name="49Gx4" />

Many high-performance, enterprise-class SSDs are designed as PCI Express [[RAID controller]] cards.{{Citation needed|date=September 2021}} Before NVMe was standardized, many of these cards utilized proprietary interfaces and custom drivers to communicate with the operating system; they had much higher transfer rates (over 1&nbsp;GB/s) and IOPS (over one million I/O operations per second) when compared to Serial ATA or [[Serial attached SCSI|SAS]] drives.{{Quantify |reason=Listing numbers isn't a comparison.|date=September 2021}}<ref name="P3Feb" /><ref name="NeWKh" /> For example, in 2011 OCZ and Marvell co-developed a native PCI Express solid-state drive controller for a PCI Express 3.0 x16 slot with maximum capacity of 12&nbsp;TB and a performance of to 7.2&nbsp;GB/s sequential transfers and up to 2.52&nbsp;million IOPS in random transfers.<ref name="VLf63" />{{Relevance inline|reason=Can't find any info on whether this product was even sold, and I can't imagine it was when the other thing OCZ was in the news for at the time were their PCIe based SSDs being constantly failing nightmares that were impossible to recover because of the proprietary interface and required drivers... Enterprise would have rightfully scoffed at those numbers, thrown a couple thousand more regular SSDs in their giant storage arrays if they needed more than the billions of IOPS they were already achieving, maybe updated from 40&nbsp;Gbps to 100&nbsp;Gbps runs between the storage servers, and called it a day.|date=September 2021}}

[[SATA Express]] was an interface for connecting SSDs through SATA-compatible ports, optionally providing multiple PCI Express lanes as a pure PCI Express connection to the attached storage device.<ref name="ymSig" /> [[M.2]] is a specification for internally mounted computer [[expansion card]]s and associated connectors, which also uses multiple PCI Express lanes.<ref name="SNLQe" />

PCI Express storage devices can implement both [[AHCI]] logical interface for backward compatibility, and [[NVM Express]] logical interface for much faster I/O operations provided by utilizing internal parallelism offered by such devices. Enterprise-class SSDs can also implement [[SCSI over PCI Express]].<ref name="FJvMX" />

=== Cluster interconnect ===
Certain [[data-center]] applications (such as large [[computer cluster]]s) require the use of fiber-optic interconnects due to the distance limitations inherent in copper cabling. Typically, a network-oriented standard such as Ethernet or [[Fibre Channel]] suffices for these applications, but in some cases the overhead introduced by [[routing|routable]] protocols is undesirable and a lower-level interconnect, such as [[InfiniBand]], [[RapidIO]], or [[NUMAlink]] is needed. Local-bus standards such as PCIe and [[HyperTransport]] can in principle be used for this purpose,<ref name="YUum6" /> but {{as of | 2015 | lc = on}}, solutions are only available from niche vendors such as [[Dolphin Interconnect Solutions|Dolphin ICS]], and TTTech Auto.

== Competing protocols ==
Other communications standards based on high bandwidth serial architectures include [[InfiniBand]], [[RapidIO]], [[HyperTransport]], [[Intel QuickPath Interconnect]], the [[Mobile Industry Processor Interface]] (MIPI), and [[NVLink]]. Differences are based on the trade-offs between flexibility and extensibility vs latency and overhead. For example, making the system hot-pluggable, as with Infiniband but not PCI Express, requires that software track network topology changes.{{citation needed|date=February 2021}}

Another example is making the packets shorter to decrease latency (as is required if a bus must operate as a memory interface). Smaller packets mean packet headers consume a higher percentage of the packet, thus decreasing the effective bandwidth. Examples of bus protocols designed for this purpose are RapidIO and HyperTransport.{{citation needed|date=February 2021}}

{{Clarify|date=September 2024|text=PCI Express falls somewhere in the middle,|reason=In the middle of *what*? What are the endpoints? Nothing above talks about device interconnects or routed network protocols; some discussion of routing was removed in a February 2019 edit, leaving this paragraph missing some context.}} targeted by design as a system interconnect ([[local bus]]) rather than a device interconnect or routed network protocol. Additionally, its design goal of software transparency constrains the protocol and raises its latency somewhat.{{citation needed|date=February 2021}}

Delays in PCIe 4.0 implementations led to the [[Gen-Z (consortium)|Gen-Z]] consortium, the CCIX effort and an open [[Coherent Accelerator Processor Interface]] (CAPI) all being announced by the end of 2016.<ref name="1Jwlv" />

On 11 March 2019, Intel presented [[Compute Express Link|Compute Express Link (CXL)]], a new interconnect bus, based on the PCI Express 5.0 physical layer infrastructure. The initial promoters of the CXL specification included: [[Alibaba Group|Alibaba]], [[Cisco]], [[Dell EMC]], [[Facebook]], [[Google]], [[Hewlett Packard Enterprise|HPE]], [[Huawei]], [[Intel]] and [[Microsoft]].<ref name="aJ00L" />

== Integrators list ==
The PCI-SIG Integrators List lists products made by PCI-SIG member companies that have passed compliance testing. The list include switches, bridges, NICs, SSDs, etc.<ref name="9ps7Q" />

== See also ==
{{Portal|Electronics}}

{{Div col|colwidth=22em}}
* [[Active State Power Management]] (ASPM)
* [[Peripheral Component Interconnect]] (PCI)
* [[PCI configuration space]]
* [[PCI-X]] (PCI Extended)
* [[PCI/104-Express]]
* [[PCIe/104]]
* [[Root complex]]
* [[Serial Digital Video Out]] (SDVO)
* {{Section link|List of device bit rates|Main buses}}
* [[UCIe]]
* [[Compute Express Link]] (CXL)
{{div col end}}

== Notes ==
{{notelist}}

== References ==
{{reflist|1=30em|refs=
<ref name="pcie-basics">{{cite web |url = http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=4e00a39acaa5c5a8ee44ebb07baba982e5972c67 |title = PCI Express Basics |date = 2007-08-21 |access-date = 2014-07-15 |author = Ravi Budruk |publisher = [[PCI-SIG]] |format = PDF |url-status = dead |archive-url = https://web.archive.org/web/20140715120034/http://www.pcisig.com/developers/main/training_materials/get_document?doc_id=4e00a39acaa5c5a8ee44ebb07baba982e5972c67 |archive-date = 2014-07-15}}</ref>
<ref name="howstuffworks1">{{cite web | url = http://computer.howstuffworks.com/pci-express.htm | work = How Stuff Works | title = How PCI Express Works | access-date = 2009-12-07 | url-status = live | archive-url = https://web.archive.org/web/20091203053924/http://computer.howstuffworks.com/pci-express.htm | archive-date = 2009-12-03 | date = 2005-08-17|first1=Tracy V. |last1=Wilson}}</ref>
<ref name="faq1">{{cite web |url = http://www.pcisig.com/news_room/faqs/faq_express/ |title = PCI Express Architecture Frequently Asked Questions |publisher = PCI-SIG |access-date = 23 November 2008 |url-status = dead |archive-url = https://web.archive.org/web/20081113163608/http://www.pcisig.com/news_room/faqs/faq_express/ |archive-date = 13 November 2008}}</ref>
<ref name="PCIe card 2">{{Citation | title = PCI Express Card Electromechanical Specification Revision 2.0}}</ref>
<ref name="CEM1.1">''PCI Express Card Electromechanical Specification Revision 1.1''</ref>
<ref name="JuErgh">{{cite web|title=Mini-Fit® PCI Express®* Wire to Board Connector System|url=https://www.molex.com/pdm_docs/ps/PS-45558-001-001.pdf|access-date=4 December 2020}}</ref>
<ref name="CEM3.0">''PCI Express Card Electromechanical Specification Revision 3.0''</ref>
<ref name="EeePC">{{cite web|url=http://beta.ivancover.com/wiki/index.php/Eee_PC_Research|title=Eee PC Research|type=wiki|work=ivc|access-date=26 October 2009|url-status=usurped|archive-url=https://web.archive.org/web/20100330035948/http://beta.ivancover.com/wiki/index.php/Eee_PC_Research|archive-date=30 March 2010}}</ref>
<ref name="pcie_cabling1.0">{{cite web| title = PCI Express External Cabling 1.0 Specification| access-date = 9 February 2007| url = http://www.pcisig.com/specifications/pciexpress/pcie_cabling1.0/| url-status = live| archive-url = https://web.archive.org/web/20070210055546/http://www.pcisig.com/specifications/pciexpress/pcie_cabling1.0/| archive-date = 10 February 2007}}</ref>
<ref name="PoRghEr">{{Citation | title = PCI SIG discusses M-PCIe oculink & 4th gen PCIe | date = 13 September 2013 | newspaper = The Register | place = [[United Kingdom|UK]] | url = https://www.theregister.co.uk/Print/2013/09/13/pci_sig_discusses_m_pcie_oculink_and_fourth_gen_pcie/ | url-status = live | archive-url = https://web.archive.org/web/20170629201006/http://www.theregister.co.uk/Print/2013/09/13/pci_sig_discusses_m_pcie_oculink_and_fourth_gen_pcie/ | archive-date = 29 June 2017}}</ref>
<ref name="faq4">{{cite web|url = http://www.pcisig.com/news_room/faqs/FAQ_PCI_Express_4.0/#EQ3|archive-url = https://web.archive.org/web/20140518224913/http://www.pcisig.com/news_room/faqs/FAQ_PCI_Express_4.0/#EQ3|title = PCI Express 4.0 Frequently Asked Questions|access-date = 2014-05-18|archive-date = 2014-05-18|publisher = PCI-SIG|work = pcisig.com}}</ref>
<ref name="PCIExpressPressRelease">{{cite press release | title = PCI Express Base 2.0 specification announced | publisher = [[PCI-SIG]] | date = 15 January 2007 | access-date = 9 February 2007 | url = http://www.pcisig.com/news_room/PCIe2_0_Spec_Release_FINAL2.pdf | url-status = dead | archive-url = https://web.archive.org/web/20070304101327/http://www.pcisig.com/news_room/PCIe2_0_Spec_Release_FINAL2.pdf | archive-date = 4 March 2007}} — note that in this press release the term ''aggregate bandwidth'' refers to the sum of incoming and outgoing bandwidth; using this terminology the aggregate bandwidth of full duplex 100BASE-TX is 200{{nbsp}}Mbit/s.</ref>
<ref name="extrmetech">{{Cite news |url= http://www.extremetech.com/article2/0,1697,2169018,00.asp |title= PCI Express 3.0 Bandwidth: 8.0 Gigatransfers/s |publisher= ExtremeTech |date= 9 August 2007 |access-date= 5 September 2007 |url-status= live |archive-url= https://web.archive.org/web/20071024140702/http://www.extremetech.com/article2/0,1697,2169018,00.asp |archive-date= 24 October 2007}}</ref>
<ref name="faq3">{{cite web | url = http://www.pcisig.com/news_room/faqs/pcie3.0_faq/#EQ2 | archive-url = https://web.archive.org/web/20140201172536/http://www.pcisig.com/news_room/faqs/pcie3.0_faq/#EQ2 | title = PCI Express 3.0 Frequently Asked Questions | access-date = 2014-05-01 | archive-date = 2014-02-01 | publisher = PCI-SIG | work = pcisig.com}}</ref>
<ref name="OCuLink2">{{cite web|url=https://www.connectortips.com/oculink-connectors-cables-support-new-pcie-standard/|archiveurl=https://web.archive.org/web/20170313215047/http://www.connectortips.com/oculink-connectors-cables-support-new-pcie-standard/|url-status=dead|title=OCuLink connectors and cables support new PCIe standard|archivedate=March 13, 2017|website=www.connectortips.com}}</ref>
<ref name="EE_4+5">{{cite magazine |url=http://www.eetimes.com/document.asp?doc_id=1330006 |title=PCIe 4.0 Heads to Fab, 5.0 to Lab |magazine=EE Times |date=2016-06-26 |access-date=2016-08-27 |url-status=live |archive-url=https://web.archive.org/web/20160828221858/http://www.eetimes.com/document.asp?doc_id=1330006 |archive-date=2016-08-28}}</ref>
<ref name="heise_idf_2016">{{cite web |url=http://www.heise.de/newsticker/meldung/IDF-PCIe-4-0-laeuft-PCIe-5-0-in-Arbeit-3297114.html |title=IDF: PCIe 4.0 läuft, PCIe 5.0 in Arbeit |language=de |website=[[Heise Online]] |date=2016-08-18 |access-date=2016-08-18 |url-status=live |archive-url=https://web.archive.org/web/20160819153631/http://www.heise.de/newsticker/meldung/IDF-PCIe-4-0-laeuft-PCIe-5-0-in-Arbeit-3297114.html |archive-date=2016-08-19}}</ref>
<ref name="TR_pcie4">{{cite news|last1=Born|first1=Eric|title=PCIe 4.0 specification finally out with 16 GT/s on tap|url=https://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap|access-date=8 June 2017|publisher=Tech Report|date=8 June 2017|url-status=live|archive-url=https://web.archive.org/web/20170608155216/http://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gt-s-on-tap|archive-date=8 June 2017}}</ref>
<ref name="PCIe5r09">{{cite web|url=http://pcisig.com/doubling-bandwidth-under-two-years-pci-express®-base-specification-revision-50-version-09-now|title=Doubling Bandwidth in Under Two Years: PCI Express® Base Specification Revision 5.0, Version 0.9 is Now Available to Members|website=pcisig.com|language=en|access-date=2018-12-12}}</ref>
<ref name="businesswire.com">{{cite web|url=https://www.businesswire.com/news/home/20190618005945/en/PCI-SIG%C2%AE-Announces-Upcoming-PCI-Express%C2%AE-6.0-Specification-to-Reach-64-GTs|title=PCI-SIG® Announces Upcoming PCI Express® 6.0 Specification to Reach 64 GT/s|date=June 18, 2019|website=www.businesswire.com}}</ref>
<ref name="PCIeFiber">{{cite web |url=http://www.cablinginstall.com/index/display/article-display/8876181966/articles/cabling-installation-maintenance/news/data-center/2011/6/plx-demo_shows_pcie.html |title=PLX demo shows PCIe over fiber as data center clustering interconnect |publisher=Penn Well |work=Cabling install |access-date=29 August 2012 }}{{Dead link|date=April 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref>
<ref name="adnacoPCIe">{{cite web |url=http://www.adnaco.com/2011/09/03/new1 |date=2011-04-22 |title=Introduced second generation PCI Express Gen 2 over fiber optic systems |publisher=Adnaco |access-date=29 August 2012 |url-status=live |archive-url=https://web.archive.org/web/20121004094357/http://www.adnaco.com/2011/09/03/new1/ |archive-date=4 October 2012}}</ref>
<ref name="pipe_spec">{{cite web | title = PHY Interface for the PCI Express Architecture | edition = version 2.00 | access-date = 21 May 2008 | publisher = Intel | url = http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf | url-status = dead | archive-url = https://web.archive.org/web/20080317171752/http://download.intel.com/technology/pciexpress/devnet/docs/pipe2_00.pdf | archive-date = 17 March 2008}}</ref>
<ref name="pcie_schematics1">{{cite web | publisher = Interface bus | title = Mechanical Drawing for PCI Express Connector | access-date = 7 December 2007 | url = http://www.interfacebus.com/PCI-Express-Bus-PCIe-Description.html#d}}</ref>
<ref name="pcie_schematics2">{{cite web | url = http://portal.fciconnect.com/Comergent/fci/drawing/10018783.pdf | title = FCi schematic for PCIe connectors | publisher = FCI connect | access-date = 7 December 2007}}</ref>
<ref name="traffic_profile">{{cite book| url=https://books.google.com/books?id=Xp7-NKsJ8_sC&dq=frequent+enforced+acknowledgements/&pg=PA35| title=Computer Peripherals And Interfaces| year=2008| publisher=Technical Publications Pune| isbn=9788184313086| access-date=23 July 2009| url-status=live| archive-url=https://web.archive.org/web/20140225203956/http://www.google.com/books?id=Xp7-NKsJ8_sC&pg=PA35&dq=frequent+enforced+acknowledgements%2F| archive-date=25 February 2014}}</ref>
<ref name="s5NDG">{{cite book |chapter=PCI express and advanced switching: Evolutionary path to building next generation interconnects |pages=21–29 |doi=10.1109/CONECT.2003.1231473 |date=August 2003 |title=11th Symposium on High Performance Interconnects, 2003. Proceedings. |last1=Mayhew |first1=D. |last2=Krishnan |first2=V. |isbn=0-7695-2012-X |s2cid=7456382}}</ref>
<ref name="DQmzv">{{cite web | url=https://www.pcmag.com/encyclopedia/term/48998/pci-express | title=Definition of PCI Express|work = PCMag}}</ref>
<ref name="gf9Lm">{{cite web | publisher = Fedora project | url = http://ols.fedoraproject.org/OLS/Reprints-2007/zhang-Reprint.pdf | title = Enable PCI Express Advanced Error Reporting in the Kernel | work = Proceedings of the Linux Symposium | first1 = Yanmin | last1 = Zhang | first2 = T Long | last2 = Nguyen | date = June 2007 | url-status = dead | archive-url = https://web.archive.org/web/20160310074031/https://ols.fedoraproject.org/OLS/Reprints-2007/zhang-Reprint.pdf | archive-date = 2016-03-10 | access-date = 2012-05-08}}</ref>
<ref name="sxOen">https://www.hyperstone.com Flash Memory Form Factors – The Fundamentals of Reliable Flash Storage, Retrieved 19 April 2018</ref>
<ref name="4TrCr">{{Citation | title=PCI Express Base Specification, Revision 2.1. | chapter=4.2.4.9. Link Width and Lane Sequence Negotiation | date=4 March 2009}}</ref>
<ref name="2Nt8T">{{cite web | work = Interface bus | url = http://www.interfacebus.com/Design_Connector_PCI_Express.html | title = PCI Express Bus | access-date = 2010-06-12 | url-status = dead | archive-url = https://web.archive.org/web/20071208162241/http://www.interfacebus.com/Design_Connector_PCI_Express.html | archive-date = 2007-12-08}}</ref>
<ref name="Gchhw">32 lanes are defined by the ''PCIe Base Specification'' up to PCIe 5.0 but there's no card standard in the ''PCIe Card Electromechanical Specification'' and that lane number was never implemented.</ref>
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<ref name="o2GFI">''PCI Express x16 Graphics 150W-ATX Specification Revision 1.0''</ref>
<ref name="uLc7Q">''PCI Express 225 W/300 W High Power Card Electromechanical Specification Revision 1.0''</ref>
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<ref name="iPAaS">''PCI Express Base Specification, Revision 3.0'' Table 4-24</ref>
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<ref name="PCIe70v05">{{cite web|url=https://pcisig.com/blog/pcie%C2%AE-70-specification-version-05-now-available-full-draft-available-members | title = PCIe® 7.0 Specification, Version 0.5 Now Available: Full Draft Available to Members|website=pcisig.com|language=en|access-date=2024-04-03}}</ref>
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<ref name="PCIe70v09">{{cite web|url=https://pcisig.com/blog/pcie-70-specification-version-09-final-draft-now-available-member-review | title = PCIe 7.0 Specification, Version 0.9: Final Draft Now Available for Member Review|website=pcisig.com|language=en|access-date=2025-03-19}}</ref>
}}


== Further reading ==
<!-- WARNING: DO NOT POST LINKS TO ANY PIRATED SPECS. See DMCA take-down notice at [[wmf:File:DMCA PCI.pdf]] -->
* {{Citation | title = PCI Express System Architecture | series = Mind share PC system architecture | editor-first = Joseph ‘Joe’ | editor-last = Winkles | first1 = Ravi | last1 = Budruk | first2 = Don | last2 = Anderson | first3 = Tom | last3 = Shanley | year = 2003 | isbn = 978-0-321-15630-3 | publisher = Addison-Wesley}}, 1120 pp.
* {{Citation | first1 = Edward | last1 = Solari | first2 = Brad | last2 = Congdon | publisher = Intel | title = Complete PCI Express Reference: Design Implications for Hardware and Software Developers | year = 2003 | isbn = 978-0-9717861-9-6}}, 1056 pp.
* {{Citation | first1 = Adam | last1 = Wilen | first2 = Justin P | last2 = Schade | first3 = Ron | last3 = Thornburg |date=Apr 2003 | title = Introduction to PCI Express: A Hardware and Software Developer's Guide | isbn = 978-0-9702846-9-3 | publisher = Intel}}, 325 pp.

== External links ==
* {{commons category-inline}}
* [https://pcisig.com/specifications PCI-SIG Specifications]
<!-- WARNING: Do NOT post links to any pirated specs. See DMCA take-down notice at [[wmf:File:DMCA PCI.pdf]] -->

{{Computer bus}}
{{Basic computer components}}

[[Category:Computer-related introductions in 2004]]
[[Category:Peripheral Component Interconnect]]
[[Category:Serial buses]]
[[Category:Computer standards]]
[[Category:Motherboard expansion slot]]