Editing Place and route

{{Short description|Stage of electronic circuit design}}
{{Use American English|date = April 2019}}

'''Place and route''' (also called PnR or P&R) is a stage in the design of [[printed circuit board]]s, [[integrated circuits]], and [[field-programmable gate array]]s. As implied by the name, it is composed of two steps, [[placement (EDA)|placement]] and [[routing (electronic design automation)|routing]]. The first step, placement, involves deciding where to place all [[electronic components]], [[circuitry]], and [[logic]] elements in a generally limited amount of space. This is followed by routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process.

Place and route is used in several contexts:
* [[Printed circuit board]]s, during which [[electronic component|component]]s are graphically placed on the board and the wires drawn between them
* [[Integrated circuit]]s, during which a [[integrated circuit layout|layout]] of a larger block of the circuit or the whole circuit is created from layouts of smaller sub-blocks
* [[Field-programmable gate array|FPGA]]s, during which [[logic]] elements are placed and interconnected on the grid of the FPGA

These processes are similar at a high level, but the actual details are very different. With the large sizes of modern designs, this operation is usually performed by [[electronic design automation]] (EDA) tools.

In all these contexts, the final result when placing and routing is finished is the "layout", a geometric description of the location and rotation of each part, and the exact path of each wire connecting them.

Occasionally some people call the entire place-and-route process "layout".

==Printed circuit board==
The design of a printed circuit board comes after the creation of a [[Circuit diagram|schematic]] and generation of a [[netlist]]. The generated netlist is then read into a layout tool and associated with the footprints of the devices from a library. Placing and routing the devices can now start.<ref name="Layout_book">{{Cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|page=26-27|chapter=Chap. 1.3.3: Physical Design of Printed Circuit Boards|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0 |isbn=978-3-030-39284-0|s2cid=215840278 }}</ref>

Placing and routing is generally done in two steps.  [[Placement (EDA)|Placing]] the components comes first, then [[Routing (EDA)|routing]] the connections between the components.  The placement of components is not absolute during the routing phase, as it may still be changed by moving and rotating, especially with designs using more complex components such as FPGAs or microprocessors.  Their large number of [[signal (electrical engineering)|signal]]s, and their [[signal integrity]] needs may require optimization of the placement.<ref name="PCDandF">{{cite web |url = http://pcdandf.com/cms/content/view/4345/95/ |title = FPGA/PCB Co-Design Increases Fabrication Yields |access-date = 2008-07-24 |publisher=Printed Circuit Design and Fabrication}}</ref>

The resulting design is then output in RS-274X [[Gerber format]] to load in the [[Computer-aided_manufacturing|computer-aided manufacturing (CAM)]] system of the manufacturer. In contrast to an IC layout, where the entire finished layout is stored in one graphics file, different files and formats are needed for PCB manufacture. The fabrication data consists of a set of Gerber files, a drill file, and a pick-and-place file containing the location and alignment of the devices generated for automated placement of the devices in the assembly process.<ref name="Layout_book" />

==Field-programmable gate array==
The process of placing and routing for an FPGA is generally not performed by a person, but uses a tool provided by the FPGA Vendor or  another software manufacturer.  The need for software tools is because of the complexity of the circuitry within the FPGA and the function the designer wishes to perform.  FPGA designs are described using logic diagrams containing [[digital logic]] and [[hardware description language|hardware description languages]] such as [[VHDL]] and [[Verilog]].  These will then be put through an automated place-and-route procedure to generate a pinout, which will be used to interface with the parts outside of the FPGA.<ref name="PCDandF" />

==Integrated circuits==
The IC place-and-route stage typically starts with one or more schematics, HDL files, or pre-routed [[IP core]]s, or some combination of all three. It produces an IC layout that is automatically converted to a [[mask work]] in the standard [[GDS II Stream Format|GDS II]] or the [[Open Artwork System Interchange Standard|OASIS]] format.<ref>A. Kahng, J. Lienig, I. Markov, J. Hu: "VLSI Physical Design: From Graph Partitioning to Timing Closure", Springer (2022), {{doi|10.1007/978-3-030-96415-3}}, {{ISBN|978-3-030-96414-6}}, pp. 5-10.</ref>

== History ==
The final layout of early ICs and PCBs was stored as a [[tape-out]] of [[Rubylith]] on [[transparency (projection) | transparent film]].

Gradually, [[electronic design automation]] automated more and more of the place-and-route work. At first, it merely sped up the process of making many small edits without spending a lot of time peeling up and sticking down the tape. Later [[design rule checking]] sped up the process of checking for the most common sorts of errors. Later auto routers speed up the process of routing.

Some people hope that further improvements in autoplacers and autorouters will eventually produce good layouts without any human manual intervention. Further automation leads to the idea of a [[silicon compiler]].

==References== 
{{reflist|1}}

{{Digital electronics}}
[[Category:Electronic design automation]]