Editing Propagation delay

{{short description|Time for a signal or other quantity to reach its destination}}
{{Use American English|date=January 2019}}

'''Propagation delay''' is the time duration taken for a signal to reach its destination, for example in the [[electromagnetic]] field, a wire, [[speed of sound|gas]], fluid or [[seismic wave|solid body]].

== Physics ==

* An electromagnetic wave travelling through a medium has a propagation delay determined by the [[speed of light]] in that particular medium, or ca. 1 [[nanosecond]] per {{convert|29.98|cm|in}} in a [[vacuum]].
* An electric signal travelling through a wire has an propagation delay of ca. 1 nanosecond per {{convert|15|cm|in}}.<ref name='Complete digital design'>{{Cite book | last = Balch | first = Mark | title = Mcgraw Hill - Complete Digital Design A Comprehensive Guide To Digital Electronics And Computer System Architecture | publisher = McGraw-Hill Professional | year = 2003 | pages = 430 | url = https://books.google.com/books?id=uFSRT-OIxyoC | isbn = 978-0-07-140927-8 }}</ref>

See also [[radio propagation]], [[velocity factor]], [[signal velocity]] and [[mechanical wave]].

== Electronics ==

[[File:Propagation delay timing diagram.svg|thumb|400px|Propagation delay [[Digital timing diagram|timing diagram]] of a [[NOT gate]]]]

[[File:Full-Adder Propagation Delay.svg|thumb|400px|A [[full adder]] has an overall gate delay of 3 [[logic gate]]s from the inputs ''A'' and ''B'' to the carry output ''C''<sub>out</sub> shown in red.]]

[[Logic gate]]s can have a '''gate delay''' ranging from [[picosecond]]s to more than 10 nanoseconds, depending on the technology being used.<ref name='Complete digital design'/> It is the time between the gate input becoming stable and the gate output becoming stable. Manufacturers often refer to the time from the input changing to 50% of its final input level, to the output reaching 50% of its final output level; this may depend on the direction of the level change, in which case separate fall and rise delays t<sub>PHL</sub> and t<sub>PLH</sub> or t<sub>f</sub> and t<sub>r</sub> are given.

Reducing gate delays allows [[digital circuit]]s to process data at a faster rate and improve overall performance. Determining the propagation delay of a combined circuit requires identifying the longest path of propagation delays from input to output, and adding each propagation delay along this path.

The [[principle of logical effort]] utilizes propagation delays to compare designs implementing the same logical statement. The difference in propagation delays of logic elements is the major contributor to [[glitch]]es in [[asynchronous circuit]]s as a result of [[race condition]]s.

* Propagation delay may increase or decrease with [[operating temperature]] depending on the device type. As the temperature increases the gate delay decreases for FinFET transistors due to [[Inverse Temperature Dependence]]; for metal wires and other conductive materials the propagation delay increases due to rising [[electrical resistance]].
* Marginal increases in supply voltage can increase propagation delay, since the upper switching threshold voltage V<sub>IH</sub> (often expressed as a percentage of the high-voltage supply rail) naturally increases proportionately.<ref>{{cite web|title=Logic Signal Voltage Levels|url=http://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/|website=All About Circuits|access-date=1 June 2016}}</ref>
* Increases in output load capacitance, often from placing increased fan-out loads on a wire, will also increase propagation delay.

All of these factors influence each other through an [[RC time constant]]: any increase in load capacitance increases C, heat-induced resistance the R factor, and supply threshold voltage increases will affect whether more than one time constants are required to reach the threshold.  If the output of a logic gate is connected to a long trace or used to drive many other gates (high [[fanout]]) the propagation delay increases substantially.

== Networking ==

In computer networks, propagation delay is the amount of time it takes for the head of the signal to travel from the sender to the receiver. It can be computed as the ratio between the link length and the propagation speed over the specific medium.

Propagation delay is equal to ''d / s'' where ''d'' is the distance and ''s'' is the [[wave propagation speed]]. In wireless communication, ''s''=''c'', i.e. the [[speed of light]]. In [[copper wire]], the speed ''s'' generally ranges from .59c to .77c.<ref name="Ethernet propagation delay">{{cite web | url = http://stason.org/TULARC/networking/lans-ethernet/3-11-What-is-propagation-delay-Ethernet-Physical-Layer.html | title=What is propagation delay? (Ethernet Physical Layer) | access-date = 2010-11-09 | date = 2010-10-21 | work = Ethernet FAQ}}</ref><ref name="Propagation Delay">{{cite web | url = http://www.wildpackets.com/resources/compendium/ethernet/propagation_delay | title=Propagation Delay and Its Relationship to Maximum Cable Length | access-date = 2010-11-09 | work = Networking Glossary | archive-url = https://web.archive.org/web/20110220015404/http://www.wildpackets.com/resources/compendium/ethernet/propagation_delay | archive-date = 2011-02-20 | url-status = dead}}</ref> This delay is the major obstacle in the development of high-speed computers and is called the [[interconnect bottleneck]] in IC systems.

== See also ==

* [[Contamination delay]]
* [[Delay calculation]]
* [[Latency (engineering)]]
* [[Time of flight]]
* [[Transmission delay]]


== References ==

{{Reflist}}

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[[Category:Digital circuits]]
[[Category:Electronics concepts]]
[[Category:Timing in electronic circuits]]