Editing Q-Bus

{{short description|Computer bus}}
{{Infobox Computer Hardware Bus
| name        = Q-Bus
| fullname    = Q-Bus
| image       =DEC_MicroVAX_II_CPU_KA630-AA_M7606.jpg
| caption     =DEC [[MicroVAX]] II CPU card (quad height)
| invent-date =
| invent-name = [[Digital Equipment Corporation]]
| super-name  =[[VAXBI bus]]
| super-date  =1986
| width       = 8 or 16-bit data, 16-bit address extended to 22-bit
| numdev      = 127 in theory, ~20 in practice
| speed       =
| hotplug     =No
| style       = p
| external    =No
|replaces=[[Unibus]]}}
The '''Q-bus''',<ref>{{cite book| last=Schmidt |first=Atlant G. |chapter=Unibus, Q-Bus and VAXBI Bus |title=Digital bus handbook |chapter-url=https://archive.org/details/digitalbushandbo0000unse/page/n131/mode/2up |chapter-url-access=registration |editor=Di Giacomo Joseph |publisher=McGraw Hill |year=1990 |isbn=0070169233}}</ref> also known as the '''LSI-11 Bus''', is one of several [[bus (computing)|bus]] technologies used with [[Programmed Data Processor|PDP]] and [[VAX|MicroVAX]] computer systems previously manufactured by the [[Digital Equipment Corporation]] of [[Maynard, Massachusetts|Maynard]], [[Massachusetts]].

The Q-bus is a less expensive version of [[Unibus]] using multiplexing so that address and data signals share the same wires.<ref name=":0">{{Cite book |url=https://archive.org/details/bitsavers_dechandboomsHandbook1985_21400965 |title=digital Microsystems Handbook 1985 |date=1985 |pages= |language=en}}</ref> This allows both a physically smaller and less-expensive implementation of essentially the same functionality.

Over time, the physical address range of the Q-bus was expanded from 16 to 18 and then 22 bits. Block transfer modes were also added to the Q-bus.<ref name=":0" />

==Main features of the Q-bus==
[[File:DEC LSI11-23.jpg|thumb|LSI-11/23 Q-Bus [[expansion card]]s and slots]]
[[File:BA213.jpg|thumb|DEC BA213 cabinet; 12 Q-Bus-22 slots]]The Q-bus is arranged as a series of [[Expansion card|modules]] installed in one or more [[Backplane|backplanes]].

Like the Unibus before it, the Q-bus uses:<ref>{{Cite book |url=http://www.bitsavers.org/pdf/dec/qbus/Digital_Microcomputer_Products_Handbook_1985.pdf |title=digital Microcomputer Products Handbook |year=1985}}</ref><ref>{{Cite book |url=http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP-11_Bus_Handbook_1979.pdf |title=PDP-11 Bus Handbook |year=1979}}</ref>
* ''[[Memory-mapped I/O]]''
* ''[[Byte addressing]]''
* A strict ''[[Master-slave (computers)|master-slave]]'' relationship between devices on the bus
* ''[[Asynchronous communication|Asynchronous signaling]]''

''Memory-mapped I/O'' means that data cycles between any two devices, whether CPU, memory, or I/O devices, use the same protocols. On the Unibus, a range of physical addresses are dedicated for I/O devices. The Q-bus simplifies this design by providing a specific signal (originally called ''BBS7'', ''Bus Bank Select 7'' but later generalized to be called ''BBSIO'', ''Bus Bank Select I/O'') that selects the range of addresses used by the I/O devices.

''Byte addressing'' means that the physical address passed on the Unibus is interpreted as the address of a byte-sized quantity of data. Because the bus actually contains a data path that is two bytes wide, address bit <nowiki>[0]</nowiki> is subject to special interpretation and data on the bus has to travel in the correct [[byte lane]]s.

A strict ''Master-Slave'' relationship means that at any point in time, only one device can be the ''Master'' of the Q-bus. This ''master device'' can initiate data transactions which can then be responded to by a maximum of one selected ''slave device''. (This had no effect on whether a given bus cycle is reading or writing data; the bus master can command either type of transaction.) At the end of the bus cycle, a ''[[bus arbitration]]'' protocol then selects the next device to be given mastery of the bus.

''Asynchronous signaling'' means that the bus has no fixed cycle time; the duration of any particular data transfer cycle on the bus is determined solely by the master and slave devices participating in the current data cycle. These devices use ''[[Handshake (computing)|handshake]]'' signals to control the timing of the data cycle. [[Timeout (computing)|Timeout logic]] within the master device limits the maximum allowed length of any given bus cycle.

Depending on its generation, the Q-bus contains 16, 18, or 22 ''BDAL'' (''Bus Data/Address Line'') lines. 16, 18, or 22 BDAL lines are used for the physical address portion of each bus cycle. Eight or 16 DBAL lines are then re-used for the data portion(s) of each bus cycle. Newer generations of the bus allow [[burst mode (computing)|''block mode'' transfer]] where a single bus address can be followed by more than one data cycle (with the transfers taking place at consecutive bus addresses). Because the address portion of each bus cycle can not transfer data, the use of block mode means fewer address cycles and more time for data cycles, allowing increased bus data transfer [[Bandwidth (computing)|bandwidth]].

[[Bus master]]y is awarded based on an I/O card's topological proximity to the [[bus arbiter|bus arbitrator]] (at the logical front of the bus); closer cards are granted priority over further cards.

Interrupts can be delivered to the ''Interrupt Fielding Processor'' at any of four [[interrupt priority level]]s. Within a given level, the cards closer to the IFP (at the front of the bus) take priority over cards further back on the bus. [[Vectored Interrupt|Interrupts are vectored]]: a card requesting an interrupt has its interrupt vector read by the IFP. In this way, the interrupts from all I/O cards in the system can be distinguished with no ambiguity.

== Physical characteristics ==
Q-bus modules are configured as printed-circuit boards with gold-plated card-edge connectors which mate with corresponding slots on a backplane. The edge connectors on the modules are split into individual "fingers," similarly to Unibus modules, but are limited to four connectors, compared to the six of Unibus. Modules are available in either double-height (two connectors) or quad-height (four connectors) sizes. This nomenclature is somewhat non-intuitive, as the difference between the two is actually the ''width'' of the PCB. Quad-height modules tend to be used for CPUs, memory, video processors, and other high-bandwidth components, whereas double-height modules tend to be used for interface cards, connector breakout boards, real-time clocks, ROM/microcode, and other relatively low-bandwidth components. Some exceptions are the double-height LSI-11/2, KDF11-A, and KDJ11-A CPUs, and many early small-capacity memory modules.

==Logic minimization==
As with the Unibus, the signaling was carefully optimized so that the minimum amount of logic is required across the entire bus system. Asynchronous signaling is used but de-skewing of addresses and data is the responsibility of the current bus master, minimizing the complexity of the bus slave devices. The responsibility for timing-out failed bus cycles also is placed in the master devices. Similarly, the complexities of handling interrupt transactions are concentrated into the single ''Interrupt-Fielding Processor'' (the PDP-11 or VAX-11 computer) in the system.

==Compatibility==
The design of the Q-bus was very closely related to the design of the Unibus both in spirit and in detailed implementation. Adapters were available from Digital and from third parties that allow Q-bus devices to be connected to Unibus-based computers and vice versa.<ref>{{Cite book |url=http://www.bitsavers.org/pdf/dec/pdp11/1184/EK-1184E-TM-001_Dec87.pdf |title=PDP-11/84 System Technical and Reference Manual |date=December 1987 |pages=1‐2,2‐52–2‐69 |language=en}}</ref> A number of I/O devices were available in either Unibus or Q-bus flavors; some of these devices have minor differences while many others were essentially identical.

==Soviet clones==
In Soviet systems (see [[1801 series CPU]]), the Q-Bus architecture is called '''МПИ''' (''Магистральный Параллельный Интерфейс'', or parallel bus interface). Its main difference is that it supports up to four processors on the same bus. Otherwise it is completely binary and electrically compatible with the standard Q-Bus, except for the physical layout of connectors.

==Cycle Types==
The Q-Bus supports 6 basic transaction types:<ref name=":0" />
 DATI Data in - master read - note no DATIB (not required)
 DATO Data out - master write
 DATOB Data out (byte)
 DATIO Data in/out
 DATIOB Data in/out (byte)
 IAK Interrupt Acknowledge

== Device Types ==
A wide range of module types are available for the Q-Bus. Generally, they can be categorized as:

* CPU modules
* Memory modules
* Interface modules
* System modules (grant continuity cards, connector breakout boards, etc)

==Interfaces==
 {{multiple image
| perrow            = 2
| total_width       = 450
| image1            = Bubbl-tec QSB-11A Bubbl-Board for DEC Qbus, component side (19257373711).jpg
| caption1          = 1 MBit [[Bubble memory]] dual-width Q-Bus [[expansion card]]
| image2            = Core memory.jpg
| caption2          = 8K × 19 bit [[core memory]] quad-width Q-Bus [[expansion card]]
| image4            = Intergraph PCB484 MicroVAX II memory module.jpg
| caption4          = DEC MicroVAX II memory card (quad width)
}}
A wide range of interface cards are available for the Q-Bus. Various Q-bus modules can be dual-width (two sets of fingers, half the total width of the mounting), or quad-width (four sets of fingers, the full width of the mounting), indicating that the module occupies one-half of or all of the Q-bus mounting slot, respectively.

==External links==
* {{cite web| url=http://hoffmanlabs.org/openvms/hwvax/hwqbus.shtml#topofpage |title=HP OpenVMS :: Q-Bus Hardware |website=HoffmanLabs |archive-url=https://web.archive.org/web/20210311023428/http://hoffmanlabs.org/openvms/hwvax/hwqbus.shtml |archive-date=11 March 2021}}
* {{cite web| url=http://www.runningserver.com/?page=runningserver.content.thelab.qbussample |website=RunningServer.com |title=The Lab - Q-Bus Beispielplatine, Selbstgebaute Q-BUS Platinen | archive-url=https://web.archive.org/web/20170214163740/http://www.runningserver.com/?page=runningserver.content.thelab.qbussample |archive-date=14 February 2017 |lang=de}}
* [http://bitsavers.org/pdf/dec/standards/EL-00160-00-0_A_DEC_STD_160_LSI-11_Bus_Specification_Sep91.pdf DEC STD 160: LSI-11 Bus Specification]

==References==

{{Reflist}}

{{Computer-bus}}
{{Digital Equipment Corporation}}

[[Category:DEC hardware]]
[[Category:Minicomputers]]
[[Category:Computer buses]]