Editing SIMM

{{Short description|Computer memory module}}
{{about|a type of memory module for computers}}

<!-- Commented out because image was deleted: [[Image:SIMMs.jpg|frame|30- (top) and 72-pin (bottom) SIMMs. Early 30-pin modules commonly had either 256 KB or 1 MB of memory.]] -->
[[File:SIMM 30 68 72.png|thumbnail|30-pin, proprietary Apple 68-pin, and 72-pin SIMMs]]

A '''SIMM''' ('''single in-line memory module''') is a type of [[memory module]] used in computers from the early 1980s to the early 2000s. It is a printed circuit board upon which multiple [[random-access memory]] [[Integrated circuit]] chips are attached to one or both sides.<ref name="GeeksforGeeks 2020 e240">{{cite web | title=What is DIMM(Dual Inline Memory Module)? | website=GeeksforGeeks | date=2020-04-15 | url=https://www.geeksforgeeks.org/what-is-dimmdual-inline-memory-module/ | access-date=2024-04-07 | quote=In the case of SIMM, the connectors are only present on the single side of the module...DIMM has a row of connectors on both sides(front and back) of the module}}</ref> It differs from a [[dual in-line memory module]] (DIMM), the most predominant form of memory module since the late 1990s, in that the contacts on a SIMM are [[redundancy (engineering)|redundant]] on both sides of the module. SIMMs were standardised under the [[JEDEC]] JESD-21C standard.

Most early PC [[motherboard]]s ([[Intel 8088|8088]]-based PCs, [[IBM Personal Computer XT|XT]]s, and early [[IBM Personal Computer AT|ATs]]) used socketed [[Dual in-line package|DIP]] chips for [[DRAM]]. As computer memory capacities grew, memory modules were used to save motherboard space and ease memory expansion. Instead of plugging in eight or nine single DIP chips, only one additional memory module was needed to increase the memory of the computer.

==History==
SIMMs were invented in 1983 by James E. Clayton<ref name="journal">Clayton, James E. (1983). [https://books.google.com/books?id=mawpAQAAMAAJ&q=SIP Low-cost, high-density memory packaging: A 64K X 9 DRAM SIP module], ''The International journal for hybrid microelectronics''.</ref> at [[Wang Laboratories]] with subsequent patents granted in 1987.<ref>{{US patent|4656605}} - ''Single in-line memory module''</ref>
<ref>{{US patent|4727513}} - ''Signal in-line memory module''</ref> Wang Laboratories [[RAM parity#Wang lawsuit|litigated both patents against multiple companies]].<ref>{{cite web |title=Wang Laboratories, Inc., Plaintiff/cross-appellant, v. Toshiba Corporation; Toshiba America Electronic Components, inc.; Toshiba America Information Systems, Inc., defendants-appellants, and Nec Corporation; Nec Electronics Inc. and Nec Technologies, inc., Defendants-appellants, and Molex Incorporated, Defendant, 993 F.2d 858 (Fed. Cir. 1993)|url=https://law.justia.com/cases/federal/appellate-courts/F2/993/858/310372/|website=justia.com|access-date=22 December 2023|date=May 10, 1993}}</ref><ref>{{cite web |title=Wang Laboratories, Inc., Plaintiff-appellee, v. Clearpoint Research Corporation, Defendant-appellant, 5 F.3d 1504 (Fed. Cir. 1993)|url=https://law.justia.com/cases/federal/appellate-courts/F3/5/1504/626911/|website=justia.com|access-date=22 December 2023|date=July 23, 1993}}</ref><ref>{{cite web |title=Wang Laboratories v. MITSUBISHI ELECTRONICS, 860 F. Supp. 1448 (C.D. Cal. 1993)|url=https://law.justia.com/cases/federal/district-courts/FSupp/860/1448/2159908/|website=justia.com|access-date=22 December 2023|date=December 17, 1993}}</ref><ref>{{cite web |title=Wang Laboratories, Inc., Plaintiff-appellant, v. Mitsubishi Electronics America, Inc. and Mitsubishi Electric Corporation, Defendants/cross-appellants, 103 F.3d 1571 (Fed. Cir. 1997)|url=https://law.justia.com/cases/federal/appellate-courts/F3/103/1571/518294/|website=justia.com|access-date=22 December 2023|date=January 3, 1997}}</ref><ref>{{cite web |title=Wang Laboratories v. OKI ELECTRIC INDUSTRY CO., 15 F. Supp. 2d 166 (D. Mass. 1998)|url=https://law.justia.com/cases/federal/district-courts/FSupp2/15/166/2314770/|website=justia.com|access-date=22 December 2023|date=July 31, 1998}}</ref> The original memory modules were built upon ceramic substrates with 64K Hitachi "flip chip" parts and had pins, i.e. [[single in-line package]] (SIP) [[integrated circuit packaging|packaging]].<ref name="journal" /> SIMMs using pins are usually called [[SIPP memory|SIP or SIPP memory]] modules to distinguish them from the more common modules using edge connectors.

The first variant of SIMMs has 30 pins and provides 8 [[bit]]s of data (plus a 9th error-detection bit in [[Parity bit|parity]] SIMMs). They were used in AT-compatible ([[Intel 80286|286]]-based, e.g., [[Wang APC]]<ref>[https://books.google.com/books?id=xsMx9D2s6y0C&pg=PA33 Wang Plays A Strong PC-Compatible Hand], ''PC Magazine'', October 1, 1985</ref>), [[Intel 80386|386]]-based, [[Intel 80486|486]]-based, [[Macintosh Plus]], [[Macintosh II]], [[Macintosh Quadra|Quadra]], [[Atari STE]] microcomputers, [[Wang VS]] minicomputers and [[Roland Corporation|Roland]] electronic samplers.

The second variant of SIMMs has 72 pins and provides 32 bits of data (36 bits in parity and [[ECC memory|ECC]] versions). These appeared first in the early 1990s in later models of the [[IBM PS/2]], and later in systems based on the [[Intel 80486|486]], [[Intel P5|Pentium]], [[Pentium Pro]], early [[Pentium II]], and contemporary/competing chips of other brands. By the mid-90s, 72-pin SIMMs had replaced 30-pin SIMMs in new-build computers, and were starting to themselves be replaced by [[DIMM]]s.

Non-IBM PC computers such as UNIX [[workstation]]s may use proprietary non-standard SIMMs. The [[Macintosh IIfx]] uses proprietary non-standard SIMMs with 64 pins.

DRAM technologies used in SIMMs include [[dynamic random-access memory#Page mode DRAM|FPM]] (Fast Page Mode memory, used in all 30-pin and early 72-pin modules), and the higher-performance [[dynamic random-access memory#Extended data out DRAM|EDO]] DRAM (used in later 72-pin modules).

Due to the differing data bus widths of the memory modules and some processors, sometimes several modules must be installed in identical pairs or in identical groups of four to fill a memory bank. The rule of thumb is a ''286'', ''386SX'', [[Motorola 68000|68000]] or low-end [[Motorola 68020|68020]] / [[Motorola 68030|68030]] (e.g. Atari Falcon, Mac LC) system (using a 16 bit wide data bus) would require two 30-pin SIMMs for a memory bank. On ''386DX'', ''486'', and full-spec 68020 through [[Motorola 68060|68060]] (e.g. Atari TT, Amiga 4000, Mac II) systems (32 bit data bus), either four 30-pin SIMMs or one 72-pin SIMM are required for one memory bank. On [[Intel P5|Pentium]] systems (data bus width of 64 bits), two 72-pin SIMMs are required. However, some Pentium systems have support for a "half bank mode", in which the data bus would be shortened to only 32 bits to allow operation of a single SIMM. Conversely, some 386 and 486 systems use what is known as "memory interleaving", which requires twice as many SIMMs and effectively doubles the bandwidth.

The earliest SIMM sockets were conventional push-type sockets. These were soon replaced by [[Zero insertion force|ZIF]] sockets in which the SIMM was inserted at an angle, then tilted into an upright position. To remove one, the two metal or plastic clips at each end must be pulled to the side, then the SIMM must be tilted back and pulled out (low-profile sockets reversed this convention somewhat, like SODIMMs - the modules are inserted at a "high" angle, then pushed ''down'' to become more flush with the motherboard). The earlier sockets used plastic retainer clips which were found to break, so steel clips replaced them.

Some SIMMs support [[presence detect]] (PD). Connections are made to some of the pins that encode the capacity and speed of the SIMM, so that compatible equipment can detect the properties of the SIMM. PD SIMMs can be used in equipment which does not support PD; the information is ignored. Standard SIMMs can easily be converted to support PD by fitting jumpers, if the SIMMs have solder pads to do so, or by soldering wires on.<ref>[http://www.keycruncher.com/blog/2003/12/14/making-standard-simm-s-work-memory-upgrade-on-the-hp-laserjet-6mp-5mp/ ''Making Standard SIMMs Work &ndash; Memory Upgrade on the HP LaserJet 6MP/5MP'' Article on fitting jumpers to add Presence Detect to standard SIMMs]</ref>

==30-pin SIMMs==
[[File:Atari STE 256kB RAM 1.jpg|thumbnail|30-pin SIMM, 256 KB capacity]]
[[File:SIMM Bank.jpg|thumbnail|Two 30-pin SIMM slots on an [[IBM PS/2 Model 50]] motherboard]]
Standard sizes: 256 KB, 1 MB, 4 MB, 16 MB.

30-pin SIMMs have 12 address lines, which can provide a total of 24 address bits. With an 8-bit data width, this leads to an absolute maximum capacity of 16&nbsp;MB for both parity and non-parity modules (the additional redundancy-bit chip usually does not contribute to the usable capacity).
{|class="wikitable"
|+ 30-pin SIMM
!Pin # !! Name !! Signal description
|rowspan=16|
!Pin # !! Name !! Signal description
|-
|1||V<sub>CC</sub>||+5 VDC
|16||DQ4||Data 4
|-
|2||/CAS||Column address strobe
|17||A8||Address 8
|-
|3||DQ0||Data 0
|18||A9||Address 9
|-
|4||A0||Address 0
|19||A10||Address 10
|-
|5||A1||Address 1
|20||DQ5||Data 5
|-
|6||DQ1||Data 1
|21||/WE||Write enable
|-
|7||A2||Address 2
|22||V<sub>SS</sub>||Ground
|-
|8||A3||Address 3
|23||DQ6||Data 6
|-
|9||V<sub>SS</sub>||Ground
|24||A11||Address 11
|-
|10||DQ2||Data 2
|25||DQ7||Data 7
|-
|11||A4||Address 4
|26||QP<sup>*</sup>||Data parity out
|-
|12||A5||Address 5
|27||/RAS||Row address strobe
|-
|13||DQ3||Data 3
|28||/CASP<sup>*</sup>||Parity column address strobe
|-
|14||A6||Address 6
|29||DP<sup>*</sup>||Data parity in
|-
|15||A7||Address 7
|30||V<sub>CC</sub>||+5 VDC
|}
<sup>*</sup> Pins 26, 28 and 29 are [[not connected]] on non-parity SIMMs.

==72-pin SIMMs==
[[Image:Edoram.jpg|thumb|72-pin EDO DRAM SIMM]]
Standard sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB (the standard also defines 3.3&nbsp;V modules with additional address lines and up to 2&nbsp;GB)

With 12 address lines, which can provide a total of 24 address bits, two ranks of chips, and 32-bit data output, the absolute maximum capacity is 2<sup>27</sup> = 128&nbsp;MB.<!-- (32 * 2**(14*2)) / (8*1048576) http://www.pjrc.com/mp3/simm/datasheet.html -->
<!-- Extensive googling has failed to turn up evidence of a 256 MB SIMM.  You can search for it, but in every instance it's a multi-SIMM kit (e.g. 2x128 MB, 4x64 MB) or a mislabeled DIMM such as Sun X7005A 512 MB Memory Kit (picture has two notches, not 1).  Note that in the era when memory meant SIMM, people tended to mis-name the similar-appearing DIMMs in casual conversation. -->

{|class="wikitable"
|+5 V 72-pin SIMM
!Pin #!!Name!!Signal description
|rowspan=37|
!Pin #!!Name!!Signal description
|-
|1||V<sub>SS</sub>||Ground
|37||MDP1<sup>*</sup>||Data parity 1 (MD8..15)
|-
|2||MD0||Data 0
|38||MDP3<sup>*</sup>||Data parity 3 (MD24..31)
|-
|3||MD16||Data 16
|39||V<sub>SS</sub>||Ground
|-
|4||MD1||Data 1
|40||/CAS0||Column address strobe 0
|-
|5||MD17||Data 17
|41||/CAS2||Column address strobe 2
|-
|6||MD2||Data 2
|42||/CAS3||Column address strobe 3
|-
|7||MD18||Data 18
|43||/CAS1||Column address strobe 1
|-
|8||MD3||Data 3
|44||/RAS0||Row address strobe 0
|-
|9||MD19||Data 19
|45||/RAS1<sup>†</sup>||Row address strobe 1
|-
|10||V<sub>CC</sub>||+5 VDC
|46||NC||Not connected <!-- JEDEC says /G (/OE, output enable)on 3.3V SIMMs, but I don't see that:
http://www.icwic.cn/icwic/data/pdf/cd/cd012/140346.pdf
*{{cite web|url=http://doc.chipfind.ru/hanbit/hmd4m32m2ve.htm|title=HMD4M32M2VE (Hanbit) - 16mbyte(4mx32) Dram Simm Edo Mode, 4k Refresh, 3.3v|publisher=doc.chipfind.ru|accessdate=2014-02-11}}
-->
|-
|11||NU [PD5<sup>#</sup>]||Not used [presence detect 5 (3v3)]
|47||/WE||Read/write enable
|-
|12||MA0||Address 0
|48||NC [/ECC<sup>#</sup>]||Not connected [ECC presence (if grounded) (3v3)]
|-
|13||MA1||Address 1
|49||MD8||Data 8
|-
|14||MA2||Address 2
|50||MD24||Data 24
|-
|15||MA3||Address 3
|51||MD9||Data 9
|-
|16||MA4||Address 4
|52||MD25||Data 25
|-
|17||MA5||Address 5
|53||MD10||Data 10
|-
|18||MA6||Address 6
|54||MD26||Data 26
|-
|19||MA10||Address 10
|55||MD11||Data 11
|-
|20||MD4||Data 4
|56||MD27||Data 27
|-
|21||MD20||Data 20
|57||MD12||Data 12
|-
|22||MD5||Data 5
|58||MD28||Data 28
|-
|23||MD21||Data 21
|59||V<sub>CC</sub>||+5 VDC
|-
|24||MD6||Data 6
|60||MD29||Data 29
|-
|25||MD22||Data 22
|61||MD13||Data 13
|-
|26||MD7||Data 7
|62||MD30||Data 30
|-
|27||MD23||Data 23
|63||MD14||Data 14
|-
|28||MA7||Address 7
|64||MD31||Data 31
|-
|29||MA11||Address 11
|65||MD15||Data 15
|-
|30||V<sub>CC</sub>||+5 VDC
|66||NC [/EDO<sup>#</sup>]||Not connected [EDO presence (if grounded) (3v3)]
|-
|31||MA8||Address 8
|67||PD1<sup>x</sup>||Presence detect 1
|-
|32||MA9||Address 9
|68||PD2<sup>x</sup>||Presence detect 2
|-
|33||/RAS3<sup>†</sup>||Row address strobe 3
|69||PD3<sup>x</sup>||Presence detect 3
|-
|34||/RAS2||Row Address Strobe 2
|70||PD4<sup>x</sup>||Presence detect 4
|-
|35||MDP2<sup>*</sup>||Data parity 2 (MD16..23)
|71||NC [PD (ref)<sup>#</sup>]||Not connected [presence detect (ref) (3v3)]
|-
|36||MDP0<sup>*</sup>||Data parity 0 (MD0..7)
|72||V<sub>SS</sub>||Ground
|}
<sup>*</sup> Pins 35, 36, 37 and 38 are not connected on non-parity SIMMs.<ref>[http://www.jedec.org/sites/default/files/docs/4_04_02R8.PDF JEDEC Standard No. 21-C, Section 4.4.2] "72 pin SIMM DRAM Module Family".</ref><br/>
<sup>†</sup> /RAS1 and /RAS3 are only used on two-rank SIMMS: 2, 8, 32, and 128 MB.<br/>
<sup>#</sup> These lines are only defined on 3.3 V modules.<br/>
<sup>x</sup> Presence-detect signals are detailed in JEDEC standard.

==Proprietary SIMMs==

===GVP 64-pin===
Several CPU cards from [[Great Valley Products]] for the [[Commodore International|Commodore]] [[Amiga]] used special 64-pin SIMMs (32 bits wide, 1, 4 or 16&nbsp;MB, 60&nbsp;ns).

===Apple 64-pin===
[[DPRAM|Dual-ported]] 64-pin SIMMs were used in [[Apple Inc.|Apple]] [[Macintosh IIfx]] computers to allow overlapping read/write cycles (1, 4, 8, 16&nbsp;MB, 80&nbsp;ns).<ref>[http://www.lowendmac.com/ii/macintosh-iifx.html Macintosh IIfx].</ref><ref>{{cite book | last = Apple Computer, Inc. | author-link = Apple Computer | title = Guide to the Macintosh Family Hardware | publisher = Addison-Wesley, Inc | year = 1990 | edition = 2nd | page = 230}}</ref>

{|class="wikitable"
|+ 5V 64-pin Mac IIfx SIMM<ref>{{cite book | last = Apple Computer, Inc. | author-link = Apple Computer | title = Guide to the Macintosh Family Hardware | publisher = Addison-Wesley, Inc | year = 1990 | edition = 2nd | pages = 214–222}}</ref>
!Pin #!!Name!!Signal description
|rowspan=33|
!Pin #!!Name!!Signal description
|-
|1||GND||Ground
|33||Q4||Data output bus, bit 4
|-
|2||NC||Not connected
|34||/W4||Write-enable input for RAM IC 4
|-
|3||+5V||+5&nbsp;volts
|35||A8||Address bus, bit 8
|-
|4||+5V||+5&nbsp;volts
|36||NC||Not connected
|-
|5||/CAS||Column address strobe
|37||A9||Address bus, bit 9
|-
|6||D0||Data input bus, bit 0
|38||A10||Address bus, bit 10
|-
|7||Q0||Data output bus, bit 0
|39||A11||Address bus, bit 11
|-
|8||/W0||Write-enable input for RAM IC 0
|40||D5||Data input bus, bit 5
|-
|9||A0||Address bus, bit 0
|41||Q5||Data output bus, bit 5
|-
|10||NC||Not connected
|42||/W5||Write-enable input for RAM IC 5
|-
|11||A1||Address bus, bit 1
|43||NC||Not connected
|-
|12||D1||Data input bus, bit 1
|44||NC||Not connected
|-
|13||Q1||Data output bus, bit 1
|45||GND||Ground
|-
|14||/W1||Write-enable input for RAM IC 1
|46||D6||Data input bus, bit 6
|-
|15||A2||Address bus, bit 2
|47||Q6||Data output bus, bit 6
|-
|16||NC||Not connected
|48||/W6||Write-enable input for RAM IC 6
|-
|17||A3||Address bus, bit 3
|49||NC||Not connected
|-
|18||GND||Ground
|50||D7||Data input bus, bit 7
|-
|19||GND||Ground
|51||Q7||Data output bus, bit 7
|-
|20||D2||Data input bus, bit 2
|52||/W7||Write-enable input for RAM IC 7
|-
|21||Q2||Data output bus, bit 2
|53||/QB||Reserved (parity)
|-
|22||/W2||Write-enable input for RAM IC 2
|54||NC||Not connected
|-
|23||A4||Address bus, bit 4
|55||/RAS||Row address strobe
|-
|24||NC||Not connected
|56||NC||Not connected
|-
|25||A5||Address bus, bit 5
|57||NC||Not connected
|-
|26||D3||Data input bus, bit 3
|58||Q||Parity-check output
|-
|27||Q3||Data output bus, bit 3
|59||/WWP||Write wrong parity
|-
|28||/W3||Write-enable input for RAM IC 3
|60||PDCI||Parity daisy-chain input
|-
|29||A6||Address bus, bit 6
|61||+5V||+5&nbsp;volts
|-
|30||NC||Not connected
|62||+5V||+5&nbsp;volts
|-
|31||A7||Address bus, bit 7
|63||PDCO||Parity daisy-chain output
|-
|32||D4||Data input bus, bit 4
|64||GND||Ground
|}

===HP LaserJet===
72-pin SIMMs with [[HP LaserJet#Upgrading memory of older models|non-standard]] [[Serial presence detect|presence detect]] (PD) connections.

==See also==
*[[Dual in-line package]] (DIP)
*[[Single in-line package]] (SIP)
*[[Zig-zag in-line package]] (ZIP)
*[[Dual in-line memory module]] (DIMM)

==References==
<references/>

==External links==
{{Commons category|SIMM}}
*[https://web.archive.org/web/20120716225721/http://www.edgetechcorp.com/support/installation-manuals/1000%20General%20SIMM%20Ver2(09-04).pdf General SIMM Installation Guide]

{{DRAM}}

[[Category:Computer memory form factor]]