Editing Southbridge (computing)

[[File:Chipset schematic.svg|thumb|300px|A typical north/southbridge layout]]
[[File:IBM ThinkPad T42 Motherboard.jpg|thumb|300px|IBM T42 laptop motherboard with the following labels: CPU (central processing unit), NB (northbridge), GPU (graphics processing unit), and SB (southbridge)]]
{{short description|One of the two chips in the core logic chipset architecture on a PC motherboard}}

On older [[personal computer]] [[motherboard]]s, the '''southbridge''' is one of the two chips in the core logic [[chipset]], handling many of a computer's [[input/output]] functions. The other component of the chipset is the [[Northbridge (computing)|northbridge]], which generally handles high speed onboard communications. 

A southbridge chipset handles functions such as USB, audio, the system firmware, the lower speed PCI/PCIe buses, the IOAPIC interrupt controller, the SATA storage, the historical PATA storage, the NVMe storage, and low speed buses such as [[Industry Standard Architecture|ISA]], [[Low Pin Count|LPC]], [[Serial Peripheral Interface|SPI]], and/or [[Serial Peripheral Interface#Intel's Enhanced Serial Peripheral Interface|eSPI]].<ref>{{Citation |title=What is Southbridge? |date=4 November 2002 |website=Webopedia Computer Dictionary |type=word definition |url=http://www.webopedia.com/TERM/S/Southbridge.html}}.</ref><ref name="Mujtaba">{{Cite web |last=Mujtaba |first=Hassan |date=2019-09-13 |title=Intel Z490, H470 Motherboards For 10th Gen Comet Lake-S CPUs Leaked |url=https://wccftech.com/intel-z490-h470-b460-h410-chipset-motherboards-10th-gen-comet-lake-s-cpu-leak/ |access-date=2020-10-30 |website=Wccftech |language=en-US}}</ref> Different combinations of southbridge and northbridge chips are possible,<ref>{{Citation |title=Chipset: Northbridge and Southbridge |url=http://www.rigacci.org/wiki/doku.php/doc/appunti/hardware/chipset |publisher=Rigacci}}.</ref> but these two kinds of chips are designed to work together.{{Cn|date=June 2024}} There is no industry-wide standard for interoperability between different core logic chipset designs. In the 1990s and early 2000s, the interface between a northbridge and southbridge was the PCI bus. As of 2023, the main bridging interfaces used are [[Direct Media Interface]] ([[Intel]]) and [[PCI Express]] ([[AMD]]).

The southbridge typically implements the slower capabilities of the motherboard in a northbridge-southbridge chipset computer architecture. In systems with [[Intel]] chipsets, the southbridge has been named [[I/O Controller Hub]] (ICH) and later replaced by [[Platform Controller Hub]] chipsets. In older Intel/AMD architectures the southbridge is usually linked to the northbridge, which in turn connected to the CPU. Circa 2004 and onward Intel architectures started to link southbridge directly to the CPU (e.g. via [[Direct Media Interface]]). Through the use of controller-integrated channel circuitry, the northbridge (or CPU itself) can directly link signals from the I/O units to the CPU for data control and access.

As of 2024, most personal computer devices based on Intel or AMD architectures no longer use a set of two chips, and instead have a single chip acting as the 'chipset', for example Intel's Z790 chipset, and a central processing unit.

==Current status==
Due to the push for [[System on a chip|system-on-chip]] (SoC) processors, modern devices increasingly have the northbridge integrated into the CPU [[Die (integrated circuit)|die]] itself;{{Explain|reason=What push for SoC processors? Explain the context.|date=October 2018}} examples are [[Intel]]'s [[Sandy Bridge]]<ref>{{cite web|last =Vatto|first =Kristian|title=Why Ivy Bridge is still Quad-core?|url= http://www.anandtech.com/show/5174/why-ivy-bridge-is-still-quad-core | website = Anandtech |access-date= September 27, 2015}}</ref> and [[AMD]]'s [[AMD Fusion|Fusion]] processors,<ref>{{cite web|last =Stokes|first = Jon |title= With Fusion, AMD's devils are in the details|url= https://arstechnica.com/business/2010/11/with-fusion-amds-devils-are-in-the-details/ | website =Arstechnica|date = 11 November 2010 |access-date=September 27, 2015}}</ref> both released in 2011. 

With the [[Intel 5 Series]] chipset in 2008, the southbridge became redundant and was replaced by the [[Platform Controller Hub]] (PCH) architecture introduced. AMD did the same with the release of their first APUs in 2011, naming the PCH the [[fusion controller hub]] (FCH), which was only used on AMD's APUs until 2017 when it began to be used on AMD's Zen architecture while dropping the FCH name. 

On Intel platforms, all southbridge features and remaining I/O functions are managed by the PCH, which is directly connected to the CPU via the [[Direct Media Interface]] (DMI).<ref>{{cite web|url= http://www.intel.com/content/www/us/en/chipsets/mainstream-chipsets/mobile-chipset-hm57.html |title=Mobile Intel HM57 Express Chipset |publisher=Intel | access-date= 2014-04-21}}</ref> Intel low-power processors (Haswell-U and onward) and ultra low-power processors (Haswell-Y and onward) also integrate an on-package PCH. Based on its [[Chiplet]] design, [[AMD Ryzen]] processors also integrated some southbridge functions, such as some [[USB]] and [[SATA]]/[[NVMe]] interfaces.<ref>{{Cite web|last=Hagedoorn|first=Hilbert|title=AMD Ryzen 3000: New Block diagram about PCIe 4.0 on Matisse and X570 chipset|url=https://www.guru3d.com/news-story/amd-ryzen-3000-new-block-diagram-about-pcie-4-on-matisse-and-x570-chipset.html|access-date=2020-06-12|website=Guru3D.com|date=23 May 2019 |language=en-us}}</ref>

== Etymology ==
The name is derived from representing the architecture in the fashion of a map and was first described as such with the introduction of the [[Conventional PCI|PCI Local Bus]] Architecture in 1991. At Intel, the authors of the PCI specification viewed the PCI local bus as being at the very centre of the PC platform architecture (i.e., at the [[Equator]]).

The [[Northbridge (computing)|northbridge]] extends to the north of the PCI bus backbone in support of CPU, memory/[[CPU cache|cache]], and other performance-critical capabilities. Likewise the southbridge extends to the south of the PCI bus backbone and bridges to less performance-critical I/O capabilities such as the disk interface, audio, etc.

The CPU is located at the top of the map at due north. The CPU is connected to the chipset via a fast bridge (the northbridge) located ''north'' of other system devices as drawn. The northbridge is connected to the rest of the chipset via a slow bridge (the southbridge) located ''south'' of other system devices as drawn.

Although the current PC platform architecture has replaced the PCI bus backbone with faster I/O backbones, the bridge naming convention remains.

== Functionality ==
[[File:Motherboard diagram.svg|thumb|250px|Motherboard diagram, created in 2007, which supports many on-board peripheral functions as well as several expansion slots]]
The functionality found in a contemporary southbridge includes:<ref name="southbridge">{{Citation |title=What is a chipset? |url=http://www.misco.co.uk/content/MODULE/MOTHERBOARDS/WHAT-IS-CHIPSET.HTM |place=[[United Kingdom|UK]] |publisher=Misco}}.</ref><ref name="Mujtaba"/>
* [[PCI bus]]. A south bridge may also include support for [[PCI-X]].
* Low speed [[PCI Express]] (PCIe) interfaces usually for Ethernet and NVMe.
* [[Industry Standard Architecture|ISA bus]] or [[Low Pin Count|LPC bridge]]. ISA slots are no longer provided on more recent motherboards. The LPC bridge provides a data and control path to the [[super I/O]] (the normal attachment for the [[PS/2 port|PS/2]] keyboard and mouse, parallel port, serial port, IR port, and floppy controller).
* [[I2C]] and [[SMBus]] controller.
* [[Direct memory access|DMA]] controller. The [[8237]] DMA controller allows ISA or LPC devices direct access to [[main memory]] without needing help from the CPU.
* [[Programmable interrupt controller|PIC]] and [[I/O APIC]].
* [[Mass storage]] interfaces such as [[Serial ATA|SATA]], [[M.2]], and historical [[Parallel ATA|PATA]]. This typically allows attachment of [[hard drives]] or [[SSDs]].
* [[Real-time clock]].
* [[Programmable interval timer]].
* [[High Precision Event Timer]].
* [[Advanced Configuration and Power Interface|ACPI]] controller or [[Advanced Power Management|APM]] controller.
* [[Serial Peripheral Interface|SPI serial bus]] mostly used for [[firmware]] (e.g., [[BIOS]]/[[UEFI]]) [[Flash memory|flash]] storage access.
* [[Nonvolatile BIOS memory]]. The system [[Nonvolatile BIOS memory|CMOS]] (BIOS configuration memory), assisted by battery supplemental power, creates a limited [[non-volatile]] storage area for BIOS configuration data.
* [[Intel HD Audio]] or [[AC'97]] sound interface.
* [[USB]] interfaces.

Optionally, a southbridge also includes support (onboard discrete chip or southbridge-integrated) for [[Ethernet]], [[Wi-Fi]], [[RAID]], [[Thunderbolt (interface)|Thunderbolt]], and [[Out-of-band management]].

== See also ==
* [[Memory controller]]
* [[Northbridge (computing)]]

== References ==
{{Reflist|40em}}

== External links ==
* {{cite web|url=http://www.informit.com/articles/article.aspx?p=339936| website =InformIT | title = Motherboards & Core-Logic Chipsets: The Deep Stuff > What the North Bridge and South Bridge Do |access-date= November 18, 2010}}

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[[Category:IBM PC compatibles]]
[[Category:Chipsets]]