Editing StrongARM

{{Short description|Family of computer microprocessors}}
{{Other uses|Strongarm (disambiguation){{!}}Strongarm}}
{{Redirect|SA-110|the Finnish military truck|Sisu SA-110}}
{{Use dmy dates|date=February 2022}}
[[Image:DEC StrongARM.jpg|thumb|DEC StrongARM SA-110 microprocessor]]

The '''StrongARM''' is a family of computer [[microprocessor]]s developed by [[Digital Equipment Corporation]] and manufactured in the late 1990s which implemented the [[ARM architecture family|ARM v4]] [[instruction set architecture]].<ref>{{Cite web |title=StrongARM Microprocessor: SA-110 |url=https://datasheets.chipdb.org/Intel/STRONG/SA110.HTM |access-date=2024-07-31 |website=datasheets.chipdb.org}}</ref> It was later acquired by [[Intel]] in 1997 from DEC's own Digital Semiconductor division as part of a settlement of a lawsuit between the two companies over patent infringement.<ref name="Intel-DEC-settlement">{{ cite web | title = Intel, DEC Settle Alpha Chip Dispute | date = 2022-08-11 |orig-date= 1997-10-27 |last= Levine |first= Daniel S. | url = http://www.wired.com/1997/10/intel-dec-settle-alpha-chip-dispute/ | publisher = Wired.com | accessdate = 2022-08-11 |archiveurl = https://web.archive.org/web/20160314015908/http://www.wired.com/1997/10/intel-dec-settle-alpha-chip-dispute/ |archivedate = 2016-03-14 }}</ref> Intel then continued to manufacture it before replacing it with the StrongARM-derived ARM-based follow-up architecture called [[XScale]] in the early 2000s.

==History==
According to Allen Baum, the StrongARM traces its history to attempts to make a low-power version of the [[DEC Alpha]], which DEC's engineers quickly concluded was not possible. They then became interested in designs dedicated to low-power applications which led them to the ARM family. One of the only major users of the ARM for performance-related products at that time was [[Apple Inc.|Apple]], whose [[Apple Newton|Newton]] device was based on the ARM platform. DEC approached Apple wondering if they might be interested in a high-performance ARM, to which the Apple engineers replied "Phhht, yeah. You can't do it, but, yeah, if you could we'd use it."<ref>{{cite interview |first=Allen |last=Baum |interviewer=David Brock |title=Oral History of Allen Baum |date=18 July 2018 |url=https://archive.computerhistory.org/resources/access/text/2018/06/102717165-05-01-acc.pdf |page=60}}</ref>

The StrongARM was a collaborative project between DEC and [[Arm Holdings|Advanced RISC Machines]] to create a faster ARM microprocessor. The StrongARM was designed to address the upper end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer [[personal digital assistant]]s and [[set-top box]]es.<ref name="DTJ">Montanaro, James et al. (1997). [http://www.hpl.hp.com/hpjournal/dtj/vol9num1/vol9num1art5.pdf "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor"] {{Webarchive|url=https://web.archive.org/web/20190101024112/http://www.hpl.hp.com/hpjournal/dtj/vol9num1/vol9num1art5.pdf |date=1 January 2019 }}. ''Digital Technical Journal'', vol. 9, no. 1. pp. 49&ndash;62.</ref><ref>{{cite web | url = http://www.thefreelibrary.com/DIGITAL+TARGETS+SUPERCHARGED+StrongARM+CHIP+AT+CONSUMER+ELECTRONICS...-a017919435 | title = Digital targets supercharged StrongARM chip at consumer electronics market | access-date =7 June 2011 | date = 5 February 1996 | agency = [[PR Newswire]]}}</ref>

Traditionally, the [[semiconductor]] division of DEC was located in [[Massachusetts]]. In order to gain access to the design talent in [[Silicon Valley]], DEC opened a design center in [[Palo Alto, California]]. This design center was led by [[Dan Dobberpuhl]] and was the main design site for the StrongARM project. Another design site that worked on the project was in [[Austin, Texas]] that was created by some ex-DEC designers returning from [[Apple Computer]] and [[Motorola]]. The project was set up in 1995, and quickly delivered their first design, the '''SA-110'''.

DEC agreed to sell StrongARM to Intel as part of a lawsuit settlement in 1997.<ref>{{cite web|url=http://news.cnet.com/2100-1023-204668.html
|title=Intel, Digital settle suit
|first=Erich
|last=Luening
|date=27 October 1997
|work= [[CNet]] news.com
|access-date=29 July 2008}}</ref> Intel used the StrongARM to replace their ailing line of RISC processors, the [[Intel i860|i860]] and [[Intel i960|i960]].

When the semiconductor division of DEC was sold to Intel, many engineers from the Palo Alto design group moved to [[SiByte]], a start-up company designing [[MIPS architecture|MIPS]] [[system-on-a-chip]] (SoC) products for the networking market. The Austin design group spun off to become [[Alchemy (processor)|Alchemy Semiconductor]], another start-up company designing MIPS SoCs for the hand-held market. A new StrongARM core was developed by Intel and introduced in 2000 as the [[XScale]].<ref>{{cite web |url=http://www.mdronline.com/publications/epw/issues/epw_46.html |archive-url=https://web.archive.org/web/20071019213400/http://www.mdronline.com/publications/epw/issues/epw_46.html |title=Embedded Processor Watch #46; 5/4/1999 |archive-date=19 October 2007 |work=mdronline.com}}</ref>

==SA-110==
The SA-110 was the first microprocessor in the StrongARM family. The first versions, operating at 100, 160, and 200&nbsp;MHz, were announced on 5 February 1996.<ref>Digital Equipment Corporation (5 February 1996). "Digital Targets Supercharged StrongARM Chip at Consumer Electronics Market". Press release.</ref> When announced, samples of these versions were available, with volume production slated for mid-1996. Faster 166 and 233&nbsp;MHz versions were announced on 12 September 1996.<ref>Digital Equipment Corporation (12 September 1996). "Digital's StrongARM Chips Pull Away in Embedded Race". Press release.</ref> Samples of these versions were available at announcement, with volume production slated for December 1996. Throughout 1996, the SA-110 was the highest performing microprocessor for portable devices.<ref>Turley, Jim (27 January 1997). "Embedded Vendors Seek Differentiation". ''[[Microprocessor Report]]'', pp. 16&ndash;21.</ref> Towards the end of 1996 it was a leading CPU for internet/intranet appliances and [[thin client]] systems.<ref name="eetimes lead 1996">{{cite news | url=http://www.eetimes.com/electronics-news/4146617/Digital-s-StrongARM-Microprocessors-Take-CPU-Lead-in-Network-Client-Market | title=Digital's StrongARM Microprocessors Take CPU Lead in Network Client Market | work=[[EE Times]] | date=18 November 1996 | access-date=16 March 2012}}</ref> The SA-110's first design win was the [[Apple, Inc.|Apple]] [[MessagePad|MessagePad 2000]].<ref>Turley, Jim (18 November 1996). "Newton First Design Win for StrongARM". ''Microprocessor Report'', p. 5.</ref> It was also used in a number of products including the [[Acorn Computers]] [[Risc PC]] and [[Eidos Interactive|Eidos Optima]] video editing system. The SA-110's lead designers were [[Daniel W. Dobberpuhl]], Gregory W. Hoeppner, Liam Madden, and Richard T. Witek.<ref name="DTJ"/>

===Description===
{{Unreferenced section|date=December 2018}}
The SA-110 had a simple [[microarchitecture]]. It was a [[Scalar processor|scalar]] design that executed instructions [[Out-of-order execution|in-order]] with a five-stage [[classic RISC pipeline]]. The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB and PLL. The IBOX contained hardware that operated in the first two stages of the pipeline such as the [[program counter]]. It fetched, decoded and issued instructions. Instruction fetch occurs during the first stage, decode and issue during the second. The IBOX decodes the more complex instructions in the ARM instruction set by translating them into sequences of simpler instructions. The IBOX also handled branch instructions. The SA-110 did not have [[branch prediction]] hardware, but had mechanisms for their speedy processing.

Execution starts at stage three. The hardware that operates during this stage is contained in the EBOX, which comprises the [[register file]], [[arithmetic logic unit]] (ALU), [[barrel shifter]], [[Binary multiplier|multiplier]] and condition code logic. The register file had three read ports and two write ports. The ALU and barrel shifter executed instructions in a single cycle. The multiplier is not pipelined and has a latency of multiple cycles.

The IMMU and DMMU are [[memory management unit]]s for instructions and data, respectively. Each MMU contained a 32-entry [[CPU cache#Associativity|fully associative]] [[translation lookaside buffer]] (TLB) that can map 4&nbsp;KB, 64&nbsp;KB or 1&nbsp;MB [[Page (computer science)|page]]s. The write buffer (WB) has eight 16-byte entries. It enables the pipelining of stores. The bus interface unit (BIU) provided the SA-110 with an external interface.

The [[Phase-locked loop|PLL]] generates the internal [[clock signal]] from an external 3.68&nbsp;MHz clock signal. It was not designed by DEC, but was contracted to the Centre Suisse d'Electronique et de Microtechnique (CSEM) located in [[Neuchâtel]], [[Switzerland]].

The instruction [[CPU cache|cache]] and data cache each have a capacity of 16&nbsp;KB and are 32-way [[set-associative]] and virtually addressed. The SA-110 was designed to be used with slow (and therefore low-cost) memory and therefore the high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. The caches are responsible for most of the transistor count and they take up half the die area.

The SA-110 contained 2.5 million transistors and is 7.8&nbsp;mm by 6.4&nbsp;mm large (49.92&nbsp;mm<sup>2</sup>). It was fabricated by DEC in its proprietary CMOS-6 process at its Fab 6 [[Semiconductor fabrication plant|fab]] in Hudson, Massachusetts. CMOS-6 was DEC's sixth-generation [[CMOS|complementary metal&ndash;oxide&ndash;semiconductor (CMOS)]] process. CMOS-6 has a 0.35&nbsp;μm feature size, a 0.25&nbsp;μm effective channel length but for use with the SA-110, only three levels of [[aluminium interconnect]]. It used a power supply with a variable voltage of 1.2 to 2.2 [[volt]]s (V) to enable designs to find a balance between power consumption and performance (higher voltages enable higher clock rates). The SA-110 was packaged in a 144-pin [[Thin Quad Flat Pack|thin quad flat pack]] (TQFP).

==SA-1100==
The SA-1100 was a derivative of the SA-110 developed by DEC. Announced in 1997, the SA-1100 was targeted for portable applications such as PDAs and differs from the SA-110 by providing a number of features that are desirable for such applications. To accommodate these features, the data cache was reduced in size to 8&nbsp;KB.

The extra features are integrated memory, [[PCMCIA]], and color LCD controllers connected to an on-die system bus, and five serial I/O channels that are connected to a peripheral bus attached to the system bus. The memory controller supported FPM and EDO DRAM, SRAM, flash, and ROM. The PCMCIA controller supports two slots. The memory address and data bus is shared with the PCMCIA interface. Glue logic is required. The serial I/O channels implement a slave USB interface, a [[Synchronous Data Link Control|SDLC]], two [[UART]]s, an [[IrDA]] interface, a MCP, and a [[Synchronous Serial Port|synchronous serial port]].

The SA-1100 had a companion chip, the SA-1101. It was introduced by Intel on 7 October 1998.<ref>Intel Corporation (7 October 1998). "Intel Introduces StrongARM Products for PC Companions". Press release.</ref> The SA-1101 provided additional peripherals to complement those integrated on the SA-1100 such as a video output port, two [[PS/2 connector|PS/2]] ports, a USB controller and a PCMCIA controller that replaces that on the SA-1100. Design of the device started by DEC, but was only partially complete when acquired by Intel, who had to finish the design. It was fabricated at DEC's former [[Hudson, Massachusetts]] fabrication plant, which was also sold to Intel.<ref>{{cite web|url=http://www.mdronline.com/publications/epw/issues/epw_17.html|title=The Linley Group - The industry's leading experts in communications semiconductor markets|work=mdronline.com}}</ref>

The SA-1100 contained 2.5 million transistors and measured 8.24&nbsp;mm by 9.12&nbsp;mm (75.15&nbsp;mm<sup>2</sup>). It was fabricated in a 0.35&nbsp;μm CMOS process with three levels of [[aluminium interconnect]] and was packaged in a 208-pin TQFP.<ref name="ISSCC-1998">Stephany, R. et al. (1998). "A 200MHz 32b 0.5W CMOS RISC Microprocessor". ''ISSCC Digest of Technical Papers'', pp. 238&ndash;239, 443.</ref>

One of the early recipients of this processor was-ill-fated [[Psion netBook]] and its more consumer oriented sibling [[Psion Series 7]].

==SA-1110==
The SA-1110 was a derivative of the SA-110 developed by Intel. It was announced on 31 March 1999, positioned as an alternative to the SA-1100.<ref>Intel Corporation (31 March 1999). "Intel StrongARM Processor, Companion Chip Optimized For Handheld Computing Devices". Press release.</ref> At announcement, samples were set for June 1999 and volume later that year. Intel discontinued the SA-1110 in early 2003.<ref>Martyn Williams (14 February 2003). "Intel puts StrongArm on death row". ''[[InfoWorld]]''.</ref> The SA-1110 was available in 133 or 206&nbsp;MHz versions. It differed from the SA-1100 by featuring support for 66&nbsp;MHz (133&nbsp;MHz version only) or 103&nbsp;MHz (206&nbsp;MHz version only) [[SDRAM]].<ref>{{cite web|url=http://www.mdronline.com/publications/epw/issues/epw_42.html|title=The Linley Group - The industry's leading experts in communications semiconductor markets|work=mdronline.com}}</ref> Its companion chip, which provided additional support for peripherals, was the SA-1111. The SA-1110 was packaged in a 256-pin [[Ball grid array|micro ball grid array]]. It was used in mobile phones, personal data assistants (PDAs) such as the Compaq (later HP) [[iPAQ]] and HP [[Jornada (PDA)|Jornada]], the Sharp SL-5x00 Linux Based Platforms and the [[Simputer]].<ref>{{cite web|url=http://www.mdronline.com/publications/epw/issues/epw_101.html|title=The Linley Group - The industry's leading experts in communications semiconductor markets|work=mdronline.com}}</ref> It was also used to run the Intel Web Tablet, a tablet device that is considered potentially the first to introduce large screen, portable web browsing. Intel dropped the product just prior to launch in 2001.

==SA-1500==
The SA-1500 was a derivative of the SA-110 developed by DEC initially targeted for [[set-top box]]es.<ref>Rick Boyd-Merrit; Peter Clarke (24 July 1998). [http://www.eetimes.com/news/98/1018news/strongarm.html "Intel to reveal details on StrongARM chip"]. ''[[EE Times]]''.</ref><ref>Prashant P. Gandhi (18 August 1998). [http://www.hotchips.org/archives/hc10/3_Tue/HC10.S8/HC10.8.3.pdf "SA-1500: A 300&nbsp;MHz RISC CPU with Attached Media Processor"] {{Webarchive|url=https://web.archive.org/web/20081120010823/http://www.hotchips.org/archives/hc10/3_Tue/HC10.S8/HC10.8.3.pdf |date=20 November 2008 }}. [[Hot Chips|Hot Chips&nbsp;10]].</ref> It was designed and manufactured in low volumes by DEC but was never put into production by Intel. The SA-1500 was available at 200 to 300&nbsp;MHz. The SA-1500 featured an enhanced SA-110 core, an on-chip [[coprocessor]] called the ''Attached Media Processor'' (AMP), and an on-chip SDRAM and I/O bus controller. The SDRAM controller supported 100&nbsp;MHz SDRAM, and the I/O controller implemented a 32-bit I/O bus that may run at frequencies up to 50&nbsp;MHz for connecting to peripherals and the SA-1501 companion chip.

The AMP implemented a long-instruction-word instruction set containing instructions designed for multimedia, such as integer and floating-point [[multiply–accumulate operation]]s and [[single instruction, multiple data|SIMD]] arithmetic. Each long-instruction word is 64&nbsp;bits wide and specifies an arithmetic operation and a branch or a load/store. Instructions operate on operands from a 64-entry 36-bit register file, and on a set of control registers. The AMP communicates with the SA-110 core via an on-chip bus and it shares the data cache with the SA-110. The AMP contained an ALU with a shifter, a branch unit, a load/store unit, a multiply–accumulate unit, and a [[single-precision floating-point format|single-precision]] [[floating-point unit]]. The AMP supported user-defined instructions via a 512-entry writable control store.<ref name="microprocessorreport19971208_sa1500">{{ cite magazine | url=https://www.cecs.uci.edu/~papers/mpr/MPR/19971208/111603.pdf | title=StrongARM-1500 Grapples With MPEG-2 | magazine=[[Microprocessor Report]] | last1=Turley | first1=Jim | date=8 December 1997 | access-date=14 March 2024 }}</ref>

The SA-1501 companion chip provided additional video and audio processing capabilities and various I/O functions such as PS/2 ports, a parallel port, and interfaces for various peripherals.

The SA-1500 contains 3.3 million transistors and measures 60&nbsp;mm<sup>2</sup>. It was fabricated in a 0.28&nbsp;μm CMOS process. It used a 1.5 to 2.0&nbsp;V internal power supply and 3.3&nbsp;V I/O, consuming less than 0.5&nbsp;W at 100&nbsp;MHz and 2.5&nbsp;W at 300&nbsp;MHz. It was packaged in a 240-pin metal [[quad flat package]] or a 256-ball [[PBGA|plastic ball grid array]].

==StrongARM latch==
The '''StrongARM latch''' is an [[flip-flop (electronics)|electronic latch]] circuit topology first<ref name=Abidi>{{cite book |last1=Abidi |first1={{abbr|A.|Asad}} |author-link1=Asad Abidi |last2=Hao Xu |title=Proceedings of the IEEE 2014 Custom Integrated Circuits Conference |chapter=Understanding the regenerative comparator circuit |date=15–17 September 2014 |pages=1–8 |publisher=[[Institute of Electrical and Electronics Engineers|IEEE]] |doi=10.1109/CICC.2014.6946003 |isbn=978-1-4799-3286-3 |s2cid=329565 }}</ref><ref name=Razavi>{{cite journal |last1=Razavi |first1={{abbr|B.|Behzad}} |author-link1=Behzad Razavi |date=2015-06-22 |title=The StrongARM Latch |journal=IEEE Solid-State Circuits Magazine |publisher=[[Institute of Electrical and Electronics Engineers|IEEE]] |volume=7 |issue=2 |pages=12–17 |doi=10.1109/MSSC.2015.2418155 |s2cid=9477992 }}</ref> proposed by [[Toshiba]] engineers Tsuguo Kobayashi ''et al.''<ref>{{cite book |last1=Kobayashi |first1={{abbr|T.|Tsuguo}} |last2=Nogami |first2={{abbr|K.|Kazutaka}} |last3=Shirotori |first3={{abbr|T.|Tsukasa}} |last4=Fujimoto |first4={{abbr|Y.|Yukihiro}} |last5=Watanabe |first5={{abbr|O.|Osamu}} |title=1992 Symposium on VLSI Circuits Digest of Technical Papers |chapter=A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture |date=4–6 June 1992 |publisher=[[Institute of Electrical and Electronics Engineers|IEEE]] |pages=28–29 |doi=10.1109/VLSIC.1992.229252 |isbn=0-7803-0701-1 |s2cid=67412709 }}</ref> and got significant attention after being used in StrongARM microprocessors.<ref name=Abidi /><ref name=Razavi /> It is widely used as a [[sense amplifier]], a [[comparator]], or just a robust latch with high sensitivity.<ref name=Abidi /><ref name=Razavi />

==References==
{{Reflist}}

==Further reading==
* Halfhill, Tom R. (19 April 1999). "Intel Flexes StrongArm With New Chips". ''[[Microprocessor Report]]''.
* Litch, Tim; Slaton, Jeff (March/April 1998). "StrongARMing Portable Communications". ''[[IEEE Micro]]''. pp.&nbsp;48&ndash;55.
* Santhanam, S. et al. (November 1998). "A low-cost, 300-MHz, RISC CPU with attached media processor". ''IEEE Journal of Solid-State Circuits'', vol. 33, no. 11. pp.&nbsp;1829&ndash;1839.
* Turley, Jim (13 November 1995). "StrongArm Punches Up ARM Performance". ''[[Microprocessor Report]]''.
* Turley, Jim (15 September 1997). "SA-1100 Puts PDA on a Chip". ''[[Microprocessor Report]]''.
* Witek, Rich; Montanaro, James (1996). "StrongARM: A high-performance ARM processor". ''Proceedings of COMPCON '96'', pp.&nbsp;188&ndash;191.

{{Digital Equipment Corporation}}
{{Intel processors|discontinued}}

[[Category:32-bit microprocessors]]
[[Category:ARM processors]]
[[Category:DEC microprocessors]]
[[Category:Intel microprocessors]]
[[Category:ARM architecture]]