Editing Tejas and Jayhawk

'''Tejas''' was a code name for [[Intel Corporation|Intel]]'s [[microprocessor]], which was to be a successor to the latest [[Pentium 4]] with the [[Pentium 4#Prescott|Prescott]] core and was sometimes referred to as '''Pentium V'''.<ref name="dat inquiry" /> '''Jayhawk''' was a code name for its [[Xeon]] counterpart. The cancellation of the processors in May 2004 underscored Intel's historical transition of its focus on single-core processors to [[multi-core]] processors.

==History==
In early 2003, Intel showed Tejas and a plan to release it sometime in 2004 with possible delays into 2005. Its development however, was cancelled on May 7, 2004.<ref>{{Cite web |date=2004-05-07 |title=Intel cancels Tejas, moves to dual-core designs |url=https://www.eetimes.com/intel-cancels-tejas-moves-to-dual-core-designs/ |website=EETimes}}</ref> Analysts attribute these issues to heat and power consumption problems due to Intel's goal of reaching ever higher clock speeds, at the detriment of work done per clock (and therefore performance per clock). This was already the case with Prescott and its mediocre performance increase over [[Pentium 4#Northwood|Northwood]] despite higher clock speeds, not to mention heavy competition from [[Advanced Micro Devices]] with their [[Athlon 64]]. Prescott was supposed to attain >5&nbsp;GHz speeds with ease, yet this was not possible due to physical limitations such as heat generated and power consumed at ambient temperatures (the "power wall"). Tejas went even further ahead with this paradigm, with Intel targeting 10&nbsp;GHz [[clock speed]]s by 2011 trying to fulfill the prediction made by [[Andrew  Grove]] in his keynote speech at the 1996 [[COMDEX|COMDEX/Fall]].<ref>{{Cite web |last=Grove |first=Andrew S |title=Intel Keynote Transcript |url=https://www.intel.com/pressroom/archive/speeches/ag111896.htm |access-date=2024-11-29 |website=www.intel.com}}</ref> Soon enough it was clear this represented a dead end.

This cancellation reflected Intel's intention to focus on dual-core chips for the [[Itanium]] platform. With respect to [[desktop computer|desktop]] processors, Intel's development efforts shifted to the [[Pentium M (microarchitecture)|Pentium M microarchitecture]] (itself a derivative of the [[P6 (microarchitecture)|P6 microarchitecture]] last used in the [[Pentium III]]) used in the [[Centrino]] notebook platform, which offered greatly improved performance per watt compared to Prescott and other [[NetBurst]] designs. The result of modernizing the P6 microarchitecture was the [[Intel Core|Core]] processor line, and later the [[Intel Core 2|Core 2]] line, offering Intel's first native dual core products for desktops and [[laptops]] while regaining the performance crown<ref>{{Cite web |last=Shimpi |first=Anand Lal |title=Intel's Core 2 Extreme & Core 2 Duo: The Empire Strikes Back |url=https://www.anandtech.com/show/2045 |access-date=2023-06-24 |website=www.anandtech.com}}</ref> back from AMD.

This defined the end for the NetBurst architecture, with Core setting the foundation and path for power efficient architectures that followed along the [[Tick–tock model]]. Although NetBurst was a dead end for the company, its concepts were later reused and repurposed<ref>{{Cite web |date=2022-06-17 |title=Intel's Netburst: Failure is a Foundation for Success |url=https://chipsandcheese.com/2022/06/17/intels-netburst-failure-is-a-foundation-for-success/ |access-date=2023-06-24 |website=Chips and Cheese |language=en-US}}</ref> in [[Sandy Bridge]].

To bridge the gap left by Tejas' cancellation in the x86 market, Intel did one last revision to NetBurst, codenamed [[Pentium 4#Cedar Mill|Cedar Mill]] (single core) and Presler (dual core).

==Design and microarchitecture==
Tejas and Jayhawk were to make several improvements on the Pentium 4's [[NetBurst|NetBurst microarchitecture]]. Tejas was originally to be built on a [[90 nm]] process, later moving to a [[65 nm]] process. The 90 nm version of the processor was reported to have 1 MB L2 [[CPU cache|cache]], while the 65&nbsp;nm chip would increase the cache to 2 MB. There was also to be a [[dual core]] version of Tejas called ''Cedarmill'' (or ''Cedar Mill'' depending on the source). This ''Cedarmill'' should not be confused with the 65 nm Cedar Mill-based Pentium 4, which appears to be what the codename was recycled for.
[[File:Intel Jayhawk Thermal Sample Chip.jpg|thumb|A thermal sample of an Intel Jayhawk CPU, with the [[Sspec]] QBGC]]
The [[trace cache]] capacity would likely have been increased, and the number of pipeline stages was increased to between 40 and 50 stages.<ref name="tweakers">[http://tweakers.net/reviews/740/chip-magicians-at-work-patching-at-45nm.html Chip magicians at work: patching at 45nm]</ref> There would have been an improved version of [[Hyper-Threading]], as well as a new version of [[Streaming SIMD Extensions|SSE]], which was later backported to the Intel Core 2 series and named [[SSSE3]]. Tejas was slated to operate at frequencies of 7 [[GHz]]<ref name="dat inquiry">{{cite web|last=Dutton|first=Paul|title=Pentium V will launch with 64-bit Windows Elements|url=http://www.theinquirer.net/inquirer/news/1035334/pentium-v-will-launch-with--64-bit-windows-elements|archive-url=https://web.archive.org/web/20090511145152/http://www.theinquirer.net/inquirer/news/1035334/pentium-v-will-launch-with--64-bit-windows-elements|url-status=unfit|archive-date=May 11, 2009|publisher=The Inquirer|access-date=31 March 2013}}</ref> or higher. However, it's likely that Tejas wouldn't have had linear performance scaling, as it would on average have executed fewer instructions per clock cycle due to more pipeline bubbles from branch mispredicts and data cache misses. Also, it would have run hotter as well with a [[Thermal design power|TDP]] much higher than the Prescott core of Pentium 4. The CPU was cancelled late in its development after it had reached its [[tapeout]] phase.<ref name="tweakers" />

Initial claims reported early samples of single core 90 nm Tejas running at 2.8 GHz and rated for 150 W TDP on the [[LGA 775]] socket,<ref name="anandtech">{{Cite news|url=http://www.anandtech.com/show/1217|title=Covert Ops in Taiwan - Intel Tejas & Socket 775 Unveiled|last=Shimpi|first=Anand Lal|access-date=2016-12-01}}</ref> a notable increase over single core 90 nm Prescott (Pentium 4 521, 2.8 GHz, 84 W TDP)<ref>{{Cite news|url=http://ark.intel.com/products/27461/Intel-Pentium-4-Processor-521-supporting-HT-Technology-1M-Cache-2_80-GHz-800-MHz-FSB|title=Intel® Pentium® 4 Processor 521 supporting HT Technology (1M Cache, 2.80 GHz, 800 MHz FSB) Specifications|newspaper=Intel® ARK (Product Specs)|access-date=2016-12-01}}</ref> and higher than 90&nbsp;nm dual core Smithfield (Pentium D 820, 2.8 GHz, 95 W TDP).<ref>{{Cite news|url=http://ark.intel.com/products/27512/Intel-Pentium-D-Processor-820-2M-Cache-2_80-GHz-800-MHz-FSB|title=Intel® Pentium® D Processor 820 (2M Cache, 2.80 GHz, 800 MHz FSB) Specifications|newspaper=Intel® ARK (Product Specs)|access-date=2016-12-01}}</ref> In contrast, 65 nm dual core Core 2 Duo processors had a maximum of 65 W TDP (E6850, 3.00&nbsp;GHz)<ref>{{Cite news|url=http://ark.intel.com/products/30785/Intel-Core2-Duo-Processor-E6850-4M-Cache-3_00-GHz-1333-MHz-FSB|title=Intel® Core™2 Duo Processor E6850 (4M Cache, 3.00 GHz, 1333 MHz FSB) Specifications|newspaper=Intel® ARK (Product Specs)|access-date=2016-12-01}}</ref> while being much more efficient with markedly higher performance per clock.

However, the existence of [[engineering sample]]s have been challenged and no source indicates that tape-out of Tejas ever existed - the sample shown in the [[AnandTech]] article <ref name="anandtech" /> being a Prescott B0 ES.<ref>{{Cite web|url=https://twitter.com/d0cTB/status/1039585378792099842|author=Samuel Demeulemeester|date=2018-09-11|access-date=2018-09-12|title=J'ai enfin résolu un mystère vieux de 15 ans : ce post de [anandtech] qui disait en janvier [2004] avoir une photo de Tejas alors que mes sources affirmaient que Tejas n'avait jamais tape-out. J'ai retrouvé le CPU ... et c'est un Prescott B0 ES.|trans-title=I finally solved a 15-years-old mystery: this anandtech post saying in January [2004] to have a photograph of Tejas whereas my sources stated that Tejas was never tape-out. I found the CPU ... and it's a Prescott B0 ES.}}</ref> Most probably only thermal samples of Tejas were produced.

== See also ==
* [[Mac transition to Intel processors]]

==References==
{{Reflist}}

===General===
*{{cite news |last1=Flynn |first1=Laurie J. |title=Intel Halts Development Of 2 New Microprocessors |url=https://www.nytimes.com/2004/05/08/business/intel-halts-development-of-2-new-microprocessors.html |work=The New York Times |date=8 May 2004}}
*{{cite web |last1=Shilov |first1=Anton |title=Intel to Cancel NetBurst, Pentium 4, Xeon Evolution |url=http://www.xbitlabs.com/news/cpu/display/20040507000306.html |website=Xbit |archive-url=https://web.archive.org/web/20150422234613/http://www.xbitlabs.com/news/cpu/display/20040507000306.html |archive-date=April 22, 2015 |date=May 7, 2004}}
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{{Intel processors|netburst}}

[[Category:Intel x86 microprocessors]]

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